From nobody Tue Jun 30 05:22:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78509C4332F for ; Mon, 24 Jan 2022 20:38:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387195AbiAXUgg (ORCPT ); Mon, 24 Jan 2022 15:36:36 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:54008 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379804AbiAXUMl (ORCPT ); Mon, 24 Jan 2022 15:12:41 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 510AFB810AF; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF883C340EB; Mon, 24 Jan 2022 20:12:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055158; bh=46GvYvu2qBY0XJLufv8o7VnMQWHTSSvKJFHbggT3hWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XzqZtHU43pqSF9cnPOVi8OzU/ekycmEQngryg7+eDdRwKqRJX2qpAum18krWHJGuf 5GqY3AfzVo+a5osEltJIsNqoz6lIsgLpVcAImdP7V5wvCkHZEsK7iswC2qVdhLy5NB TVv3rzPluMu3sGx9D/eX39AR5Evih3nlB6i1DFMJBB1iTYunHgWMUQqNnqmvHxTP7U PtzOuGJV0TEQPEzosRtaaa+/2Gl6FA9rCQ6ZIY6zfmyPyhL9m6G4sxfdU8DNBcARDt c5IYIPwMeWVuEfg5J6eKvKjZ2sTsQsXeZi9lLj5n+YScKJgy/UXjuAwmYEyhhScvpL bUOkTXBBFCMSg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hc-002Y3f-0D; Mon, 24 Jan 2022 20:12:36 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v4 01/10] dt-bindings: arm-pmu: Document Apple PMU compatible strings Date: Mon, 24 Jan 2022 20:12:22 +0000 Message-Id: <20220124201231.298961-2-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As we are about to add support fur the Apple PMUs, document the compatible strings associated with the two micro-architectures present in the Apple M1. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 981bac451698..7a04b8aaaec3 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,firestorm-pmu + - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu --=20 2.30.2 From nobody Tue Jun 30 05:22:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51B4BC4167E for ; Mon, 24 Jan 2022 20:38:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387177AbiAXUge (ORCPT ); Mon, 24 Jan 2022 15:36:34 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:54010 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379805AbiAXUMl (ORCPT ); Mon, 24 Jan 2022 15:12:41 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 90BFFB8122D; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41152C340EF; Mon, 24 Jan 2022 20:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055158; bh=KnKaDKP2ZmunzG4S4wREZKGTAqqogy6WlIrJ0BuxmmM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dd+4KutZ2rMWteOoVnL+hn4rMU3MN1zhYmpoIZTsqB2KslfGyV/f3jOzgCse/psBF CLm9IoNlrykTNUZHDOkSYl21RUwXi6RlTRXJHtkkStT4q+zO/2C5bfIza8pBXWsRUs IgSY3CSoWdKaAjdQ+BlMKDuDCXZqdj/BpTNwN4qHgl4fpF+R5mYiuI1lU3NLW+TMvM Ji7s1SPGEJ/rpEbU+UHH0btr9MkiWHBCBGzSlAp9/WtcSYQ4TndRDZqtWnIqnUacxI 0kjLfzyLS+CD0zPdTBqtsnCkVo/Y8e/zFnHFuz/hbPp6wMg5VPLZOpNkmLhFFstwwQ Yif6vB3NIQvWw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hc-002Y3f-9x; Mon, 24 Jan 2022 20:12:36 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v4 02/10] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Date: Mon, 24 Jan 2022 20:12:23 +0000 Message-Id: <20220124201231.298961-3-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC. We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/apple,aic.yaml | 2 ++ include/dt-bindings/interrupt-controller/apple-aic.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.= yaml index 97359024709a..c7577d401786 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU =20 The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include= /dt-bindings/interrupt-controller/apple-aic.h index 604f2bb30ac0..bf3aac0e5491 100644 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -11,5 +11,7 @@ #define AIC_TMR_HV_VIRT 1 #define AIC_TMR_GUEST_PHYS 2 #define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 =20 #endif --=20 2.30.2 From nobody Tue Jun 30 05:22:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AD0DC46467 for ; Mon, 24 Jan 2022 20:38:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386103AbiAXUfK (ORCPT ); Mon, 24 Jan 2022 15:35:10 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:54018 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348693AbiAXUMl (ORCPT ); Mon, 24 Jan 2022 15:12:41 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D3CE8B8123F; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83020C340F5; Mon, 24 Jan 2022 20:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055158; bh=LIpzrBypwYEGVNUjiOpGMHuLMUB4NRzeRBE/q+tX41U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O0w4JTLS/QPzG+PD1NU35JZbHIr5W+1sR2XF3TomuspTnLcw1SSE95XTSH+9A+aYA EEwhHMGpY1pSBYOWxDLDh6rm3SrBM4FCg96UgZwnnLlcb1LirMecVjvManY5yQfHng pkMggytohHcloxokTUvb5xlqvSGAzrxuR0chBgQVwPqJJubsUvGsZigL/Gsk5FJna3 04un9rXI/o6KX674qY5mFYorTU3mx61hJOU/uHIbXl0DAkcyDMJjfWsQJsa4aPTlz4 v6XzxNs+7sEE+O0WR8HUN/WYnizhQxszb/iUc8M6chuTwZyZ912WpN3yokS026Wc8I QuzdNqDrCrCMA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hc-002Y3f-JF; Mon, 24 Jan 2022 20:12:36 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 03/10] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts Date: Mon, 24 Jan 2022 20:12:24 +0000 Message-Id: <20220124201231.298961-4-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Signed-off-by: Marc Zyngier --- .../interrupt-controller/apple,aic.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.= yaml index c7577d401786..d97683eb2c54 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -70,6 +70,33 @@ properties: power-domains: maxItems: 1 =20 + affinities: + type: object + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + properties: + fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - cpus + required: - compatible - '#interrupt-cells' --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93737C433F5 for ; Mon, 24 Jan 2022 21:57:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1575484AbiAXVvr (ORCPT ); Mon, 24 Jan 2022 16:51:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357676AbiAXVRp (ORCPT ); Mon, 24 Jan 2022 16:17:45 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC493C067A6E; Mon, 24 Jan 2022 12:12:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0BC76B8122C; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B54FDC340E7; Mon, 24 Jan 2022 20:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055158; bh=W9bLhuCJW47SQum5mYpyzLakoC0n72L/swVRyAU1Tlw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PxC7VtuDykjvOCkP/ZTSBM4PMAW7Hzb7JVMeb8I0apNeLyN8OtHg7hA4Xbh2Z0gES umCDV8y7OVPR8RYu7XJ5y24796g9fUGawBl8PpuU/3FIhdRoehEvQVF72SSQRK9gvm cEV58X3hhnbNmIxw7neTauKQlyJt+w/COjDCxhcxYdXiSZQElBi4Wt5F8U69m3iQyW 0xbQJfgZnWKUM1Dw0r8kLa3GMkxBM9wZvnGq2vQ4k3uo6DOmmabCDc6gQE3t0kpELF e/4k5P8jSHYci75+7OYyYeZMXCOciAAQNxbTWBRv/+EQcZS4mfakc2uWr1+ezSkANu 6gYyi3AxBjQKg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hc-002Y3f-SB; Mon, 24 Jan 2022 20:12:36 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 04/10] irqchip/apple-aic: Parse FIQ affinities from device-tree Date: Mon, 24 Jan 2022 20:12:25 +0000 Message-Id: <20220124201231.298961-5-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, parse the affinities kindly provided in the device-tree. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-apple-aic.c | 49 +++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 2543ef65825b..2d31ac605573 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -177,6 +177,9 @@ struct aic_irq_chip { void __iomem *base; struct irq_domain *hw_domain; struct irq_domain *ipi_domain; + struct { + cpumask_t aff; + } *fiq_aff[AIC_NR_FIQ]; int nr_hw; int ipi_hwirq; }; @@ -794,12 +797,50 @@ static struct gic_kvm_info vgic_info __initdata =3D { .no_hw_deactivation =3D true, }; =20 +static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node= *aff) +{ + int i, n; + u32 fiq; + + if (of_property_read_u32(aff, "fiq-index", &fiq) || + WARN_ON(fiq >=3D AIC_NR_FIQ) || ic->fiq_aff[fiq]) + return; + + n =3D of_property_count_elems_of_size(aff, "cpus", sizeof(u32)); + if (WARN_ON(n < 0)) + return; + + ic->fiq_aff[fiq] =3D kzalloc(sizeof(ic->fiq_aff[fiq]), GFP_KERNEL); + if (!ic->fiq_aff[fiq]) + return; + + for (i =3D 0; i < n; i++) { + struct device_node *cpu_node; + u32 cpu_phandle; + int cpu; + + if (of_property_read_u32_index(aff, "cpus", i, &cpu_phandle)) + continue; + + cpu_node =3D of_find_node_by_phandle(cpu_phandle); + if (WARN_ON(!cpu_node)) + continue; + + cpu =3D of_cpu_node_to_id(cpu_node); + if (WARN_ON(cpu < 0)) + continue; + + cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff); + } +} + static int __init aic_of_ic_init(struct device_node *node, struct device_n= ode *parent) { int i; void __iomem *regs; u32 info; struct aic_irq_chip *irqc; + struct device_node *affs; =20 regs =3D of_iomap(node, 0); if (WARN_ON(!regs)) @@ -833,6 +874,14 @@ static int __init aic_of_ic_init(struct device_node *n= ode, struct device_node *p return -ENODEV; } =20 + affs =3D of_get_child_by_name(node, "affinities"); + if (affs) { + struct device_node *chld; + + for_each_child_of_node(affs, chld) + build_fiq_affinity(irqc, chld); + } + set_handle_irq(aic_handle_irq); set_handle_fiq(aic_handle_fiq); =20 --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2FBFC433F5 for ; Mon, 24 Jan 2022 21:57:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1575466AbiAXVvp (ORCPT ); Mon, 24 Jan 2022 16:51:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1450006AbiAXVRn (ORCPT ); Mon, 24 Jan 2022 16:17:43 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93E07C067A6C; Mon, 24 Jan 2022 12:12:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5A80EB81239; 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SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-apple-aic.c | 34 +++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 2d31ac605573..9daa28c55fa1 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -155,7 +155,7 @@ #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4) #define UPMSR_IACT BIT(0) =20 -#define AIC_NR_FIQ 4 +#define AIC_NR_FIQ 6 #define AIC_NR_SWIPI 32 =20 /* @@ -416,16 +416,15 @@ static void __exception_irq_entry aic_handle_fiq(stru= ct pt_regs *regs) aic_irqc->nr_hw + AIC_TMR_EL02_VIRT); } =20 - if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) = =3D=3D - (FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) { - /* - * Not supported yet, let's figure out how to handle this when - * we implement these proprietary performance counters. For now, - * just mask it and move on. - */ - pr_err_ratelimited("PMC FIQ fired. Masking.\n"); - sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT, - FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF)); + if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) { + int irq; + if (cpumask_test_cpu(smp_processor_id(), + &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff)) + irq =3D AIC_CPU_PMU_P; + else + irq =3D AIC_CPU_PMU_E; + generic_handle_domain_irq(aic_irqc->hw_domain, + aic_irqc->nr_hw + irq); } =20 if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) =3D=3D= UPMCR0_IMODE_FIQ && @@ -465,7 +464,18 @@ static int aic_irq_domain_map(struct irq_domain *id, u= nsigned int irq, handle_fasteoi_irq, NULL, NULL); irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); } else { - irq_set_percpu_devid(irq); + int fiq =3D hw - ic->nr_hw; + + switch (fiq) { + case AIC_CPU_PMU_P: + case AIC_CPU_PMU_E: + irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff); + break; + default: + irq_set_percpu_devid(irq); + break; + } + irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data, handle_percpu_devid_irq, NULL, NULL); } --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AAC6C3526D for ; Mon, 24 Jan 2022 22:04:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1578750AbiAXWDg (ORCPT ); Mon, 24 Jan 2022 17:03:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377195AbiAXVRp (ORCPT ); Mon, 24 Jan 2022 16:17:45 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E4FAC067A6F; Mon, 24 Jan 2022 12:12:42 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8F7C9B8119E; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51A69C340EA; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055159; bh=D4DFxQ0NvYaCCiIOskF2Q4DtYSIOrAhdQyICBlG0lyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZX8JrGGGuabGiXs84XsSIs0Nd2v6F67VtiUBhCwLEHDFnmRkhmuWl2kbC27OFWRDt vqKP+5qVGHVfZRibu/qZCN6xbHPJrFlkPn/75pN0juYXr3wwZ8Hd+vXi8d+BSZutP+ URFMEb3ap4Rmm/xEtJ0zP2J/PAnqQu8NjG060y6ZhFoE1J5LQSt0bsOqt3K6685n3q FIscOUEoOHUz+d6CoRmOLVs4Fuen+phkax1vKYwUQ2n40cy3koNthusFkX3fbyPQ7j aK/ciNZk6ttAHlwgynsD1kS2eKXYyPlSU/VHPpK25R+uec2578kDXuFz6lWxAGeDOn l2olM/LgT4tFA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hd-002Y3f-Dh; Mon, 24 Jan 2022 20:12:37 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 06/10] arm64: dts: apple: Add t8103 PMU interrupt affinities Date: Mon, 24 Jan 2022 20:12:27 +0000 Message-Id: <20220124201231.298961-7-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The two PMU pseudo interrupts have specific affinities. One set is affine to the small cores, and the other set affine to the big ones. Signed-off-by: Marc Zyngier --- arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 19afbc91020a..ca856f9955d8 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -213,6 +213,18 @@ aic: interrupt-controller@23b100000 { interrupt-controller; reg =3D <0x2 0x3b100000 0x0 0x8000>; power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + fiq-index =3D ; + cpus =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + p-core-pmu-affinity { + fiq-index =3D ; + cpus =3D <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; }; =20 pmgr: power-management@23b700000 { --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF44FC433F5 for ; Mon, 24 Jan 2022 20:38:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387219AbiAXUgk (ORCPT ); Mon, 24 Jan 2022 15:36:40 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:39684 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347369AbiAXUMk (ORCPT ); Mon, 24 Jan 2022 15:12:40 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2C44261446; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CF9AC340EC; Mon, 24 Jan 2022 20:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055159; bh=YaKveBwpxFwRietemPz69WhA3Q6XcSoMygr0LTUe+c4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dzdSp0Q/0bEw3FZcskjmxWxEv4BUzUpUo927d5k7SvXXcPEyMGltnVzcvfNiEjqFr yuVUkoOvuZKkm4rk50GKgf7+ncr9dn/XFDy7huf7kNMC77demCKwDc23kn+N6moIDe ix6y3tsXqiDFDuPxyKg+eHyHEbuyp29CtpygcpNqu9soLQYt77DY/ZcZdo+mC5CJ+H bnl4/ckal2VijVyUs/wyJplYBlARw5w960SEPbmzBtsWxqOh5wjyS9UmFmdLRPmZWu ZfnnJmqp5tKpz89g05zaXlhT7KbeLH1CDbJ9RwtYrx4tTI2bYVWpOUhlrUfuxZTYpq 3ysRYa5uA/XDQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hd-002Y3f-Nx; Mon, 24 Jan 2022 20:12:37 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 07/10] arm64: dts: apple: Add t8303 PMU nodes Date: Mon, 24 Jan 2022 20:12:28 +0000 Message-Id: <20220124201231.298961-8-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Advertise the two PMU nodes for the t8103 SoC. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index ca856f9955d8..aa0768ecb800 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -97,6 +97,18 @@ timer { ; }; =20 + pmu-e { + compatible =3D "apple,icestorm-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,firestorm-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + clkref: clock-ref { compatible =3D "fixed-clock"; #clock-cells =3D <0>; --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE0EDC433F5 for ; Mon, 24 Jan 2022 21:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1575449AbiAXVvn (ORCPT ); Mon, 24 Jan 2022 16:51:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1449984AbiAXVRk (ORCPT ); Mon, 24 Jan 2022 16:17:40 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DBA7C067A6B; Mon, 24 Jan 2022 12:12:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C12EE6137A; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 940F3C340E5; Mon, 24 Jan 2022 20:12:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055160; bh=x91SqHqSDXzrR/xOFZmvpf3H6bGQ2CI6FHdX2RXvYF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=puyGksuJbeN301FmGQnLnEq8p9BZJlqTj17HnD196fcXsI7B8Mj3cxNeoJAyitHAs 7hAEdj63zXne5Y5GNPSw7ptdtdDGYHb1UdneFYAsdgLjMn/tMbjdfgb/ppKlycGPRp bSJMwdZq2D2OiuWs8w0SZketZZQAuzRdgi0A26+4gw8vIG5Rj5nD624vOneRN4wl2y qkG3Sys27s6XcQTxKbrlo7XTYZywHKNT8lxAG2bGjqwK6V55LFOXaNIeB3K52kQwLP qWg/w8sdVfxN8NGy+d8fBzDbjHQARzNJFTb3bDea28NfZcpfXLAM4RUEnAHC5KHYDK aEg1CY064tdtw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5he-002Y3f-2Q; Mon, 24 Jan 2022 20:12:38 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 08/10] irqchip/apple-aic: Move PMU-specific registers to their own include file Date: Mon, 24 Jan 2022 20:12:29 +0000 Message-Id: <20220124201231.298961-9-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/apple_m1_pmu.h | 19 +++++++++++++++++++ drivers/irqchip/irq-apple-aic.c | 11 +---------- 2 files changed, 20 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/include/asm/apple_m1_pmu.h diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h new file mode 100644 index 000000000000..b848af7faadc --- /dev/null +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __ASM_APPLE_M1_PMU_h +#define __ASM_APPLE_M1_PMU_h + +#include +#include + +/* Core PMC control register */ +#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) +#define PMCR0_IMODE GENMASK(10, 8) +#define PMCR0_IMODE_OFF 0 +#define PMCR0_IMODE_PMI 1 +#define PMCR0_IMODE_AIC 2 +#define PMCR0_IMODE_HALT 3 +#define PMCR0_IMODE_FIQ 4 +#define PMCR0_IACT BIT(11) + +#endif /* __ASM_APPLE_M1_PMU_h */ diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 9daa28c55fa1..69e1e6abcc38 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -109,16 +110,6 @@ * Note: sysreg-based IPIs are not supported yet. */ =20 -/* Core PMC control register */ -#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) -#define PMCR0_IMODE GENMASK(10, 8) -#define PMCR0_IMODE_OFF 0 -#define PMCR0_IMODE_PMI 1 -#define PMCR0_IMODE_AIC 2 -#define PMCR0_IMODE_HALT 3 -#define PMCR0_IMODE_FIQ 4 -#define PMCR0_IACT BIT(11) - /* IPI request registers */ #define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0) #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1) --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39DD4C2BA4C for ; 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d=kernel.org; s=k20201202; t=1643055160; bh=byMO3nYSC2TvSH32oHHrAxbZ7HoV85bYK3g6rU+Vckk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ebm4MB3E88Yqn7BvQzfMhMEsishhVM9UX7r3FPZu846+SL16XmVkZHDFFbeOw/RS9 TWWh5aN2GJa/EBJPnVKVQyVHCEiEN+t9tqlBHiUXiznH51+NefoYO/vDxfMVtDU+Hy /aYkJL44EeYBfkj1HjzdzSrRLARG5NjUu/O/NJ3/3uiyNTzZgsl1PlhTh4/4pxuTe/ K76MRh7c5RfUO/EgezAlJNQoo89bSIFXn80CR50EIkCRvbTR45TFXXKCuedF3mUVuG dgGYhI5GT/gtzT9eqsWjkPHE+c/uEmFWYa6I5pfHj+4ShNIcjkpkXTNiBMC3CcgOC1 K2lDT3qIKpfoA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hf-002Y3f-07; Mon, 24 Jan 2022 20:12:39 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 09/10] drivers/perf: arm_pmu: Handle 47 bit counters Date: Mon, 24 Jan 2022 20:12:30 +0000 Message-Id: <20220124201231.298961-10-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current ARM PMU framework can only deal with 32 or 64bit counters. Teach it about a 47bit flavour. Yes, this is odd. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- drivers/perf/arm_pmu.c | 2 ++ include/linux/perf/arm_pmu.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 295cc7952d0e..0a9ed1a061ac 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_= event *event) { if (event->hw.flags & ARMPMU_EVT_64BIT) return GENMASK_ULL(63, 0); + else if (event->hw.flags & ARMPMU_EVT_47BIT) + return GENMASK_ULL(46, 0); else return GENMASK_ULL(31, 0); } diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 2512e2f9cd4e..0407a38b470a 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -26,6 +26,8 @@ */ /* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 1 +/* Event uses a 47bit counter */ +#define ARMPMU_EVT_47BIT 2 =20 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x --=20 2.30.2 From nobody Tue Jun 30 05:22:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B935DC43217 for ; Mon, 24 Jan 2022 20:42:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1389175AbiAXUkg (ORCPT ); Mon, 24 Jan 2022 15:40:36 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:58660 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381304AbiAXUUF (ORCPT ); Mon, 24 Jan 2022 15:20:05 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 790D3B8122D; Mon, 24 Jan 2022 20:20:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4310C340E8; Mon, 24 Jan 2022 20:20:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643055602; bh=IOrzP7AZQZvXLCOiOi008mSBOlUIwceqknphO08hNss=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h9p9wTpKRQZyIKOxNxeLo9FVtT8eHJhsC+GC6TKHlZoVtX++cSqbkiCWhoLQ9ZbBd /fdhYV3T1bKowvJW9KZSRgWH+MXzL0wmGG2kxxku/Apr26HTpSbD0+XhCHa6fA7GBn LtFd5dQ/a8seiA6T993ih5649GJyyXowPRFaSS57e6CeWafWrfemAmo6y/J+9nUUbH DhJGgAUXZArE9ZCbvn8eyZt2s+cVuffxo452yhXegggrJ73Tt13Sits/Y6DWfE/p4A JMRBWrDevj9f2A4mG8XUhbVlKmazgUZduKdLiNdReLnfiKagz5J6OhDQHbwST6Vu9z cwaoQxKmkxaZQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nC5hf-002Y3f-Ay; Mon, 24 Jan 2022 20:12:39 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v4 10/10] drivers/perf: Add Apple icestorm/firestorm CPU PMU driver Date: Mon, 24 Jan 2022 20:12:31 +0000 Message-Id: <20220124201231.298961-11-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220124201231.298961-1-maz@kernel.org> References: <20220124201231.298961-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a new, weird and wonderful driver for the equally weird Apple PMU HW. Although the PMU itself is functional, we don't know much about the events yet, so this can be considered as yet another random number generator... Nonetheless, it can reliably count at least cycles and instructions in the usually wonky big-little way. For anything else, it of course supports raw event numbers. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/apple_m1_pmu.h | 45 ++ drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/apple_m1_cpu_pmu.c | 584 ++++++++++++++++++++++++++ 4 files changed, 637 insertions(+) create mode 100644 drivers/perf/apple_m1_cpu_pmu.c diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index b848af7faadc..99483b19b99f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -6,8 +6,21 @@ #include #include =20 +/* Counters */ +#define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0) +#define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0) +#define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0) +#define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0) +#define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0) +#define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0) +#define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0) +#define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0) +#define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0) +#define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0) + /* Core PMC control register */ #define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) +#define PMCR0_CNT_ENABLE_0_7 GENMASK(7, 0) #define PMCR0_IMODE GENMASK(10, 8) #define PMCR0_IMODE_OFF 0 #define PMCR0_IMODE_PMI 1 @@ -15,5 +28,37 @@ #define PMCR0_IMODE_HALT 3 #define PMCR0_IMODE_FIQ 4 #define PMCR0_IACT BIT(11) +#define PMCR0_PMI_ENABLE_0_7 GENMASK(19, 12) +#define PMCR0_STOP_CNT_ON_PMI BIT(20) +#define PMCR0_CNT_GLOB_L2C_EVT BIT(21) +#define PMCR0_DEFER_PMI_TO_ERET BIT(22) +#define PMCR0_ALLOW_CNT_EN_EL0 BIT(30) +#define PMCR0_CNT_ENABLE_8_9 GENMASK(33, 32) +#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44) + +#define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) +#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) +#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) +#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) + +#define SYS_IMP_APL_PMCR2_EL1 sys_reg(3, 1, 15, 2, 0) +#define SYS_IMP_APL_PMCR3_EL1 sys_reg(3, 1, 15, 3, 0) +#define SYS_IMP_APL_PMCR4_EL1 sys_reg(3, 1, 15, 4, 0) + +#define SYS_IMP_APL_PMESR0_EL1 sys_reg(3, 1, 15, 5, 0) +#define PMESR0_EVT_CNT_2 GENMASK(7, 0) +#define PMESR0_EVT_CNT_3 GENMASK(15, 8) +#define PMESR0_EVT_CNT_4 GENMASK(23, 16) +#define PMESR0_EVT_CNT_5 GENMASK(31, 24) + +#define SYS_IMP_APL_PMESR1_EL1 sys_reg(3, 1, 15, 6, 0) +#define PMESR1_EVT_CNT_6 GENMASK(7, 0) +#define PMESR1_EVT_CNT_7 GENMASK(15, 8) +#define PMESR1_EVT_CNT_8 GENMASK(23, 16) +#define PMESR1_EVT_CNT_9 GENMASK(31, 24) + +#define SYS_IMP_APL_PMSR_EL1 sys_reg(3, 1, 15, 13, 0) +#define PMSR_OVERFLOW GENMASK(9, 0) =20 #endif /* __ASM_APPLE_M1_PMU_h */ diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index e1a0c44bc686..d4fa0dabb05f 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -146,6 +146,13 @@ config MARVELL_CN10K_TAD_PMU Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) performance monitors on CN10K family silicons. =20 +config APPLE_M1_CPU_PMU + bool "Apple M1 CPU PMU support" + depends on ARM_PMU && ARCH_APPLE + help + Provides support for the non-architectural CPU PMUs present on + the Apple M1 SoCs and derivatives. + source "drivers/perf/hisilicon/Kconfig" =20 endmenu diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 2db5418d5b0a..21ad0832e3d4 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_XGENE_PMU) +=3D xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) +=3D arm_spe_pmu.o obj-$(CONFIG_ARM_DMC620_PMU) +=3D arm_dmc620_pmu.o obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_tad_pmu.o +obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c new file mode 100644 index 000000000000..979a7c2b4f56 --- /dev/null +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CPU PMU driver for the Apple M1 and derivatives + * + * Copyright (C) 2021 Google LLC + * + * Author: Marc Zyngier + * + * Most of the information used in this driver was provided by the + * Asahi Linux project. The rest was experimentally discovered. + */ + +#include +#include +#include + +#include +#include +#include + +#define M1_PMU_NR_COUNTERS 10 + +#define M1_PMU_CFG_EVENT GENMASK(7, 0) + +#define ANY_BUT_0_1 GENMASK(9, 2) +#define ONLY_2_TO_7 GENMASK(7, 2) +#define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) + +/* + * Description of the events we actually know about, as well as those with + * a specific counter affinity. Yes, this is a grand total of two known + * counters, and the rest is anybody's guess. + * + * Not all counters can count all events. Counters #0 and #1 are wired to + * count cycles and instructions respectively, and some events have + * bizarre mappings (every other counter, or even *one* counter). These + * restrictions equally apply to both P and E cores. + * + * It is worth noting that the PMUs attached to P and E cores are likely + * to be different because the underlying uarches are different. At the + * moment, we don't really need to distinguish between the two because we + * know next to nothing about the events themselves, and we already have + * per cpu-type PMU abstractions. + * + * If we eventually find out that the events are different across + * implementations, we'll have to introduce per cpu-type tables. + */ +enum m1_pmu_events { + M1_PMU_PERFCTR_UNKNOWN_01 =3D 0x01, + M1_PMU_PERFCTR_CPU_CYCLES =3D 0x02, + M1_PMU_PERFCTR_INSTRUCTIONS =3D 0x8c, + M1_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + M1_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + M1_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + M1_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + M1_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + M1_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + M1_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + M1_PMU_PERFCTR_UNKNOWN_96 =3D 0x96, + M1_PMU_PERFCTR_UNKNOWN_97 =3D 0x97, + M1_PMU_PERFCTR_UNKNOWN_98 =3D 0x98, + M1_PMU_PERFCTR_UNKNOWN_99 =3D 0x99, + M1_PMU_PERFCTR_UNKNOWN_9a =3D 0x9a, + M1_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + M1_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, + M1_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + M1_PMU_PERFCTR_UNKNOWN_bf =3D 0xbf, + M1_PMU_PERFCTR_UNKNOWN_c0 =3D 0xc0, + M1_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + M1_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + M1_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + M1_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + M1_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + M1_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + M1_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + M1_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + M1_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + M1_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + M1_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + M1_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + M1_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + M1_PMU_CFG_COUNT_USER =3D BIT(8), + M1_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +/* + * Per-event affinity table. Most events can be installed on counter + * 2-9, but there are a number of exceptions. Note that this table + * has been created experimentally, and I wouldn't be surprised if more + * counters had strange affinities. + */ +static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] =3D { + [0 ... M1_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [M1_PMU_PERFCTR_UNKNOWN_01] =3D BIT(7), + [M1_PMU_PERFCTR_CPU_CYCLES] =3D ANY_BUT_0_1 | BIT(0), + [M1_PMU_PERFCTR_INSTRUCTIONS] =3D BIT(7) | BIT(1), + [M1_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_96] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_97] =3D BIT(7), + [M1_PMU_PERFCTR_UNKNOWN_98] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_99] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9a] =3D BIT(7), + [M1_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [M1_PMU_PERFCTR_UNKNOWN_bf] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c0] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + +static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CPU_CYCLES, + [PERF_COUNT_HW_INSTRUCTIONS] =3D M1_PMU_PERFCTR_INSTRUCTIONS, + /* No idea about the rest yet */ +}; + +/* sysfs definitions */ +static ssize_t m1_pmu_events_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *page) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr =3D container_of(attr, struct perf_pmu_events_attr, attr); + + return sprintf(page, "event=3D0x%04llx\n", pmu_attr->id); +} + +#define M1_PMU_EVENT_ATTR(name, config) \ + PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) + +static struct attribute *m1_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CPU_CYCLES), + M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INSTRUCTIONS), + NULL, +}; + +static const struct attribute_group m1_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D m1_pmu_event_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-7"); + +static struct attribute *m1_pmu_format_attrs[] =3D { + &format_attr_event.attr, + NULL, +}; + +static const struct attribute_group m1_pmu_format_attr_group =3D { + .name =3D "format", + .attrs =3D m1_pmu_format_attrs, +}; + +/* Low level accessors. No synchronisation. */ +#define PMU_READ_COUNTER(_idx) \ + case _idx: return read_sysreg_s(SYS_IMP_APL_PMC## _idx ##_EL1) + +#define PMU_WRITE_COUNTER(_val, _idx) \ + case _idx: \ + write_sysreg_s(_val, SYS_IMP_APL_PMC## _idx ##_EL1); \ + return + +static u64 m1_pmu_read_hw_counter(unsigned int index) +{ + switch (index) { + PMU_READ_COUNTER(0); + PMU_READ_COUNTER(1); + PMU_READ_COUNTER(2); + PMU_READ_COUNTER(3); + PMU_READ_COUNTER(4); + PMU_READ_COUNTER(5); + PMU_READ_COUNTER(6); + PMU_READ_COUNTER(7); + PMU_READ_COUNTER(8); + PMU_READ_COUNTER(9); + } + + BUG(); +} + +static void m1_pmu_write_hw_counter(u64 val, unsigned int index) +{ + switch (index) { + PMU_WRITE_COUNTER(val, 0); + PMU_WRITE_COUNTER(val, 1); + PMU_WRITE_COUNTER(val, 2); + PMU_WRITE_COUNTER(val, 3); + PMU_WRITE_COUNTER(val, 4); + PMU_WRITE_COUNTER(val, 5); + PMU_WRITE_COUNTER(val, 6); + PMU_WRITE_COUNTER(val, 7); + PMU_WRITE_COUNTER(val, 8); + PMU_WRITE_COUNTER(val, 9); + } + + BUG(); +} + +#define get_bit_offset(index, mask) (__ffs(mask) + (index)) + +static void __m1_pmu_enable_counter(unsigned int index, bool en) +{ + u64 val, bit; + + switch (index) { + case 0 ... 7: + bit =3D BIT(get_bit_offset(index, PMCR0_CNT_ENABLE_0_7)); + break; + case 8 ... 9: + bit =3D BIT(get_bit_offset(index - 8, PMCR0_CNT_ENABLE_8_9)); + break; + default: + BUG(); + } + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + + if (en) + val |=3D bit; + else + val &=3D ~bit; + + write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); +} + +static void m1_pmu_enable_counter(unsigned int index) +{ + __m1_pmu_enable_counter(index, true); +} + +static void m1_pmu_disable_counter(unsigned int index) +{ + __m1_pmu_enable_counter(index, false); +} + +static void __m1_pmu_enable_counter_interrupt(unsigned int index, bool en) +{ + u64 val, bit; + + switch (index) { + case 0 ... 7: + bit =3D BIT(get_bit_offset(index, PMCR0_PMI_ENABLE_0_7)); + break; + case 8 ... 9: + bit =3D BIT(get_bit_offset(index - 8, PMCR0_PMI_ENABLE_8_9)); + break; + default: + BUG(); + } + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + + if (en) + val |=3D bit; + else + val &=3D ~bit; + + write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); +} + +static void m1_pmu_enable_counter_interrupt(unsigned int index) +{ + __m1_pmu_enable_counter_interrupt(index, true); +} + +static void m1_pmu_disable_counter_interrupt(unsigned int index) +{ + __m1_pmu_enable_counter_interrupt(index, false); +} + +static void m1_pmu_configure_counter(unsigned int index, u8 event, + bool user, bool kernel) +{ + u64 val, user_bit, kernel_bit; + int shift; + + switch (index) { + case 0 ... 7: + user_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); + kernel_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7)); + break; + case 8 ... 9: + user_bit =3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9)); + kernel_bit =3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9)); + break; + default: + BUG(); + } + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR1_EL1); + + if (user) + val |=3D user_bit; + else + val &=3D ~user_bit; + + if (kernel) + val |=3D kernel_bit; + else + val &=3D ~kernel_bit; + + write_sysreg_s(val, SYS_IMP_APL_PMCR1_EL1); + + /* + * Counters 0 and 1 have fixed events. For anything else, + * place the event at the expected location in the relevant + * register (PMESR0 holds the event configuration for counters + * 2-5, resp. PMESR1 for counters 6-9). + */ + switch (index) { + case 0 ... 1: + break; + case 2 ... 5: + shift =3D (index - 2) * 8; + val =3D read_sysreg_s(SYS_IMP_APL_PMESR0_EL1); + val &=3D ~((u64)0xff << shift); + val |=3D (u64)event << shift; + write_sysreg_s(val, SYS_IMP_APL_PMESR0_EL1); + break; + case 6 ... 9: + shift =3D (index - 6) * 8; + val =3D read_sysreg_s(SYS_IMP_APL_PMESR1_EL1); + val &=3D ~((u64)0xff << shift); + val |=3D (u64)event << shift; + write_sysreg_s(val, SYS_IMP_APL_PMESR1_EL1); + break; + } +} + +/* arm_pmu backend */ +static void m1_pmu_enable_event(struct perf_event *event) +{ + bool user, kernel; + u8 evt; + + evt =3D event->hw.config_base & M1_PMU_CFG_EVENT; + user =3D event->hw.config_base & M1_PMU_CFG_COUNT_USER; + kernel =3D event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL; + + m1_pmu_disable_counter_interrupt(event->hw.idx); + m1_pmu_disable_counter(event->hw.idx); + isb(); + + m1_pmu_configure_counter(event->hw.idx, evt, user, kernel); + m1_pmu_enable_counter(event->hw.idx); + m1_pmu_enable_counter_interrupt(event->hw.idx); + isb(); +} + +static void m1_pmu_disable_event(struct perf_event *event) +{ + m1_pmu_disable_counter_interrupt(event->hw.idx); + m1_pmu_disable_counter(event->hw.idx); + isb(); +} + +static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu) +{ + struct pmu_hw_events *cpuc =3D this_cpu_ptr(cpu_pmu->hw_events); + struct pt_regs *regs; + u64 overflow, state; + int idx; + + overflow =3D read_sysreg_s(SYS_IMP_APL_PMSR_EL1); + if (!overflow) { + /* Spurious interrupt? */ + state =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + state &=3D ~PMCR0_IACT; + write_sysreg_s(state, SYS_IMP_APL_PMCR0_EL1); + isb(); + return IRQ_NONE; + } + + cpu_pmu->stop(cpu_pmu); + + regs =3D get_irq_regs(); + + for (idx =3D 0; idx < cpu_pmu->num_events; idx++) { + struct perf_event *event =3D cpuc->events[idx]; + struct perf_sample_data data; + + if (!event) + continue; + + armpmu_event_update(event); + perf_sample_data_init(&data, 0, event->hw.last_period); + if (!armpmu_event_set_period(event)) + continue; + + if (perf_event_overflow(event, &data, regs)) + m1_pmu_disable_event(event); + } + + cpu_pmu->start(cpu_pmu); + + return IRQ_HANDLED; +} + +static u64 m1_pmu_read_counter(struct perf_event *event) +{ + return m1_pmu_read_hw_counter(event->hw.idx); +} + +static void m1_pmu_write_counter(struct perf_event *event, u64 value) +{ + m1_pmu_write_hw_counter(value, event->hw.idx); + isb(); +} + +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + unsigned long evtype =3D event->hw.config_base & M1_PMU_CFG_EVENT; + unsigned long affinity =3D m1_pmu_event_affinity[evtype]; + int idx; + + /* + * Place the event on the first free counter that can count + * this event. + * + * We could do a better job if we had a view of all the events + * counting on the PMU at any given time, and by placing the + * most constraining events first. + */ + for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + if (!test_and_set_bit(idx, cpuc->used_mask)) + return idx; + } + + return -EAGAIN; +} + +static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + clear_bit(event->hw.idx, cpuc->used_mask); +} + +static void __m1_pmu_set_mode(u8 mode) +{ + u64 val; + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + val &=3D ~(PMCR0_IMODE | PMCR0_IACT); + val |=3D FIELD_PREP(PMCR0_IMODE, mode); + write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); + isb(); +} + +static void m1_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_FIQ); +} + +static void m1_pmu_stop(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_OFF); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + /* + * Although the counters are 48bit wide, bit 47 is what + * triggers the overflow interrupt. Advertise the counters + * being 47bit wide to mimick the behaviour of the ARM PMU. + */ + event->hw.flags |=3D ARMPMU_EVT_47BIT; + return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static void m1_pmu_reset(void *info) +{ + int i; + + __m1_pmu_set_mode(PMCR0_IMODE_OFF); + + for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + m1_pmu_disable_counter(i); + m1_pmu_disable_counter_interrupt(i); + m1_pmu_write_hw_counter(0, i); + } + + isb(); +} + +static int m1_pmu_set_event_filter(struct hw_perf_event *event, + struct perf_event_attr *attr) +{ + unsigned long config_base =3D 0; + + if (!attr->exclude_guest) + return -EINVAL; + if (!attr->exclude_kernel) + config_base |=3D M1_PMU_CFG_COUNT_KERNEL; + if (!attr->exclude_user) + config_base |=3D M1_PMU_CFG_COUNT_USER; + + event->config_base =3D config_base; + + return 0; +} + +static int m1_pmu_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->handle_irq =3D m1_pmu_handle_irq; + cpu_pmu->enable =3D m1_pmu_enable_event; + cpu_pmu->disable =3D m1_pmu_disable_event; + cpu_pmu->read_counter =3D m1_pmu_read_counter; + cpu_pmu->write_counter =3D m1_pmu_write_counter; + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->stop =3D m1_pmu_stop; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; + + cpu_pmu->num_events =3D M1_PMU_NR_COUNTERS; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; + return 0; +} + +/* Device driver gunk */ +static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_icestorm_pmu"; + return m1_pmu_init(cpu_pmu); +} + +static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_firestorm_pmu"; + return m1_pmu_init(cpu_pmu); +} + +static const struct of_device_id m1_pmu_of_device_ids[] =3D { + { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, + { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { }, +}; +MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); + +static int m1_pmu_device_probe(struct platform_device *pdev) +{ + return arm_pmu_device_probe(pdev, m1_pmu_of_device_ids, NULL); +} + +static struct platform_driver m1_pmu_driver =3D { + .driver =3D { + .name =3D "apple-m1-cpu-pmu", + .of_match_table =3D m1_pmu_of_device_ids, + .suppress_bind_attrs =3D true, + }, + .probe =3D m1_pmu_device_probe, +}; + +module_platform_driver(m1_pmu_driver); +MODULE_LICENSE("GPL v2"); --=20 2.30.2