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[71.198.251.229]) by smtp.gmail.com with ESMTPSA id b12sm9348994pfv.148.2022.01.21.23.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jan 2022 23:26:47 -0800 (PST) From: Kyle Huey X-Google-Original-From: Kyle Huey To: linux-kernel@vger.kernel.org, Kan Liang Cc: linux-perf-users@vger.kernel.org, "H. Peter Anvin" , x86@kernel.org, Dave Hansen , Borislav Petkov , Thomas Gleixner , Namhyung Kim , Jiri Olsa , Alexander Shishkin , Mark Rutland , Arnaldo Carvalho de Melo , Ingo Molnar , Peter Zijlstra , Robert O'Callahan , Keno Fischer Subject: [PATCH] x86/perf: Default freeze_on_smi on for Comet Lake and later. Date: Fri, 21 Jan 2022 23:26:44 -0800 Message-Id: <20220122072644.92292-1-khuey@kylehuey.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Beginning in Comet Lake, Intel extended the concept of privilege rings to SMM.[0] A side effect of this is that events caused by execution of code in SMM are now visible to performance counters with IA32_PERFEVTSELx.USR set. rr[1] depends on exact counts of performance events for the user space tracee, so this change in behavior is fatal for us. It is, however, easily corrected by setting IA32_DEBUGCTL.FREEZE_WHILE_SMM to 1 (visible in sysfs as /sys/devices/cpu/freeze_on_smi). While we can and will tell our users to set freeze_on_smi manually when appropriate, because observing events in SMM is rarely useful to anyone, we propose to change the default value of this switch. In this patch I have assumed that all non-Atom Intel microarchitectures starting with Comet Lake behave like this but it would be good for someone at Intel to verify that. [0] See the Intel white paper "Trustworthy SMM on the Intel vPro Platform" at https://bugzilla.kernel.org/attachment.cgi?id=3D300300, particularly the end of page 5. [1] https://rr-project.org/ Signed-off-by: Kyle Huey --- arch/x86/events/intel/core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index fd9f908debe5..9604e19c8761 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6094,6 +6094,11 @@ __init int intel_pmu_init(void) x86_pmu.commit_scheduling =3D intel_tfa_commit_scheduling; } =20 + if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_COMETLAKE_L || + boot_cpu_data.x86_model =3D=3D INTEL_FAM6_COMETLAKE) { + x86_pmu.attr_freeze_on_smi =3D 1; + } + pr_cont("Skylake events, "); name =3D "skylake"; break; @@ -6135,6 +6140,7 @@ __init int intel_pmu_init(void) x86_pmu.num_topdown_events =3D 4; x86_pmu.update_topdown_event =3D icl_update_topdown_event; x86_pmu.set_topdown_event_period =3D icl_set_topdown_event_period; + x86_pmu.attr_freeze_on_smi =3D 1; pr_cont("Icelake events, "); name =3D "icelake"; break; @@ -6172,6 +6178,7 @@ __init int intel_pmu_init(void) x86_pmu.num_topdown_events =3D 8; x86_pmu.update_topdown_event =3D icl_update_topdown_event; x86_pmu.set_topdown_event_period =3D icl_set_topdown_event_period; + x86_pmu.attr_freeze_on_smi =3D 1; pr_cont("Sapphire Rapids events, "); name =3D "sapphire_rapids"; break; @@ -6217,6 +6224,7 @@ __init int intel_pmu_init(void) * x86_pmu.rtm_abort_event. */ x86_pmu.rtm_abort_event =3D X86_CONFIG(.event=3D0xc9, .umask=3D0x04); + x86_pmu.attr_freeze_on_smi =3D 1; =20 td_attr =3D adl_hybrid_events_attrs; mem_attr =3D adl_hybrid_mem_attrs; --=20 2.34.1