From nobody Sun Sep 22 11:32:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2992CC4321E for ; Thu, 20 Jan 2022 07:02:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358880AbiATHCn (ORCPT ); Thu, 20 Jan 2022 02:02:43 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:60032 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1358819AbiATHCi (ORCPT ); Thu, 20 Jan 2022 02:02:38 -0500 X-UUID: 9951080691e842b2b880ea06bb800532-20220120 X-UUID: 9951080691e842b2b880ea06bb800532-20220120 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1604621939; Thu, 20 Jan 2022 15:02:34 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 20 Jan 2022 15:02:33 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Jan 2022 15:02:32 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v1 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC Date: Thu, 20 Jan 2022 15:02:20 +0800 Message-ID: <20220120070226.1492-4-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120070226.1492-1-biao.huang@mediatek.com> References: <20220120070226.1492-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet driver support for MT8365 SoC. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: Fabien Parent --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++--- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 7c2af775d601..403439782db9 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -151,6 +151,7 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_STAR_REG_MAC_CLK_CONF 0x00ac #define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0) #define MTK_STAR_BIT_CLK_DIV_10 0x0a +#define MTK_STAR_BIT_CLK_DIV_50 0x32 =20 /* Counter registers. */ #define MTK_STAR_REG_C_RXOKPKT 0x0100 @@ -183,9 +184,11 @@ static const char *const mtk_star_clk_names[] =3D { "c= ore", "reg", "trans" }; #define MTK_STAR_REG_C_RX_TWIST 0x0218 =20 /* Ethernet CFG Control */ -#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4 -#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0) -#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0) +#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4 +#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 +#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 +#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 =20 /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, o= nly @@ -234,6 +237,7 @@ struct mtk_star_ring { }; =20 struct mtk_star_compat { + int (*set_interface_mode)(struct net_device *ndev); unsigned char bit_clk_div; }; =20 @@ -909,13 +913,6 @@ static void mtk_star_init_config(struct mtk_star_priv = *priv) priv->compat_data->bit_clk_div); } =20 -static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) -{ - regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON, - MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII, - MTK_PERICFG_BIT_NIC_CFG_CON_RMII); -} - static int mtk_star_enable(struct net_device *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); @@ -1531,7 +1528,13 @@ static int mtk_star_probe(struct platform_device *pd= ev) return -ENODEV; } =20 - mtk_star_set_mode_rmii(priv); + if (priv->compat_data->set_interface_mode) { + ret =3D priv->compat_data->set_interface_mode(ndev); + if (ret) { + dev_err(dev, "Failed to set phy interface, err =3D %d\n", ret); + return -EINVAL; + } + } =20 ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { @@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *p= dev) return devm_register_netdev(dev, ndev); } =20 +static int mt8516_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv =3D netdev_priv(ndev); + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int intf_val =3D 0; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG0_CON, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); + return 0; +} + +static int mt8365_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv =3D netdev_priv(ndev); + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int intf_val =3D 0; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON_V2, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); + return 0; +} + static struct mtk_star_compat mtk_star_mt8516_compat =3D { + .set_interface_mode =3D mt8516_set_interface_mode, .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_10, }; =20 +static struct mtk_star_compat mtk_star_mt8365_compat =3D { + .set_interface_mode =3D mt8365_set_interface_mode, + .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_50, +}; + static const struct of_device_id mtk_star_of_match[] =3D { { .compatible =3D "mediatek,mt8516-eth", .data =3D &mtk_star_mt8516_compat }, @@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = =3D { .data =3D &mtk_star_mt8516_compat }, { .compatible =3D "mediatek,mt8175-eth", .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8365-eth", + .data =3D &mtk_star_mt8365_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); --=20 2.25.1