From nobody Sun Sep 22 09:28:44 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D10BC433EF for ; Wed, 19 Jan 2022 12:37:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354765AbiASMhN (ORCPT ); Wed, 19 Jan 2022 07:37:13 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52260 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1354780AbiASMgt (ORCPT ); Wed, 19 Jan 2022 07:36:49 -0500 X-UUID: c16ece47013748989a5bd767ee54ecf8-20220119 X-UUID: c16ece47013748989a5bd767ee54ecf8-20220119 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1926431416; Wed, 19 Jan 2022 20:36:45 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 19 Jan 2022 20:36:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 19 Jan 2022 20:36:44 +0800 From: Sam Shih To: Rob Herring , Matthias Brugger , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 1/1] arm64: dts: mediatek: add clock support for mt7986a Date: Wed, 19 Jan 2022 20:36:24 +0800 Message-ID: <20220119123624.10043-2-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220119123624.10043-1-sam.shih@mediatek.com> References: <20220119123624.10043-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock controller nodes, include 40M clock source, topckgen, infracfg, apmixedsys and ethernet subsystem. Signed-off-by: Sam Shih --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 68 +++++++++++++++++++++-- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7986a.dtsi index b8da76b6ba47..694acf8f5b70 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -6,16 +6,18 @@ =20 #include #include +#include =20 / { interrupt-parent =3D <&gic>; #address-cells =3D <2>; #size-cells =3D <2>; =20 - system_clk: dummy40m { + clk40m: oscillator@0 { compatible =3D "fixed-clock"; clock-frequency =3D <40000000>; #clock-cells =3D <0>; + clock-output-names =3D "clkxtal"; }; =20 cpus { @@ -98,6 +100,18 @@ gic: interrupt-controller@c000000 { interrupts =3D ; }; =20 + infracfg: infracfg@10001000 { + compatible =3D "mediatek,mt7986-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + topckgen: topckgen@1001b000 { + compatible =3D "mediatek,mt7986-topckgen", "syscon"; + reg =3D <0 0x1001B000 0 0x1000>; + #clock-cells =3D <1>; + }; + watchdog: watchdog@1001c000 { compatible =3D "mediatek,mt7986-wdt", "mediatek,mt6589-wdt"; @@ -107,6 +121,12 @@ watchdog: watchdog@1001c000 { status =3D "disabled"; }; =20 + apmixedsys: apmixedsys@1001e000 { + compatible =3D "mediatek,mt7986-apmixedsys"; + reg =3D <0 0x1001E000 0 0x1000>; + #clock-cells =3D <1>; + }; + pio: pinctrl@1001f000 { compatible =3D "mediatek,mt7986a-pinctrl"; reg =3D <0 0x1001f000 0 0x1000>, @@ -128,11 +148,25 @@ pio: pinctrl@1001f000 { #interrupt-cells =3D <2>; }; =20 + sgmiisys0: syscon@10060000 { + compatible =3D "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg =3D <0 0x10060000 0 0x1000>; + #clock-cells =3D <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible =3D "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg =3D <0 0x10070000 0 0x1000>; + #clock-cells =3D <1>; + }; + trng: trng@1020f000 { compatible =3D "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg =3D <0 0x1020f000 0 0x100>; - clocks =3D <&system_clk>; + clocks =3D <&infracfg CLK_INFRA_TRNG_CK>; clock-names =3D "rng"; status =3D "disabled"; }; @@ -142,7 +176,13 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg =3D <0 0x11002000 0 0x400>; interrupts =3D ; - clocks =3D <&system_clk>; + clocks =3D <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names =3D "baud", "bus"; + assigned-clocks =3D <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status =3D "disabled"; }; =20 @@ -151,7 +191,11 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg =3D <0 0x11003000 0 0x400>; interrupts =3D ; - clocks =3D <&system_clk>; + clocks =3D <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names =3D "baud", "bus"; + assigned-clocks =3D <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_F26M_SEL>; status =3D "disabled"; }; =20 @@ -160,10 +204,24 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg =3D <0 0x11004000 0 0x400>; interrupts =3D ; - clocks =3D <&system_clk>; + clocks =3D <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names =3D "baud", "bus"; + assigned-clocks =3D <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_F26M_SEL>; status =3D "disabled"; }; =20 + ethsys: syscon@15000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "mediatek,mt7986-ethsys", + "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + }; =20 }; --=20 2.29.2