From nobody Tue Jun 30 11:07:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46719C433EF for ; Wed, 19 Jan 2022 07:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351892AbiASHIQ (ORCPT ); Wed, 19 Jan 2022 02:08:16 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345240AbiASHIO (ORCPT ); Wed, 19 Jan 2022 02:08:14 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:12 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , , , Rob Herring Subject: [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs Date: Wed, 19 Jan 2022 15:08:06 +0800 Message-ID: <20220119070809.15563-2-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs Signed-off-by: Qianggui Song Acked-by: Rob Herring --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic= ,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controll= er/amlogic,meson-gpio-intc.txt index 23b18b92c558..bde63f8f090e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-= gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-= gpio-intc.txt @@ -18,6 +18,7 @@ Required properties: "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L) + "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S90= 5W2) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an --=20 2.34.1 From nobody Tue Jun 30 11:07:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56364C433F5 for ; Wed, 19 Jan 2022 07:08:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351891AbiASHIU (ORCPT ); Wed, 19 Jan 2022 02:08:20 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230223AbiASHIP (ORCPT ); Wed, 19 Jan 2022 02:08:15 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:12 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line Date: Wed, 19 Jan 2022 15:08:07 +0800 Message-ID: <20220119070809.15563-3-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current meson gpio irqchip driver only support 8 channels for gpio irq line, later chips may have more then 8 channels, so need to modify code to support more. Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index d90ff0b92480..eefe15e1b3a6 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -16,7 +16,6 @@ #include #include =20 -#define NUM_CHANNEL 8 #define MAX_INPUT_MUX 256 =20 #define REG_EDGE_POL 0x00 @@ -60,6 +59,7 @@ struct irq_ctl_ops { =20 struct meson_gpio_irq_params { unsigned int nr_hwirq; + unsigned int nr_channels; bool support_edge_both; unsigned int edge_both_offset; unsigned int edge_single_offset; @@ -81,6 +81,7 @@ struct meson_gpio_irq_params { .edge_single_offset =3D 0, \ .pol_low_offset =3D 16, \ .pin_sel_mask =3D 0xff, \ + .nr_channels =3D 8, \ =20 #define INIT_MESON_A1_COMMON_DATA(irqs) \ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ @@ -90,6 +91,7 @@ struct meson_gpio_irq_params { .edge_single_offset =3D 8, \ .pol_low_offset =3D 0, \ .pin_sel_mask =3D 0x7f, \ + .nr_channels =3D 8, \ =20 static const struct meson_gpio_irq_params meson8_params =3D { INIT_MESON8_COMMON_DATA(134) @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches= [] =3D { struct meson_gpio_irq_controller { const struct meson_gpio_irq_params *params; void __iomem *base; - u32 channel_irqs[NUM_CHANNEL]; - DECLARE_BITMAP(channel_map, NUM_CHANNEL); + u32 *channel_irqs; + unsigned long *channel_map; spinlock_t lock; }; =20 @@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_co= ntroller *ctl, spin_lock_irqsave(&ctl->lock, flags); =20 /* Find a free channel */ - idx =3D find_first_zero_bit(ctl->channel_map, NUM_CHANNEL); - if (idx >=3D NUM_CHANNEL) { + idx =3D find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels); + if (idx >=3D ctl->params->nr_channels) { spin_unlock_irqrestore(&ctl->lock, flags); pr_err("No channel available\n"); return -ENOSPC; @@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node= *node, struct meson_gpio_i =20 ctl->params =3D match->data; =20 + ctl->channel_irqs =3D kcalloc(ctl->params->nr_channels, sizeof(*ctl->chan= nel_irqs), + GFP_KERNEL); + if (!ctl->channel_irqs) + return -ENOMEM; + + ctl->channel_map =3D bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL); + if (!ctl->channel_map) { + kfree(ctl->channel_irqs); + return -ENOMEM; + } + ret =3D of_property_read_variable_u32_array(node, "amlogic,channel-interrupts", ctl->channel_irqs, - NUM_CHANNEL, - NUM_CHANNEL); + ctl->params->nr_channels, + ctl->params->nr_channels); if (ret < 0) { - pr_err("can't get %d channel interrupts\n", NUM_CHANNEL); + pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels); + kfree(ctl->channel_map); + kfree(ctl->channel_irqs); return ret; } =20 @@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *n= ode, struct device_node * } =20 pr_info("%d to %d gpio interrupt mux initialized\n", - ctl->params->nr_hwirq, NUM_CHANNEL); + ctl->params->nr_hwirq, ctl->params->nr_channels); =20 return 0; =20 --=20 2.34.1 From nobody Tue Jun 30 11:07:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE392C433EF for ; Wed, 19 Jan 2022 07:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351886AbiASHIW (ORCPT ); Wed, 19 Jan 2022 02:08:22 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351897AbiASHIS (ORCPT ); Wed, 19 Jan 2022 02:08:18 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:13 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback Date: Wed, 19 Jan 2022 15:08:08 +0800 Message-ID: <20220119070809.15563-4-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Due to some chips may use different registers and offset, provide a set trigger type call back. Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index eefe15e1b3a6..b511f9532adc 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -55,6 +55,8 @@ struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl, + unsigned int idx, u32 val); }; =20 struct meson_gpio_irq_params { @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio= _irq_controller *ctl, */ type &=3D IRQ_TYPE_SENSE_MASK; =20 + /* Some controllers may have different calculation method*/ + if (params->ops.gpio_irq_sel_type) { + params->ops.gpio_irq_sel_type(ctl, idx, type); + return 0; + } + /* * New controller support EDGE_BOTH trigger. This setting takes * precedence over the other edge/polarity settings --=20 2.34.1 From nobody Tue Jun 30 11:07:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12FF4C433F5 for ; Wed, 19 Jan 2022 07:08:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351946AbiASHI1 (ORCPT ); Wed, 19 Jan 2022 02:08:27 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351902AbiASHIU (ORCPT ); Wed, 19 Jan 2022 02:08:20 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:13 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: [PATCH v2 4/4] irqchip/meson-gpio: Add support for meson s4 SoCs Date: Wed, 19 Jan 2022 15:08:09 +0800 Message-ID: <20220119070809.15563-5-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The meson s4 SoCs support 12 gpio irq lines compared with previous serial chips and have something different, details are as below. IRQ Number: - 80:68 13 pins on bank Z - 67:48 20 pins on bank X - 47:36 12 pins on bank H - 35:24 12 pins on bank D - 23:22 2 pins on bank E - 21:14 8 pins on bank C - 13:0 13 pins on bank B Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index b511f9532adc..896201d2f01f 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -42,6 +42,9 @@ #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) =20 +/* Used for s4 chips */ +#define REG_EDGE_POL_S4 0x1c + struct meson_gpio_irq_controller; static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); @@ -50,6 +53,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_i= rq_controller *ctl, unsigned int channel, unsigned long hwirq); static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); +static void meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *c= tl, + unsigned int idx, u32 val); =20 struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, @@ -95,6 +100,20 @@ struct meson_gpio_irq_params { .pin_sel_mask =3D 0x7f, \ .nr_channels =3D 8, \ =20 +#define INIT_MESON_S4_COMMON_DATA(irqs) \ + .nr_hwirq =3D irqs, \ + .ops =3D { \ + .gpio_irq_init =3D meson_a1_gpio_irq_init, \ + .gpio_irq_sel_pin =3D meson_a1_gpio_irq_sel_pin, \ + .gpio_irq_sel_type =3D meson_s4_gpio_irq_sel_type,\ + }, \ + .support_edge_both =3D true, \ + .edge_both_offset =3D 0, \ + .edge_single_offset =3D 12, \ + .pol_low_offset =3D 0, \ + .pin_sel_mask =3D 0xff, \ + .nr_channels =3D 12, \ + static const struct meson_gpio_irq_params meson8_params =3D { INIT_MESON8_COMMON_DATA(134) }; @@ -125,6 +144,10 @@ static const struct meson_gpio_irq_params a1_params = =3D { INIT_MESON_A1_COMMON_DATA(62) }; =20 +static const struct meson_gpio_irq_params s4_params =3D { + INIT_MESON_S4_COMMON_DATA(82) +}; + static const struct of_device_id meson_irq_gpio_matches[] =3D { { .compatible =3D "amlogic,meson8-gpio-intc", .data =3D &meson8_params }, { .compatible =3D "amlogic,meson8b-gpio-intc", .data =3D &meson8b_params = }, @@ -134,6 +157,7 @@ static const struct of_device_id meson_irq_gpio_matches= [] =3D { { .compatible =3D "amlogic,meson-g12a-gpio-intc", .data =3D &axg_params }, { .compatible =3D "amlogic,meson-sm1-gpio-intc", .data =3D &sm1_params }, { .compatible =3D "amlogic,meson-a1-gpio-intc", .data =3D &a1_params }, + { .compatible =3D "amlogic,meson-s4-gpio-intc", .data =3D &s4_params }, { } }; =20 @@ -200,6 +224,46 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_i= rq_controller *ctl) meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); } =20 +/* + * gpio irq relative registers for s4 + * -PADCTRL_GPIO_IRQ_CTRL0 + * bit[31]: enable/disable all the irq lines + * bit[12-23]: single edge trigger + * bit[0-11]: polarity trigger + * + * -PADCTRL_GPIO_IRQ_CTRL[X] + * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2 + * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1 + * where X =3D 1-6 + * + * -PADCTRL_GPIO_IRQ_CTRL[7] + * bit[0-11]: both edge trigger + */ +static void +meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl, + unsigned int idx, unsigned int type) +{ + unsigned int val =3D 0; + + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0); + + if (type =3D=3D IRQ_TYPE_EDGE_BOTH) { + val |=3D BIT(ctl->params->edge_both_offset + idx); + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, + BIT(ctl->params->edge_both_offset + idx), val); + return; + } + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) + val |=3D BIT(ctl->params->pol_low_offset + idx); + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + val |=3D BIT(ctl->params->edge_single_offset + idx); + + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, + BIT(idx) | BIT(12 + idx), val); +}; + static int meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, unsigned long hwirq, --=20 2.34.1