From nobody Sun Sep 22 09:25:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A72C433F5 for ; Wed, 19 Jan 2022 02:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350995AbiASC0J (ORCPT ); Tue, 18 Jan 2022 21:26:09 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:37372 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1350978AbiASC0H (ORCPT ); Tue, 18 Jan 2022 21:26:07 -0500 X-UUID: 354047b20c08407d829c1dc1220a4eec-20220119 X-UUID: 354047b20c08407d829c1dc1220a4eec-20220119 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 641642071; Wed, 19 Jan 2022 10:26:04 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 19 Jan 2022 10:26:03 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 19 Jan 2022 10:26:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 19 Jan 2022 10:26:02 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , , , Rex-BC Chen Subject: [v10,2/3] drm/mediatek: implement the DSI HS packets aligned Date: Wed, 19 Jan 2022 10:25:42 +0800 Message-ID: <20220119022543.26093-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220119022543.26093-1-rex-bc.chen@mediatek.com> References: <20220119022543.26093-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some DSI RX devices (for example, anx7625) require last alignment of packets on all lanes after each row of data is sent. Otherwise, there will be some issues of shift or scroll for screen. Take horizontal_sync_active_byte for a example, we roundup the HSA packet data to lane number, and the subtraction of 2 is the packet data value added by the roundup operation, making the long packets are integer multiples of lane number. This value (2) varies with the lane number, and that is the reason we do this operation when the lane number is 4. In the previous operation of function "mtk_dsi_config_vdo_timing", the length of HSA and HFP data packets has been adjusted to an integration multiple of lane number. Since the number of RGB data packets cannot be guaranteed to be an integer multiple of lane number, we modify the data packet length of HBP so that the number of HBP + RGB is equal to the lane number. So after sending a line of data (HSA + HBP + RGB + HFP), the data lanes are aligned. Signed-off-by: Jitao Shi Signed-off-by: Rex-BC Chen Signed-off-by: Xinlei Lee Acked-by: Chun-Kuang Hu Reviewed-by: Andrzej Hajda Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 5d90d2eb0019..e91b3fff4342 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *= dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); } =20 + if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) && + (dsi->lanes =3D=3D 4)) { + horizontal_sync_active_byte =3D + roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte =3D + roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte =3D + roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -=3D + (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); --=20 2.18.0