From nobody Tue Jun 30 12:12:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0319C433EF for ; Tue, 18 Jan 2022 05:52:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239804AbiARFw5 (ORCPT ); Tue, 18 Jan 2022 00:52:57 -0500 Received: from mo-csw-fb1515.securemx.jp ([210.130.202.171]:57876 "EHLO mo-csw-fb.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239742AbiARFw4 (ORCPT ); Tue, 18 Jan 2022 00:52:56 -0500 X-Greylist: delayed 409 seconds by postgrey-1.27 at vger.kernel.org; Tue, 18 Jan 2022 00:52:56 EST Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1515) id 20I5k9f8032622; Tue, 18 Jan 2022 14:46:10 +0900 Received: by mo-csw.securemx.jp (mx-mo-csw1516) id 20I5jjnr006451; Tue, 18 Jan 2022 14:45:45 +0900 X-Iguazu-Qid: 34trEBPRjdLYs2IbyW X-Iguazu-QSIG: v=2; s=0; t=1642484744; q=34trEBPRjdLYs2IbyW; m=528tXebc3ETxb6iOW3urXJxBf10IaN7YaOPM9/hwg+4= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1512) id 20I5jhQl013820 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 18 Jan 2022 14:45:44 +0900 X-SA-MID: 30475371 From: Yuji Ishikawa To: "David S . Miller" , Jakub Kicinski Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nobuhiro1.iwamatsu@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp Subject: [PATCH 1/2] net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL Date: Tue, 18 Jan 2022 14:39:49 +0900 X-TSB-HOP: ON X-TSB-HOP2: ON Message-Id: <20220118053950.2605-2-yuji2.ishikawa@toshiba.co.jp> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118053950.2605-1-yuji2.ishikawa@toshiba.co.jp> References: <20220118053950.2605-1-yuji2.ishikawa@toshiba.co.jp> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" just 0 should be used to represent cleared bits * ETHER_CLK_SEL_DIV_SEL_20 * ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN * ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN * ETHER_CLK_SEL_TX_CLK_O_TX_I * ETHER_CLK_SEL_RMII_CLK_SEL_IN Signed-off-by: Yuji Ishikawa Reviewed-by: Nobuhiro Iwamatsu --- drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-visconti.c index e2e0f9778..43a446cea 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c @@ -22,21 +22,21 @@ #define ETHER_CLK_SEL_RMII_CLK_EN BIT(2) #define ETHER_CLK_SEL_RMII_CLK_RST BIT(3) #define ETHER_CLK_SEL_DIV_SEL_2 BIT(4) -#define ETHER_CLK_SEL_DIV_SEL_20 BIT(0) +#define ETHER_CLK_SEL_DIV_SEL_20 0 #define ETHER_CLK_SEL_FREQ_SEL_125M (BIT(9) | BIT(8)) #define ETHER_CLK_SEL_FREQ_SEL_50M BIT(9) #define ETHER_CLK_SEL_FREQ_SEL_25M BIT(8) #define ETHER_CLK_SEL_FREQ_SEL_2P5M 0 -#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN BIT(0) +#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN 0 #define ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC BIT(10) #define ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV BIT(11) -#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN BIT(0) +#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN 0 #define ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC BIT(12) #define ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV BIT(13) -#define ETHER_CLK_SEL_TX_CLK_O_TX_I BIT(0) +#define ETHER_CLK_SEL_TX_CLK_O_TX_I 0 #define ETHER_CLK_SEL_TX_CLK_O_RMII_I BIT(14) #define ETHER_CLK_SEL_TX_O_E_N_IN BIT(15) -#define ETHER_CLK_SEL_RMII_CLK_SEL_IN BIT(0) +#define ETHER_CLK_SEL_RMII_CLK_SEL_IN 0 #define ETHER_CLK_SEL_RMII_CLK_SEL_RX_C BIT(16) =20 #define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SE= L_TX_CLK_EN) --=20 2.17.1 From nobody Tue Jun 30 12:12:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECE96C433F5 for ; Tue, 18 Jan 2022 07:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232802AbiARHa4 (ORCPT ); Tue, 18 Jan 2022 02:30:56 -0500 Received: from mo-csw-fb1114.securemx.jp ([210.130.202.173]:46878 "EHLO mo-csw-fb.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229474AbiARHaz (ORCPT ); Tue, 18 Jan 2022 02:30:55 -0500 Received: by mo-csw-fb.securemx.jp (mx-mo-csw-fb1114) id 20I5k8FR002771; Tue, 18 Jan 2022 14:46:09 +0900 Received: by mo-csw.securemx.jp (mx-mo-csw1114) id 20I5jmUW030006; Tue, 18 Jan 2022 14:45:48 +0900 X-Iguazu-Qid: 2wHHOe8oPqfgLHbULq X-Iguazu-QSIG: v=2; s=0; t=1642484748; q=2wHHOe8oPqfgLHbULq; m=VAOczg2DnS8QSbYDBwK1TRj1xM0/+Rg5QHs9/nZdNRM= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1113) id 20I5jkJl031006 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 18 Jan 2022 14:45:46 +0900 X-SA-MID: 30475378 From: Yuji Ishikawa To: "David S . Miller" , Jakub Kicinski Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nobuhiro1.iwamatsu@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp Subject: [PATCH 2/2] net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode Date: Tue, 18 Jan 2022 14:39:50 +0900 X-TSB-HOP: ON X-TSB-HOP2: ON Message-Id: <20220118053950.2605-3-yuji2.ishikawa@toshiba.co.jp> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118053950.2605-1-yuji2.ishikawa@toshiba.co.jp> References: <20220118053950.2605-1-yuji2.ishikawa@toshiba.co.jp> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fix= ed. Also, some control bits should be modified with a specific sequence. Signed-off-by: Yuji Ishikawa Reviewed-by: Nobuhiro Iwamatsu --- .../ethernet/stmicro/stmmac/dwmac-visconti.c | 32 ++++++++++++------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-visconti.c index 43a446cea..dde5b772a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c @@ -96,31 +96,41 @@ static void visconti_eth_fix_mac_speed(void *priv, unsi= gned int speed) val |=3D ETHER_CLK_SEL_TX_O_E_N_IN; writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); =20 + /* Set Clock-Mux, Start clock, Set TX_O direction */ switch (dwmac->phy_intf_sel) { case ETHER_CONFIG_INTF_RGMII: val =3D clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); + + val |=3D ETHER_CLK_SEL_RX_TX_CLK_EN; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); + + val &=3D ~ETHER_CLK_SEL_TX_O_E_N_IN; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); break; case ETHER_CONFIG_INTF_RMII: val =3D clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV | - ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN | + ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN | ETHER_CLK_SEL_RMII_CLK_SEL_RX_C; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); + + val |=3D ETHER_CLK_SEL_RMII_CLK_RST; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); + + val |=3D ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); break; case ETHER_CONFIG_INTF_MII: default: val =3D clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC | - ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN | - ETHER_CLK_SEL_RMII_CLK_EN; + ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); + + val |=3D ETHER_CLK_SEL_RX_TX_CLK_EN; + writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); break; } =20 - /* Start clock */ - writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); - val |=3D ETHER_CLK_SEL_RX_TX_CLK_EN; - writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); - - val &=3D ~ETHER_CLK_SEL_TX_O_E_N_IN; - writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); - spin_unlock_irqrestore(&dwmac->lock, flags); } =20 --=20 2.17.1