From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8628C433EF for ; Fri, 14 Jan 2022 15:16:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242742AbiANPQX (ORCPT ); Fri, 14 Jan 2022 10:16:23 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:45208 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242652AbiANPQR (ORCPT ); Fri, 14 Jan 2022 10:16:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173376; x=1673709376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XUOAM/z0skey1/2aHSGp5yId0ktuv9jM+qE4YtnPYMg=; b=xkz8WQJI6AAI1kTS6sR3Uw9vPOE+KCYsk41TkllMvRU7NVpftQvCkirO WbTXi/lEWsZXXeNCTAY8hfNHcqA27Lgfugy7yCDsA9enMkLpFyqPfigHA DqqgiPMrQ7GdSV58dllJXBwknsUv6u0vNqGB5N1VXLbwtIiBvdu6GcCrE m1o1jpuTmUJ8pZ2Umsucfka0rJ8cbd8BPN00hR6gRnUZEzHCEeCmRhxpY SbTwKOLs33dNCYcXjIs7ltl11tev5rKJZ6BO/VVzj/Y0aWlnWwfh3fzSM Z7ZobnWObQv8rZVP1aJXuk4diTRhFdCYkFd7vLYGdt2HLkXIRfyyH/2WG g==; IronPort-SDR: 7bZXMxhI1W6ANOzk/aoRucFoxwWAMmVNSQwQlQiLezS8P01P8wBPS19OtnKWvypYb0p1CReeaU BeOtxx80R+c2gAgEcZIojFy8DpB6czkNmz8B1PDA9fRf1uNh503BHEkectI7uufm9IcJX6HiOQ Qzop4lq7LWIcUmlaWSe2/Ruoojhk9eDw26F06FyTe0fToD0tQnfcVTgDAUyIbTDdo9F7VTq3bH Fb47llcmUFYihcNNUO6s9UwseM3n3hzZUK3wzffTq1SesBMCw+Th1R5dFPOFM1PmN9kob+yxaj i74cDjqGhu8xRybw8iA+axzt X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="150236573" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:16:11 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:16:10 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:04 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles Date: Fri, 14 Jan 2022 15:17:13 +0000 Message-ID: <20220114151727.2319915-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree Reviewed-by: Geert Uytterhoeven Signed-off-by: Conor Dooley --- ...larfire-soc-mailbox.yaml =3D> microchip,mpfs-mailbox.yaml} | 6 +++--- ...s-controller.yaml =3D> microchip,mpfs-sys-controller.yaml} | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-= mailbox.yaml =3D> microchip,mpfs-mailbox.yaml} (82%) rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfir= e-soc-sys-controller.yaml =3D> microchip,mpfs-sys-controller.yaml} (75%) diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-= soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs= -mailbox.yaml similarity index 82% rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-s= oc-mailbox.yaml rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.= yaml index bbb173ea483c..9251c2218c68 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mai= lbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbo= x.yaml#" +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" =20 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailb= ox controller @@ -11,7 +11,7 @@ maintainers: =20 properties: compatible: - const: microchip,polarfire-soc-mailbox + const: microchip,mpfs-mailbox =20 reg: items: @@ -38,7 +38,7 @@ examples: #address-cells =3D <2>; #size-cells =3D <2>; mbox: mailbox@37020000 { - compatible =3D "microchip,polarfire-soc-mailbox"; + compatible =3D "mpfs-mailbox"; reg =3D <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; interrupt-parent =3D <&L1>; interrupts =3D <96>; diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,pola= rfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/micro= chip/microchip,mpfs-sys-controller.yaml similarity index 75% rename from Documentation/devicetree/bindings/soc/microchip/microchip,polar= fire-soc-sys-controller.yaml rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sy= s-controller.yaml index 2cd3bc6bd8d6..f699772fedf3 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-s= oc-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-co= ntroller.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-= sys-controller.yaml#" +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-contr= oller.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" =20 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) syste= m controller @@ -19,7 +19,7 @@ properties: maxItems: 1 =20 compatible: - const: microchip,polarfire-soc-sys-controller + const: microchip,mpfs-sys-controller =20 required: - compatible @@ -30,6 +30,6 @@ additionalProperties: false examples: - | syscontroller: syscontroller { - compatible =3D "microchip,polarfire-soc-sys-controller"; + compatible =3D "microchip,mpfs-sys-controller"; mboxes =3D <&mbox 0>; }; --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E408C43219 for ; Fri, 14 Jan 2022 15:16:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242783AbiANPQ1 (ORCPT ); Fri, 14 Jan 2022 10:16:27 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:50579 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242738AbiANPQX (ORCPT ); Fri, 14 Jan 2022 10:16:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173382; x=1673709382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OOEiOzJYOr2rjLZtIJaPl6yuaJhJGBub8XFzhK4pAzA=; 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Fri, 14 Jan 2022 08:16:20 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:15 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 02/15] dt-bindings: soc/microchip: add services as children of sys ctrlr Date: Fri, 14 Jan 2022 15:17:14 +0000 Message-ID: <20220114151727.2319915-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add mpfs-rng and mpfs-generic-services as children of the system controller. Signed-off-by: Conor Dooley --- .../microchip,mpfs-sys-controller.yaml | 44 +++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-sys-controller.yaml index f699772fedf3..b69386b1a3e1 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-co= ntroller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-co= ntroller.yaml @@ -13,13 +13,45 @@ description: | The PolarFire SoC system controller is communicated with via a mailbox. This document describes the bindings for the client portion of that mail= box. =20 - properties: mboxes: maxItems: 1 =20 compatible: - const: microchip,mpfs-sys-controller + items: + - const: microchip,mpfs-sys-controller + + rng: + type: object + + description: | + The hardware random number generator on the Polarfire SoC is + accessed via the mailbox interface provided by the system controller + + properties: + compatible: + const: microchip,mpfs-rng + + required: + - compatible + + sysserv: + type: object + + description: | + The PolarFire SoC system controller is communicated with via a mailb= ox. + This binding represents several of the functions provided by the sys= tem + controller which do not belong in a specific subsystem, such as read= ing + the fpga device certificate, all of which follow the same format: + - a command + optional payload sent to the sys controller + - a status + a payload returned to Linux + + properties: + compatible: + const: microchip,mpfs-generic-service + + required: + - compatible =20 required: - compatible @@ -29,7 +61,13 @@ additionalProperties: false =20 examples: - | - syscontroller: syscontroller { + syscontroller { compatible =3D "microchip,mpfs-sys-controller"; mboxes =3D <&mbox 0>; + rng: rng { + compatible =3D "microchip,mpfs-rng"; + }; + sysserv: sysserv { + compatible =3D "microchip,mpfs-generic-service"; + }; }; --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7A79C433EF for ; Fri, 14 Jan 2022 15:16:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238417AbiANPQk (ORCPT ); Fri, 14 Jan 2022 10:16:40 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:50624 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242750AbiANPQf (ORCPT ); Fri, 14 Jan 2022 10:16:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173394; x=1673709394; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WIRab6h1hcL8MT7Wt72ljqAGomYq1u7lJ21fWjCYfGU=; b=XHiQ5kQwMhZG28gNpS2bewo3M2MscZsVQhi0IJuxFQM5G+Qh1dEqsGhw y1kNOe3IppxR1Q6IRPou7Jjbn/ejfVQgqIZ5/C7+EM+HhTYd0G7QESXzr 5OsmVmx+k9ItpIyKCll5JQ3g2mU086Jlhkarjb60vAXkyz9mFXworEPOt SXGD6+tnkWwbkmHDSKsKaQ9ckhzgV0TzyEaV7h770stPCC+kEhEamoW6p 6CaBLencxLAmAHyqkWTK80ibBMAkLxopu+KJSr0nqCcvwNnApWpmDGS62 Ese5lRY9K2AjwhuVGdqSWXudOxfTQAwGNWNH5JzLx5Cl8ZRtkzN5dMQVR Q==; IronPort-SDR: HbKIBJDyXoXla2Re69L7lEFZqn/vZmN5/+QF+7y6aR8BCvGbcwan8zI6aBYo7C9ViM2zwLelqd 8RYjH0rUej5VOatEeglxnNq18OIahyzjuCmv3F9cb4Lbj3FEBb2GR50kSur/gHfcNdcKztf8Qr p+7m1p67jxhqBvS9BQ/SlDUPnKOwQRnm5Ptc7H7X9rmuPtaDe6j6akQsnJiIVCXWthn9uCVEf6 xhjxh3hDGjSMtMrNcs+ABl5QWSlhZcqM+Ijljk1DFPAE0DdsNLYtHV18dXedAEGgioyFxhB3vA GAYpiISfc9ga40ZpfVwix6Pu X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="142730841" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:16:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:16:33 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:27 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string Date: Fri, 14 Jan 2022 15:17:15 +0000 Message-ID: <20220114151727.2319915-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree. Reviewed-by: Geert Uytterhoeven Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 0d6e2231a2c7..4e34854d1238 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -232,7 +232,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev) } =20 static const struct of_device_id mpfs_mbox_of_match[] =3D { - {.compatible =3D "microchip,polarfire-soc-mailbox", }, + {.compatible =3D "microchip,mpfs-mailbox", }, {}, }; MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match); --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9140EC433FE for ; Fri, 14 Jan 2022 15:16:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242530AbiANPQr (ORCPT ); Fri, 14 Jan 2022 10:16:47 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8118 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242762AbiANPQm (ORCPT ); Fri, 14 Jan 2022 10:16:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173402; x=1673709402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wWDJRTpp9y+U/y/0XA3ayvzfqpzbVzNVpbQ9F2yWO+o=; b=Qdk09MY4riUJzmbMYwm3ek7z/n4DCy9Z4ceio9me93k20P6LoZA5+9j/ 4DNi2kmzVt950JY1baE8Rb97g1jOwirM91RtxLXvCTIK6T9mXIjMTv7tA CJQSiSzSJWpQZZJh8Q/ASlCBsB+AvlMCJRU+SEWQ7LcCm8z4pEskkdzJQ XweM3OkVp3/FVS4dT0mw84N0kaJKe76KmwfHkdOnsl4cXYzPHoWB1tY7H wpHhBf4419EiS9l+X1inswlBtV/i3wr/ZrPqGCJ8uL+HI/ZuSG6l4onEK w1gB2Xmu4ZgPkZ0euzRSWNYCV91vVCv7vVT7zpUMjU5+OssxDfxN21fdl Q==; IronPort-SDR: 7THUJYzdHvfCAk1hHen0bIy/vPUs/6gvtCaHheXXBwOadZP0AcxVv9vIkMP3CmLz2olh8o6ZRM l72dv2FwGwHcsVhB/N4/EgIEowFd1MMmUSxQxSRa8a3yKgydidkLgvBHQGl53plT7YaLiam53g jDp8YDJmYU3joNyjEGfzeJeffJp6RsjfToAJALRxa8ajI32KJ1VYFKWZ7n9BPwVvY9AOztrMwx m5te96aFxX+awZDlZycEb553KG9MbpPYqVxfb9+eFkbV/qdpMwq4bjhVsQO1Lcmkx2TvPjTF28 84JgPucTQ/5L1L3XFrlxCc7C X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="149688457" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:16:41 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:16:40 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:35 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 04/15] dt-bindings: i2c: add bindings for microchip mpfs i2c Date: Fri, 14 Jan 2022 15:17:16 +0000 Message-ID: <20220114151727.2319915-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add device tree bindings for the i2c controller on the Microchip PolarFire SoC. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/i2c/microchip,mpfs-i2c.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2= c.yaml diff --git a/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml = b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml new file mode 100644 index 000000000000..ced843e78844 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/microchip,mpfs-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS I2C Controller Device Tree Bindings + +maintainers: + - Daire McNamara + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs + - microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: | + Desired I2C bus clock frequency in Hz. As only Standard and Fast + modes are supported, possible values are 100000 and 400000. + enum: [100000, 400000] + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + i2c@2010a000 { + compatible =3D "microchip,mpfs-i2c"; + reg =3D <0x2010a000 0x1000>; + clocks =3D <&clkcfg CLK_I2C0>; + interrupt-parent =3D <&plic>; + interrupts =3D <58>; + clock-frequency =3D <100000>; + }; +... --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57216C433FE for ; Fri, 14 Jan 2022 15:17:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242795AbiANPRH (ORCPT ); Fri, 14 Jan 2022 10:17:07 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8158 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242559AbiANPQx (ORCPT ); Fri, 14 Jan 2022 10:16:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173413; x=1673709413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5baoYDs4ELaVf+UVRyjfHOs/OiFrzXQn74tyS9s7agE=; b=IED9hjlySnisy6G4/ZNHeXK5kptsd5LUfN5ND+IHcyHruLK2S32xdcLO Ri2PvoN5p+r46OtorL0E6rphw5fVhoEABWU4UvqOHHfaQLYsUij1+pG67 teiKoUh0u7rQdCe3H8vEVa7MhHCD1w86CUaj3gTzNRZoxboPIqDl+uOox Izsdo/+U7kYpj2VMHDqmVch402OdAaCtyZ7uyqwJeFk/U2ls0Xl8ot12G +jXqKoXxU+n4kJdV41hjGsTxlsPm4r+jydkJPHTEANz88+8+dKfGd1pwS qEnPngXo93GvMN5FdhKDNYGPf97h8BEtkLoZoJ9BblgX8S1NGzwNzyzWC A==; IronPort-SDR: foIQvTnln6Mw6g1f5/p+LYDqHkSRPmpyJo6Uii3sbhIShq93syCT5/uSf1A19jMQcRW8x/L0ON P27E50h33pnTaBYd2yejE+Qrtagcp+a0ImiHyhC0pCEXAiXtHTVnnDFmPJOYFQakXjJ58HkyX+ qvNxvKB/uM65oZtpiq5vFGlQg1KWB1mh+L+wjkkXAXuoiFaHD8t4kV07EaH6g4HAW8GVhgaKtx xvukpeAMzM5p8vc4JZCGfohhfeumEPSQoGfjhuwMOHpo+yQHOogYn0U9uITHmyltQNZOBjb7yZ u410jeuA1R9xk8vTtoi5YTGa X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="149688511" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:16:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:16:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:44 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 05/15] dt-bindings: rtc: add bindings for microchip mpfs rtc Date: Fri, 14 Jan 2022 15:17:17 +0000 Message-ID: <20220114151727.2319915-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rt= c.yaml diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml = b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file mode 100644 index 000000000000..d57460cbe5e3 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + enum: + - microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + microchip,prescaler: + description: | + The prescaler divides the input frequency to create a time-based str= obe (typically 1 Hz) for + the calendar counter. The Alarm and Compare Registers, in conjunctio= n with the calendar + counter, facilitate time-matched events. To properly operate in Cale= ndar or Binary mode, + the 26-bit prescaler must be programmed to generate a strobe to the = RTC. + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + rtc@20124000 { + compatible =3D "microchip,mpfs-rtc"; + reg =3D <0x20124000 0x1000>; + clocks =3D <&clkcfg CLK_RTC>; + clock-names =3D "rtc"; + interrupts =3D <80>, <81>; + }; +... --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34ABFC433FE for ; Fri, 14 Jan 2022 15:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242802AbiANPRO (ORCPT ); Fri, 14 Jan 2022 10:17:14 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:60739 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229863AbiANPRA (ORCPT ); Fri, 14 Jan 2022 10:17:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173419; x=1673709419; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bIBkUQ3vjh7oytk/bGgn66qU7zWZlgKxXGlgkCOqeic=; b=BdXYJaJ0/8XgtFtGNgc1zkFEx+UwOqW6SE0hrivX/oLUfS2cgFsW5S9w v5f/fBg97cnP1DA4+X5cy0TbfG4qL+ojyR5UimgzC6TpUq1h5uzZ0aODJ TXHKy4mYa6xfDVUa0/hwoTIaEJKUFFhQIdy/nPjrdelPFqaLAWuXR13tS oENhQwfuVeUo9OSAEw7zf1vnZL/zL6Zkh2IQESXVUq98C3k897yMVPFAG OwsONMmw7GsIGXO0Pl5q1HxzfO8W2HziDS99T3qZIrgAGkTN02dhmbJyQ 7X95aNb56Jv/z801eI2oX3zmSunXBBxdiLdifNw0kFkZQL7OYIjDYe1Lq w==; IronPort-SDR: bE4AnhYMDYFQHqm6JsGS0tkSheiZnFHEyEOWGa6J0vD6NTieekAJmnDCdkzTbQDkmlJuRprg/5 t7/52qxrEv9vTs6gmkp2ZTjNbphbItrgS7yHROFyrILqpCs7zk8cDPOIfhflWjEPSY0qDRNuGb NzN2Z3P7jFlXBs9bwQuViuHOagdbylx0Tn2IHAMPCXDb6Oei0mIvpPJ0+GlIaLe2nHLQKa8AdR //sRYggnDOS7mAOXQY4XTBxsN10szojs7Z1P5grxjog7O0+C2SMkIEqugE9lhLLNqlZtPoUBVN UB7qwWr/gKs2SfnomSFsXfna X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="158697743" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:16:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:16:57 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:51 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 06/15] dt-bindings: gpio: add bindings for microchip mpfs gpio Date: Fri, 14 Jan 2022 15:17:18 +0000 Message-ID: <20220114151727.2319915-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-g= pio.yaml diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yam= l b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file mode 100644 index 000000000000..47a76f0e32b9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS GPIO Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +properties: + compatible: + items: + - enum: + - microchip,mpfs-gpio + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + "#interrupt-cells": + const: 1 + + ngpios: + description: + The number of GPIOs available. + minimum: 1 + maximum: 32 + default: 32 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - interrupt-controller + - "#gpio-cells" + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + gpio@20122000 { + compatible =3D "microchip,mpfs-gpio"; + reg =3D <0x20122000 0x1000>; + clocks =3D <&clkcfg CLK_GPIO2>; + interrupt-parent =3D <&plic>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + }; +... --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E60A0C433FE for ; Fri, 14 Jan 2022 15:17:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242928AbiANPRS (ORCPT ); Fri, 14 Jan 2022 10:17:18 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:50678 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239003AbiANPRH (ORCPT ); Fri, 14 Jan 2022 10:17:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173426; x=1673709426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lpP0lJkn+kaM0L/dSWda42EaX0finN6iz9h/n2ezhV4=; b=w31JYp2MXfmi6mlO1dDNAihgSyzbHPDNNffTh3bJK8zKxLIjFG7ePqLM ts9HPWD9iEqkQ5EDFBZN2vopS0qMFZ2oXUzCWtXqtEGqgLtlchfIc75Fr ZKDDUHnaYhRL0VZku0VtNJUonFCeLI7zoGmrA9tEhREVBitFP5vKsFWmK k/nc8hRI8dVqNnOzoY9xw4f8UJvGJ/vs7hoZMU1BczFLmw2n9dUDRaGEy u99zDYB9IXSIbiB+JHpfwL4QI/oZU4POk9fLm0f7HKeB4brqsdHHZbDgq HEcuEgLIVhryg3TytHNaFm7Y7TwL6Z3nb83f588uX0zyJ7GH3ifSmyzaZ g==; IronPort-SDR: kL4RnFizd87JjLb3wBExb9VGp/CQLgM9veBpyNfYNTt4VZmRcCsq3hqrBznCBZiOMZCFnx9okJ foSSuR27NRK8A7nKbyyejmO8W2SiHFvJ+90ihRZiU6yEHQ4T5P3qG9AAxgVAuLF5FxboZyVqzG cS/LkpRsKRtOd7wxYquw2dlGdo4+LVj6E5LFHCFhh+tFey09pnrpVzHzldUsv2Hcaj/OTG3UTv Uc6vIjwssw0VukRe9MizhaLB9oy5zH+ljRxPw9o4u11i4UYEcNSpwqowoexC2Pm8MXnaW+uAYq zYupVGPBuB+ZKQ3gjfbMPnIt X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="142730876" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:17:04 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:17:04 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:16:58 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 07/15] dt-bindings: spi: add bindings for microchip mpfs spi Date: Fri, 14 Jan 2022 15:17:19 +0000 Message-ID: <20220114151727.2319915-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add device tree bindings for the {q,}spi controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/spi/microchip,mpfs-spi.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-sp= i.yaml diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml = b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml new file mode 100644 index 000000000000..ece261b8e963 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + enum: + - microchip,mpfs-spi + - microchip,mpfs-qspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + spi@20108000 { + compatible =3D "microchip,mpfs-spi"; + reg =3D <0x20108000 0x1000>; + clocks =3D <&clkcfg CLK_SPI0>; + interrupt-parent =3D <&plic>; + interrupts =3D <54>; + spi-max-frequency =3D <25000000>; + }; +... --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E0CCC4167D for ; Fri, 14 Jan 2022 15:17:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242523AbiANPRW (ORCPT ); Fri, 14 Jan 2022 10:17:22 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:50699 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242886AbiANPRN (ORCPT ); Fri, 14 Jan 2022 10:17:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173432; x=1673709432; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+qPRXox7zPzI+myjQz8NC5TP9D5voUl5Cp51OFrTMa8=; b=XTHsGst4bMv67gKdofTTX809TGBjhF4Gpfmf3UrdSIs0vtsSld11U6Zm rQ3liVj14/yxBknT08D0OCFeEn6Qv2ZRbNI6h+klFB0TCnL6mCT/Kc8T6 yWMTiQ93eO+L8UV8WQPBYABR/tZSVHNgDG6gZTsyvJCfovLiJ7iazgGzW ojAT5yUuRj5hc8XtLqeA31s2NIcz0Yke0ZcHbgoofyoRJ1647XQkbtf9J 5H80p4CCDmyx1GIO3V145M+k5InmSE0ACqrpk5XgFp4OXWX303XZYe3B0 nlLBAirVwc4JBKZbIj58rV6Q0IldsLK+NXI6d/NZeP1h3pLX1p5TomRVL Q==; IronPort-SDR: pv1M3xpiwF4GwIuMI+y3FQnMDgMJogxLnT3187uonLweWF6/G9UfkbLepORDDd8bG7yn6jm5tN nnMJ0cJN8/lPD3bLaAqcKsxlY+1fjVJNOiTqp0AsC866FkUOV3Re+icAsmeST3PVp2GDkEmz25 cygmWSJNt2M953p0ZcLMS2RhhS3BKDLyC5yPmIrMf1Z+o5cBEqvowR9hCdkwPIGTvLOlVfnxCb Tq2y8igpUDBnvAIpvhifRPFWsZbndr2Y5Gxf7JH4c5SMptzcx9uSP00enpXLKeWowUmQSFnk20 z76AZYgCSKNnCqs25q1nTtTz X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="142730887" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:17:11 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:17:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:17:05 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 08/15] dt-bindings: usb: add bindings for microchip mpfs musb Date: Fri, 14 Jan 2022 15:17:20 +0000 Message-ID: <20220114151727.2319915-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add device tree bindings for the usb controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../bindings/usb/microchip,mpfs-musb.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-mu= sb.yaml diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml= b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml new file mode 100644 index 000000000000..48c458c65848 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS USB Controller Device Tree Bindings + +allOf: + - $ref: usb-drd.yaml# + +maintainers: + - Conor Dooley + +properties: + compatible: + enum: + - microchip,mpfs-musb + + dr_mode: true + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + items: + - const: dma + - const: mc + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + usb@20201000 { + compatible =3D "microchip,mpfs-musb"; + reg =3D <0x20201000 0x1000>; + clocks =3D <&clkcfg CLK_USB>; + interrupt-parent =3D <&plic>; + interrupts =3D <86>, <87>; + interrupt-names =3D "dma", "mc"; + dr_mode =3D "host"; + }; + +... --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C508DC4167B for ; Fri, 14 Jan 2022 15:17:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242862AbiANPRj (ORCPT ); Fri, 14 Jan 2022 10:17:39 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:45331 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242976AbiANPRX (ORCPT ); Fri, 14 Jan 2022 10:17:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173443; x=1673709443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m4uG6fn9Ja8wYJxOVT09ajA8/irJHQR89DHN80WIHNs=; b=gyffGj0B6q7n3ROkDKo5lScO/ptwk2l/Nl0Pd9xadJdG7TE75eVaLWp9 o8F6Putd1SbdppybzPvKwQu1VteaVJHyTIWxPbg/KCZhIBPH1JHPKAPTa GjeFOpRNm+t5VlpBWSALfNVHWy44rBl9NeIMC/GUqms8psze8paa2NMTu 5YF+o6uWSGic0FF9dU3kE6x0QTe6mDRU9vvPuGGOcPtanpYagIIyfrWiq snePOoEffywLxDheXB3JvTWRuAqjlbOJcqhp2ghSThS3jqOdDwzfALr3q PV1P2JwoqoWR/1QpDCBL95UPSzUIalJmOkkztqlDxcW3Lsxo76MUBblnl w==; IronPort-SDR: 7WWftUvpn13G7qKUhXOz04JEV8/kCBG7ebs/rTJS2i4v2zFKV3EqpZTDzTaw808lER9PFlVDBb nY41tojVN326tiTitHsZ9Ou6NjITYOtdXPSeUJNoiCOpOUeLsrsmUyzFiDx6+hHqkNUpklNHTW ZItxpo+7ZALCCY5lPXVyXj6VIuL8NepKh8cDQg3bvY/l2i963o4oFHyPuyNLejrVQY4ULMSNZo vGS03LN+E/YAPHvGdN8C/gDFhZoCebIK5uwoZl0ANnn+spb1hNwVzk9DddQNMMJGJZJ3X7172m eMHce+RQ43VbhHaWwr4fvC1d X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="150236722" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:17:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:17:21 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:17:15 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 09/15] dt-bindings: pwm: add microchip corepwm binding Date: Fri, 14 Jan 2022 15:17:21 +0000 Message-ID: <20220114151727.2319915-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add device tree bindings for the Microchip fpga fabric based "core" PWM con= troller. Signed-off-by: Conor Dooley --- .../bindings/pwm/microchip,corepwm.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b= /Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml new file mode 100644 index 000000000000..26a77cde2465 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip ip core PWM controller bindings + +maintainers: + - Conor Dooley + +description: | + corePWM is an 16 channel pulse width modulator FPGA IP + + https://www.microsemi.com/existing-parts/parts/152118 + +properties: + compatible: + items: + - const: microchip,corepwm-rtl-v4 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + + microchip,sync-update: + description: | + In synchronous mode, all channels are updated at the beginning of th= e PWM period. + Asynchronous mode is relevant to applications such as LED control, w= here + synchronous updates are not required. Asynchronous mode lowers the a= rea size, + reducing shadow register requirements. This can be set at run time, = provided + SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstrea= m programmed + to the device. + Each bit corresponds to a PWM channel & represents whether synchrono= us mode is + possible for the PWM channel. + + $ref: /schemas/types.yaml#/definitions/uint16 + default: 0 + + microchip,dac-mode: + description: | + Optional, per-channel Low Ripple DAC mode is possible on this IP cor= e. It creates + a minimum period pulse train whose High/Low average is that of the c= hosen duty + cycle. This "DAC" will have far better bandwidth and ripple performa= nce than the + standard PWM algorithm can achieve. + Each bit corresponds to a PWM channel & represents whether dac mode = is enabled + that PWM channel. + + $ref: /schemas/types.yaml#/definitions/uint16 + default: 0 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + pwm@41000000 { + compatible =3D "microchip,corepwm-rtl-v4"; + microchip,sync-update =3D /bits/ 16 <0>; + clocks =3D <&clkcfg CLK_FIC3>; + reg =3D <0x41000000 0xF0>; + #pwm-cells =3D <2>; + }; --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC6CBC433F5 for ; Fri, 14 Jan 2022 15:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229884AbiANPRs (ORCPT ); Fri, 14 Jan 2022 10:17:48 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:8255 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242880AbiANPRf (ORCPT ); Fri, 14 Jan 2022 10:17:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173454; x=1673709454; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fNSJRc4zcAnu3goaOseox9vQTabpFxy5Ys0dDRtHxM4=; b=MhhDuh/KJOD/F/p261zFvrzwfhabpagOkygLJvzNZ/OiHcuKG6t0h1uO cPlQUvepxIEtpPkf9NZKOJTvkd0RXXoH7oQrPCXXchQ4tHD0rvhUgIbSu S8tzd2QbA2WlkKS42POrYMfYhSWyieicO8LjQzjHRb2LnqwtGi9sTh/TT v2FlVn+8Rr9kARv9d9GIkDWCSuhDVLv39r39OcyNQAZUVjuEVViGFNXTS Iv3g4b4t0BAAAVAwhu8WHjYdjBmBBVh2iT1v5ZQHOoaakY29aY2TZuXpd 9JwPXNI/Ki5UYQ3RiWSJMoA8dK9cELX91FklQpAqdXcw62XIqvnD6r2z5 A==; IronPort-SDR: 9JiDrU14FgcxF40fz4FmenQP96BEz4U0M9gdGbDiMzSKZrbaDwSTz/i4Vtf8j8I79/2YxI0lP+ XtKujfkRF5X2xC8vKoRa+q/KCDkC/VTLNc2RdTcTkQx7h1rIm50M8LCLJ5ojLPbprbtIWN36yO JSNBlYxUW7mlB+TAN+SpNkiPsicxSInEzPc1KBDuQOprZaK0wiosGUqLaVtxbS5pXOd7t9Q6rF djGGb1kqSZSuN3sYrNkFDEbW4S1a6y9jh8V/WT2amPGkok4fqqY3PMsxuxAmYBCfilYIWLp+vm 2XI0CmJASP3S9QMs5Ib+9GDY X-IronPort-AV: E=Sophos;i="5.88,289,1635231600"; d="scan'208";a="149688662" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:17:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:17:29 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:17:23 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 10/15] riscv: dts: microchip: use clk defines for icicle kit Date: Fri, 14 Jan 2022 15:17:22 +0000 Message-ID: <20220114151727.2319915-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Update the Microchip Icicle kit device tree by replacing clock related magic numbers with their defined counterparts. Signed-off-by: Conor Dooley --- .../microchip/microchip-mpfs-icicle-kit.dts | 2 +- .../boot/dts/microchip/microchip-mpfs.dtsi | 25 ++++++++++--------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 0c748ae1b006..6d19ba196f12 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -31,7 +31,7 @@ cpus { memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x40000000>; - clocks =3D <&clkcfg 26>; + clocks =3D <&clkcfg CLK_DDRC>; }; }; =20 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 869aaf0d5c06..717e39b30a15 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2020 Microchip Technology Inc */ =20 /dts-v1/; +#include "dt-bindings/clock/microchip,mpfs-clock.h" =20 / { #address-cells =3D <2>; @@ -14,7 +15,6 @@ cpus { #size-cells =3D <0>; =20 cpu@0 { - clock-frequency =3D <0>; compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; device_type =3D "cpu"; i-cache-block-size =3D <64>; @@ -22,6 +22,7 @@ cpu@0 { i-cache-size =3D <16384>; reg =3D <0>; riscv,isa =3D "rv64imac"; + clocks =3D <&clkcfg CLK_CPU>; status =3D "disabled"; =20 cpu0_intc: interrupt-controller { @@ -32,7 +33,6 @@ cpu0_intc: interrupt-controller { }; =20 cpu@1 { - clock-frequency =3D <0>; compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -48,6 +48,7 @@ cpu@1 { mmu-type =3D "riscv,sv39"; reg =3D <1>; riscv,isa =3D "rv64imafdc"; + clocks =3D <&clkcfg CLK_CPU>; tlb-split; status =3D "okay"; =20 @@ -59,7 +60,6 @@ cpu1_intc: interrupt-controller { }; =20 cpu@2 { - clock-frequency =3D <0>; compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -75,6 +75,7 @@ cpu@2 { mmu-type =3D "riscv,sv39"; reg =3D <2>; riscv,isa =3D "rv64imafdc"; + clocks =3D <&clkcfg CLK_CPU>; tlb-split; status =3D "okay"; =20 @@ -86,7 +87,6 @@ cpu2_intc: interrupt-controller { }; =20 cpu@3 { - clock-frequency =3D <0>; compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -102,6 +102,7 @@ cpu@3 { mmu-type =3D "riscv,sv39"; reg =3D <3>; riscv,isa =3D "rv64imafdc"; + clocks =3D <&clkcfg CLK_CPU>; tlb-split; status =3D "okay"; =20 @@ -113,7 +114,6 @@ cpu3_intc: interrupt-controller { }; =20 cpu@4 { - clock-frequency =3D <0>; compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -129,6 +129,7 @@ cpu@4 { mmu-type =3D "riscv,sv39"; reg =3D <4>; riscv,isa =3D "rv64imafdc"; + clocks =3D <&clkcfg CLK_CPU>; tlb-split; status =3D "okay"; cpu4_intc: interrupt-controller { @@ -210,7 +211,7 @@ serial0: serial@20000000 { interrupt-parent =3D <&plic>; interrupts =3D <90>; current-speed =3D <115200>; - clocks =3D <&clkcfg 8>; + clocks =3D <&clkcfg CLK_MMUART0>; status =3D "disabled"; }; =20 @@ -222,7 +223,7 @@ serial1: serial@20100000 { interrupt-parent =3D <&plic>; interrupts =3D <91>; current-speed =3D <115200>; - clocks =3D <&clkcfg 9>; + clocks =3D <&clkcfg CLK_MMUART1>; status =3D "disabled"; }; =20 @@ -234,7 +235,7 @@ serial2: serial@20102000 { interrupt-parent =3D <&plic>; interrupts =3D <92>; current-speed =3D <115200>; - clocks =3D <&clkcfg 10>; + clocks =3D <&clkcfg CLK_MMUART2>; status =3D "disabled"; }; =20 @@ -246,7 +247,7 @@ serial3: serial@20104000 { interrupt-parent =3D <&plic>; interrupts =3D <93>; current-speed =3D <115200>; - clocks =3D <&clkcfg 11>; + clocks =3D <&clkcfg CLK_MMUART3>; status =3D "disabled"; }; =20 @@ -256,7 +257,7 @@ mmc: mmc@20008000 { reg =3D <0x0 0x20008000 0x0 0x1000>; interrupt-parent =3D <&plic>; interrupts =3D <88>, <89>; - clocks =3D <&clkcfg 6>; + clocks =3D <&clkcfg CLK_MMC>; max-frequency =3D <200000000>; status =3D "disabled"; }; @@ -267,7 +268,7 @@ emac0: ethernet@20110000 { interrupt-parent =3D <&plic>; interrupts =3D <64>, <65>, <66>, <67>; local-mac-address =3D [00 00 00 00 00 00]; - clocks =3D <&clkcfg 4>, <&clkcfg 2>; + clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; status =3D "disabled"; #address-cells =3D <1>; @@ -280,7 +281,7 @@ emac1: ethernet@20112000 { interrupt-parent =3D <&plic>; interrupts =3D <70>, <71>, <72>, <73>; local-mac-address =3D [00 00 00 00 00 00]; - clocks =3D <&clkcfg 5>, <&clkcfg 2>; + clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; status =3D "disabled"; clock-names =3D "pclk", "hclk"; #address-cells =3D <1>; --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1F2BC4321E for ; Fri, 14 Jan 2022 15:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242891AbiANPRw (ORCPT ); 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d="scan'208";a="82522738" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2022 08:17:39 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 14 Jan 2022 08:17:39 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:17:33 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 11/15] riscv: dts: microchip: add fpga fabric section to icicle kit Date: Fri, 14 Jan 2022 15:17:23 +0000 Message-ID: <20220114151727.2319915-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric. Signed-off-by: Conor Dooley --- .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++ .../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 1 + 3 files changed, 34 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arc= h/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi new file mode 100644 index 000000000000..c1dcd56b0679 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + core_pwm0: pwm@41000000 { + compatible =3D "microchip,corepwm-rtl-v4"; + reg =3D <0x0 0x41000000 0x0 0xF0>; + microchip,sync-update =3D /bits/ 16 <0>; + #pwm-cells =3D <2>; + clocks =3D <&clkcfg CLK_FIC3>; + status =3D "disabled"; + }; + + i2c2: i2c@44000000 { + compatible =3D "microchip,corei2c-rtl-v7"; + reg =3D <0x0 0x44000000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkcfg CLK_FIC3>; + interrupt-parent =3D <&plic>; + interrupts =3D <122>; + clock-frequency =3D <100000>; + status =3D "disabled"; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 6d19ba196f12..ab803f71626a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -68,6 +68,10 @@ &mmc { sd-uhs-sdr104; }; =20 +&i2c2 { + status =3D "okay"; +}; + &emac0 { phy-mode =3D "sgmii"; phy-handle =3D <&phy0>; @@ -86,3 +90,7 @@ phy1: ethernet-phy@9 { ti,fifo-depth =3D <0x01>; }; }; + +&core_pwm0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 717e39b30a15..c7d73756c9b8 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -3,6 +3,7 @@ =20 /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" +#include "microchip-mpfs-fabric.dtsi" =20 / { #address-cells =3D <2>; --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE19EC433FE for ; Fri, 14 Jan 2022 15:17:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242971AbiANPRz (ORCPT ); Fri, 14 Jan 2022 10:17:55 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:60849 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242895AbiANPRt (ORCPT ); Fri, 14 Jan 2022 10:17:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173469; x=1673709469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Fri, 14 Jan 2022 08:17:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:17:41 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 12/15] riscv: dts: microchip: refactor icicle kit device tree Date: Fri, 14 Jan 2022 15:17:24 +0000 Message-ID: <20220114151727.2319915-13-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by: Conor Dooley --- .../microchip/microchip-mpfs-icicle-kit.dts | 37 ++--- .../boot/dts/microchip/microchip-mpfs.dtsi | 65 +++++---- arch/riscv/configs/icicle_kit_defconfig | 134 ++++++++++++++++++ 3 files changed, 186 insertions(+), 50 deletions(-) create mode 100644 arch/riscv/configs/icicle_kit_defconfig diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index ab803f71626a..c51bd7cf500f 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 /dts-v1/; =20 @@ -13,11 +13,11 @@ / { compatible =3D "microchip,mpfs-icicle-kit", "microchip,mpfs"; =20 aliases { - ethernet0 =3D &emac1; - serial0 =3D &serial0; - serial1 =3D &serial1; - serial2 =3D &serial2; - serial3 =3D &serial3; + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; }; =20 chosen { @@ -39,19 +39,19 @@ &refclk { clock-frequency =3D <600000000>; }; =20 -&serial0 { +&mmuart0 { status =3D "okay"; }; =20 -&serial1 { +&mmuart1 { status =3D "okay"; }; =20 -&serial2 { +&mmuart2 { status =3D "okay"; }; =20 -&serial3 { +&mmuart3 { status =3D "okay"; }; =20 @@ -61,7 +61,10 @@ &mmc { bus-width =3D <4>; disable-wp; cap-sd-highspeed; + cap-mmc-highspeed; card-detect-delay =3D <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; @@ -72,22 +75,22 @@ &i2c2 { status =3D "okay"; }; =20 -&emac0 { +&mac0 { phy-mode =3D "sgmii"; phy-handle =3D <&phy0>; - phy0: ethernet-phy@8 { - reg =3D <8>; - ti,fifo-depth =3D <0x01>; - }; }; =20 -&emac1 { +&mac1 { status =3D "okay"; phy-mode =3D "sgmii"; phy-handle =3D <&phy1>; phy1: ethernet-phy@9 { reg =3D <9>; - ti,fifo-depth =3D <0x01>; + ti,fifo-depth =3D <0x1>; + }; + phy0: ethernet-phy@8 { + reg =3D <8>; + ti,fifo-depth =3D <0x1>; }; }; =20 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index c7d73756c9b8..62bd00092bcc 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" @@ -15,7 +15,7 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - cpu@0 { + cpu0: cpu@0 { compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; device_type =3D "cpu"; i-cache-block-size =3D <64>; @@ -33,7 +33,7 @@ cpu0_intc: interrupt-controller { }; }; =20 - cpu@1 { + cpu1: cpu@1 { compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -60,7 +60,7 @@ cpu1_intc: interrupt-controller { }; }; =20 - cpu@2 { + cpu2: cpu@2 { compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller { }; }; =20 - cpu@3 { + cpu3: cpu@3 { compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -114,7 +114,7 @@ cpu3_intc: interrupt-controller { }; }; =20 - cpu@4 { + cpu4: cpu@4 { compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size =3D <64>; d-cache-sets =3D <64>; @@ -152,8 +152,9 @@ soc { compatible =3D "simple-bus"; ranges; =20 - cache-controller@2010000 { + cctrllr: cache-controller@2010000 { compatible =3D "sifive,fu540-c000-ccache", "cache"; + reg =3D <0x0 0x2010000 0x0 0x1000>; cache-block-size =3D <64>; cache-level =3D <2>; cache-sets =3D <1024>; @@ -161,10 +162,9 @@ cache-controller@2010000 { cache-unified; interrupt-parent =3D <&plic>; interrupts =3D <1>, <2>, <3>; - reg =3D <0x0 0x2010000 0x0 0x1000>; }; =20 - clint@2000000 { + clint: clint@2000000 { compatible =3D "sifive,fu540-c000-clint", "sifive,clint0"; reg =3D <0x0 0x2000000 0x0 0xC000>; interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, @@ -174,6 +174,15 @@ clint@2000000 { <&cpu4_intc 3>, <&cpu4_intc 7>; }; =20 + dma@3000000 { + compatible =3D "sifive,fu540-c000-pdma"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic>; + interrupts =3D <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; + #dma-cells =3D <1>; + }; + plic: interrupt-controller@c000000 { compatible =3D "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xc000000 0x0 0x4000000>; @@ -188,15 +197,6 @@ plic: interrupt-controller@c000000 { riscv,ndev =3D <186>; }; =20 - dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; - reg =3D <0x0 0x3000000 0x0 0x8000>; - interrupt-parent =3D <&plic>; - interrupts =3D <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>; - #dma-cells =3D <1>; - }; - clkcfg: clkcfg@20002000 { compatible =3D "microchip,mpfs-clkcfg"; reg =3D <0x0 0x20002000 0x0 0x1000>; @@ -204,7 +204,7 @@ clkcfg: clkcfg@20002000 { #clock-cells =3D <1>; }; =20 - serial0: serial@20000000 { + mmuart0: serial@20000000 { compatible =3D "ns16550a"; reg =3D <0x0 0x20000000 0x0 0x400>; reg-io-width =3D <4>; @@ -216,7 +216,7 @@ serial0: serial@20000000 { status =3D "disabled"; }; =20 - serial1: serial@20100000 { + mmuart1: serial@20100000 { compatible =3D "ns16550a"; reg =3D <0x0 0x20100000 0x0 0x400>; reg-io-width =3D <4>; @@ -228,7 +228,7 @@ serial1: serial@20100000 { status =3D "disabled"; }; =20 - serial2: serial@20102000 { + mmuart2: serial@20102000 { compatible =3D "ns16550a"; reg =3D <0x0 0x20102000 0x0 0x400>; reg-io-width =3D <4>; @@ -240,7 +240,7 @@ serial2: serial@20102000 { status =3D "disabled"; }; =20 - serial3: serial@20104000 { + mmuart3: serial@20104000 { compatible =3D "ns16550a"; reg =3D <0x0 0x20104000 0x0 0x400>; reg-io-width =3D <4>; @@ -257,37 +257,36 @@ mmc: mmc@20008000 { compatible =3D "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg =3D <0x0 0x20008000 0x0 0x1000>; interrupt-parent =3D <&plic>; - interrupts =3D <88>, <89>; + interrupts =3D <88>; clocks =3D <&clkcfg CLK_MMC>; max-frequency =3D <200000000>; status =3D "disabled"; }; =20 - emac0: ethernet@20110000 { + mac0: ethernet@20110000 { compatible =3D "cdns,macb"; reg =3D <0x0 0x20110000 0x0 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <0>; interrupt-parent =3D <&plic>; - interrupts =3D <64>, <65>, <66>, <67>; + interrupts =3D <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; status =3D "disabled"; - #address-cells =3D <1>; - #size-cells =3D <0>; }; =20 - emac1: ethernet@20112000 { + mac1: ethernet@20112000 { compatible =3D "cdns,macb"; reg =3D <0x0 0x20112000 0x0 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <0>; interrupt-parent =3D <&plic>; - interrupts =3D <70>, <71>, <72>, <73>; + interrupts =3D <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - status =3D "disabled"; clock-names =3D "pclk", "hclk"; - #address-cells =3D <1>; - #size-cells =3D <0>; + status =3D "disabled"; }; - }; }; diff --git a/arch/riscv/configs/icicle_kit_defconfig b/arch/riscv/configs/i= cicle_kit_defconfig new file mode 100644 index 000000000000..f484130e723d --- /dev/null +++ b/arch/riscv/configs/icicle_kit_defconfig @@ -0,0 +1,134 @@ +CONFIG_SYSVIPC=3Dy +CONFIG_POSIX_MQUEUE=3Dy +CONFIG_NO_HZ_IDLE=3Dy +CONFIG_HIGH_RES_TIMERS=3Dy +CONFIG_IKCONFIG=3Dy +CONFIG_IKCONFIG_PROC=3Dy +CONFIG_CGROUPS=3Dy +CONFIG_CGROUP_SCHED=3Dy +CONFIG_CFS_BANDWIDTH=3Dy +CONFIG_CGROUP_BPF=3Dy +CONFIG_NAMESPACES=3Dy +CONFIG_USER_NS=3Dy +CONFIG_BLK_DEV_INITRD=3Dy +CONFIG_EXPERT=3Dy +CONFIG_KALLSYMS_ALL=3Dy +CONFIG_BPF_SYSCALL=3Dy +CONFIG_SOC_MICROCHIP_POLARFIRE=3Dy +CONFIG_SMP=3Dy +CONFIG_CMDLINE=3D"earlyprintk earlycon=3Dsbi debug uio_pdrv_genirq.of_id= =3Dgeneric-uio" +CONFIG_JUMP_LABEL=3Dy +CONFIG_MODULES=3Dy +CONFIG_MODULE_UNLOAD=3Dy +CONFIG_BLK_DEV_ZONED=3Dy +CONFIG_PARTITION_ADVANCED=3Dy +CONFIG_NET=3Dy +CONFIG_PACKET=3Dy +CONFIG_UNIX=3Dy +CONFIG_INET=3Dy +CONFIG_NETLINK_DIAG=3Dy +CONFIG_PCI=3Dy +CONFIG_PCI_DEBUG=3Dy +CONFIG_PCI_HOST_GENERIC=3Dy +CONFIG_PCIE_MICROCHIP_HOST=3Dy +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +CONFIG_BLK_DEV_LOOP=3Dy +CONFIG_BLK_DEV_NBD=3Dy +CONFIG_BLK_DEV_NVME=3Dy +CONFIG_BLK_DEV_SD=3Dy +CONFIG_BLK_DEV_SR=3Dy +CONFIG_ATA=3Dy +CONFIG_NETDEVICES=3Dy +CONFIG_MACB=3Dy +CONFIG_R8169=3Dy +CONFIG_INPUT_MOUSEDEV=3Dy +CONFIG_INPUT_EVDEV=3Dy +CONFIG_SERIAL_8250=3Dy +CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_OF_PLATFORM=3Dy +CONFIG_SERIAL_EARLYCON_RISCV_SBI=3Dy +CONFIG_HW_RANDOM=3Dy +CONFIG_HW_RANDOM_POLARFIRE_SOC=3Dy +CONFIG_I2C_CHARDEV=3Dy +CONFIG_I2C_MICROCHIP=3Dy +CONFIG_SPI=3Dy +CONFIG_SPI_POLARFIRE_SOC=3Dy +CONFIG_SPI_POLARFIRE_SOC_QSPI=3Dy +CONFIG_SPI_SPIDEV=3Dy +CONFIG_GPIOLIB=3Dy +CONFIG_GPIO_SYSFS=3Dy +CONFIG_GPIO_POLARFIRE_SOC=3Dy +CONFIG_POWER_RESET=3Dy +CONFIG_MEDIA_SUPPORT=3Dy +CONFIG_MEDIA_USB_SUPPORT=3Dy +CONFIG_USB_VIDEO_CLASS=3Dy +CONFIG_V4L_PLATFORM_DRIVERS=3Dy +CONFIG_DRM=3Dy +CONFIG_DRM_RADEON=3Dy +CONFIG_DRM_NOUVEAU=3Dy +CONFIG_FRAMEBUFFER_CONSOLE=3Dy +CONFIG_USB=3Dy +CONFIG_USB_XHCI_HCD=3Dy +CONFIG_USB_XHCI_PLATFORM=3Dy +CONFIG_USB_EHCI_HCD=3Dy +CONFIG_USB_EHCI_HCD_PLATFORM=3Dy +CONFIG_USB_OHCI_HCD=3Dy +CONFIG_USB_OHCI_HCD_PLATFORM=3Dy +CONFIG_USB_ACM=3Dy +CONFIG_USB_STORAGE=3Dy +CONFIG_USB_MUSB_HDRC=3Dy +CONFIG_USB_MUSB_POLARFIRE_SOC=3Dy +CONFIG_USB_INVENTRA_DMA=3Dy +CONFIG_USB_SERIAL=3Dy +CONFIG_NOP_USB_XCEIV=3Dy +CONFIG_MMC=3Dy +CONFIG_MMC_SDHCI=3Dy +CONFIG_MMC_SDHCI_PLTFM=3Dy +CONFIG_MMC_SDHCI_CADENCE=3Dy +CONFIG_MMC_SPI=3Dy +CONFIG_RTC_CLASS=3Dy +CONFIG_RTC_DRV_POLARFIRE_SOC=3Dy +CONFIG_DMADEVICES=3Dy +CONFIG_SF_PDMA=3Dy +CONFIG_UIO=3Dy +CONFIG_UIO_PDRV_GENIRQ=3Dy +CONFIG_UIO_DMEM_GENIRQ=3Dy +CONFIG_UIO_MICROCHIP_CAN=3Dy +CONFIG_UIO_MICROCHIP_PDMA=3Dy +CONFIG_UIO_MICROCHIP_DMA=3Dy +CONFIG_MAILBOX=3Dy +CONFIG_POLARFIRE_SOC_MAILBOX=3Dy +CONFIG_POLARFIRE_SOC_SYS_CTRL=3Dy +CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=3Dy +CONFIG_IIO=3Dy +CONFIG_IIO_SW_DEVICE=3Dy +CONFIG_IIO_SW_TRIGGER=3Dy +CONFIG_PAC193X=3Dy +CONFIG_PWM=3Dy +CONFIG_PWM_MICROCHIP_CORE=3Dy +CONFIG_EXT4_FS=3Dy +CONFIG_EXT4_FS_POSIX_ACL=3Dy +CONFIG_FANOTIFY=3Dy +CONFIG_MSDOS_FS=3Dy +CONFIG_VFAT_FS=3Dy +CONFIG_FAT_DEFAULT_IOCHARSET=3D"ascii" +CONFIG_EXFAT_FS=3Dy +CONFIG_TMPFS=3Dy +CONFIG_TMPFS_POSIX_ACL=3Dy +CONFIG_NFS_FS=3Dy +CONFIG_NFS_V4=3Dy +CONFIG_NFS_V4_1=3Dy +CONFIG_NFS_V4_2=3Dy +CONFIG_NLS_CODEPAGE_437=3Dy +CONFIG_NLS_CODEPAGE_850=3Dy +CONFIG_NLS_ASCII=3Dy +CONFIG_NLS_ISO8859_1=3Dy +CONFIG_NLS_UTF8=3Dy +CONFIG_PRINTK_TIME=3Dy +CONFIG_SCHED_STACK_END_CHECK=3Dy +CONFIG_SOFTLOCKUP_DETECTOR=3Dy +CONFIG_WQ_WATCHDOG=3Dy +CONFIG_SCHEDSTATS=3Dy +CONFIG_DEBUG_SPINLOCK=3Dy +CONFIG_STACKTRACE=3Dy --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3B50C433EF for ; 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charset="utf-8" From: Conor Dooley Assorted minor changes to the MPFS/Icicle kit device tree: - enable mmuart4 instead of mmuart0 - remove sifive pdma - split memory node to match updated fpga design - move stdout path to serial1 to avoid collision with bootloader running on the e51 Signed-off-by: Conor Dooley --- .../microchip/microchip-mpfs-icicle-kit.dts | 23 +++++++++++++------ .../boot/dts/microchip/microchip-mpfs.dtsi | 23 +++++++++++-------- 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index c51bd7cf500f..dc5f351b10c4 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -18,20 +18,29 @@ aliases { serial1 =3D &mmuart1; serial2 =3D &mmuart2; serial3 =3D &mmuart3; + serial4 =3D &mmuart4; }; =20 chosen { - stdout-path =3D "serial0:115200n8"; + stdout-path =3D "serial1:115200n8"; }; =20 cpus { timebase-frequency =3D ; }; =20 - memory@80000000 { + ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; - reg =3D <0x0 0x80000000 0x0 0x40000000>; + reg =3D <0x0 0x80000000 0x0 0x2e000000>; clocks =3D <&clkcfg CLK_DDRC>; + status =3D "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x0 0x0 0x40000000>; + clocks =3D <&clkcfg CLK_DDRC>; + status =3D "okay"; }; }; =20 @@ -39,10 +48,6 @@ &refclk { clock-frequency =3D <600000000>; }; =20 -&mmuart0 { - status =3D "okay"; -}; - &mmuart1 { status =3D "okay"; }; @@ -55,6 +60,10 @@ &mmuart3 { status =3D "okay"; }; =20 +&mmuart4 { + status =3D "okay"; +}; + &mmc { status =3D "okay"; =20 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 62bd00092bcc..5e7aaaf42cde 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -174,15 +174,6 @@ clint: clint@2000000 { <&cpu4_intc 3>, <&cpu4_intc 7>; }; =20 - dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; - reg =3D <0x0 0x3000000 0x0 0x8000>; - interrupt-parent =3D <&plic>; - interrupts =3D <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>; - #dma-cells =3D <1>; - }; - plic: interrupt-controller@c000000 { compatible =3D "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xc000000 0x0 0x4000000>; @@ -213,7 +204,7 @@ mmuart0: serial@20000000 { interrupts =3D <90>; current-speed =3D <115200>; clocks =3D <&clkcfg CLK_MMUART0>; - status =3D "disabled"; + status =3D "disabled"; /* Reserved for the HSS */ }; =20 mmuart1: serial@20100000 { @@ -252,6 +243,18 @@ mmuart3: serial@20104000 { status =3D "disabled"; }; =20 + mmuart4: serial@20106000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x20106000 0x0 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <94>; + clocks =3D <&clkcfg CLK_MMUART4>; + current-speed =3D <115200>; + status =3D "disabled"; + }; + /* Common node entry for emmc/sd */ mmc: mmc@20008000 { compatible =3D "microchip,mpfs-sd4hc", "cdns,sd4hc"; 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charset="utf-8" From: Conor Dooley Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by: Conor Dooley --- .../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 168 ++++++++++++++++++ 2 files changed, 221 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index dc5f351b10c4..cd2fe80fa81a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -80,6 +80,26 @@ &mmc { sd-uhs-sdr104; }; =20 +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + &i2c2 { status =3D "okay"; }; @@ -103,6 +123,39 @@ phy0: ethernet-phy@8 { }; }; =20 +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&rtc { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; + +&mbox { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + &core_pwm0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 5e7aaaf42cde..1d2447dfbf07 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -266,6 +266,66 @@ mmc: mmc@20008000 { status =3D "disabled"; }; =20 + spi0: spi@20108000 { + compatible =3D "microchip,mpfs-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x20108000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <54>; + clocks =3D <&clkcfg CLK_SPI0>; + spi-max-frequency =3D <25000000>; + status =3D "disabled"; + }; + + spi1: spi@20109000 { + compatible =3D "microchip,mpfs-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x20109000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <55>; + clocks =3D <&clkcfg CLK_SPI1>; + spi-max-frequency =3D <25000000>; + status =3D "disabled"; + }; + + qspi: spi@21000000 { + compatible =3D "microchip,mpfs-qspi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x21000000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <85>; + clocks =3D <&clkcfg CLK_QSPI>; + spi-max-frequency =3D <25000000>; + status =3D "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible =3D "microchip,mpfs-i2c"; + reg =3D <0x0 0x2010a000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&plic>; + interrupts =3D <58>; + clocks =3D <&clkcfg CLK_I2C0>; + clock-frequency =3D <100000>; + status =3D "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible =3D "microchip,mpfs-i2c"; + reg =3D <0x0 0x2010b000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&plic>; + interrupts =3D <61>; + clocks =3D <&clkcfg CLK_I2C1>; + clock-frequency =3D <100000>; + status =3D "disabled"; + }; + mac0: ethernet@20110000 { compatible =3D "cdns,macb"; reg =3D <0x0 0x20110000 0x0 0x2000>; @@ -291,5 +351,113 @@ mac1: ethernet@20112000 { clock-names =3D "pclk", "hclk"; status =3D "disabled"; }; + + gpio0: gpio@20120000 { + compatible =3D "microchip,mpfs-gpio"; + reg =3D <0x0 0x20120000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupt-controller; + #interrupt-cells =3D <1>; + clocks =3D <&clkcfg CLK_GPIO0>; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + + gpio1: gpio@20121000 { + compatible =3D "microchip,mpfs-gpio"; + reg =3D <000 0x20121000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupt-controller; + #interrupt-cells =3D <1>; + clocks =3D <&clkcfg CLK_GPIO1>; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + + gpio2: gpio@20122000 { + compatible =3D "microchip,mpfs-gpio"; + reg =3D <0x0 0x20122000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupt-controller; + #interrupt-cells =3D <1>; + clocks =3D <&clkcfg CLK_GPIO2>; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + + rtc: rtc@20124000 { + compatible =3D "microchip,mpfs-rtc"; + reg =3D <0x0 0x20124000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <80>, <81>; + clocks =3D <&clkcfg CLK_RTC>; + clock-names =3D "rtc"; + status =3D "disabled"; + }; + + usb: usb@20201000 { + compatible =3D "microchip,mpfs-musb"; + reg =3D <0x0 0x20201000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <86>, <87>; + clocks =3D <&clkcfg CLK_USB>; + interrupt-names =3D "dma","mc"; + status =3D "disabled"; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + microchip,axi-m-atr0 =3D <0x10 0x0>; + status =3D "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + mbox: mailbox@37020000 { + compatible =3D "microchip,mpfs-mailbox"; + reg =3D <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent =3D <&plic>; + interrupts =3D <96>; + #mbox-cells =3D <1>; + status =3D "disabled"; + }; + + syscontroller: syscontroller { + compatible =3D "microchip,mpfs-sys-controller"; + mboxes =3D <&mbox 0>; + =09 + rng: rng { + compatible =3D "microchip,mpfs-rng"; + }; + + sysserv: sysserv { + compatible =3D "microchip,mpfs-generic-service"; + }; + }; }; }; --=20 2.32.0 From nobody Tue Jun 30 13:56:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F9F3C433EF for ; Fri, 14 Jan 2022 15:18:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243039AbiANPSh (ORCPT ); Fri, 14 Jan 2022 10:18:37 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:50786 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242435AbiANPSR (ORCPT ); Fri, 14 Jan 2022 10:18:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642173497; x=1673709497; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Fri, 14 Jan 2022 08:18:13 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 14 Jan 2022 08:18:07 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 15/15] MAINTAINERS: update riscv/microchip entry Date: Fri, 14 Jan 2022 15:17:27 +0000 Message-ID: <20220114151727.2319915-16-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220114151727.2319915-1-conor.dooley@microchip.com> References: <20220114151727.2319915-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Update the RISC-V/Microchip entry by adding the microchip dts directory and myself as maintainer Reviewed-by: Lewis Hanly Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce8521..3b1d6be7bd56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16348,8 +16348,10 @@ K: riscv =20 RISC-V/MICROCHIP POLARFIRE SOC SUPPORT M: Lewis Hanly +M: Conor Dooley L: linux-riscv@lists.infradead.org S: Supported +F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h --=20 2.32.0