From nobody Tue Jun 30 15:32:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF36C433F5 for ; Fri, 14 Jan 2022 00:43:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238516AbiANAns (ORCPT ); Thu, 13 Jan 2022 19:43:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238482AbiANAno (ORCPT ); Thu, 13 Jan 2022 19:43:44 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D6A4C061748 for ; Thu, 13 Jan 2022 16:43:44 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id rj2-20020a17090b3e8200b001b1944bad25so12621556pjb.5 for ; Thu, 13 Jan 2022 16:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2LT+Vm4rzQkk47lugUpAeU8Aw0wC+LkjKsmIBgeDejg=; b=M52J4hq6RxIIbN21Vg65/n9UCDqSBjaQ4fbrXsn+GQPgCvQX5VTMUNl7+jfFgUnm/X y4458WxGx4CXxklfB7lepyCwO85RmpbtNNQZ9LCjF/IHoKKqTk5DH0JdE4U/9J2jnx3I +AzTvjl4VxEKiyGG2L4FMLUp1RD4AUabeML2Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2LT+Vm4rzQkk47lugUpAeU8Aw0wC+LkjKsmIBgeDejg=; b=Spniu263DlPAeyMVo+AyKnvq44ZN9GLykYWC3Fv7GX63Uidx+qhJk+NiJM1xPaoJsB d0tr3OKtPyeWmddvp7MJquX0KdfozxXRF54cZqvb92AGmVRJCuwk04e4oAMpx1/KQdqk P/rNCmOy3QBW9qiPxu89RjH0xRqq9suzpKoCdDewENW5KLwQebUiKqw3LhViCokl/jVU sDGAmqm+RttaSUXYqQfTzF49Hm92wXdcWIyj9neMhmCx1xQ3+zlML5wynpWRPdN0HZEe yTBKy7bg18+3AyUIOsrEI2toQXdwdwz2UtAUTj8auNXsYtEGB+ApS3IHs46+SK86PS96 2Msg== X-Gm-Message-State: AOAM533Jv1saAG+dBeO5VFmoAjyHJ/0kCp4ckjMGFVw85Gwn+YS8Un8M eiZzeBNWSmZYeZJsrYUyz4VmOA== X-Google-Smtp-Source: ABdhPJxgxNnaoZZRzk4weku2Sp6EHxGfy7/c7stTjDEkbQ9+wP4d2oL6pe1uoG7zyeZRZaFCNnuLPA== X-Received: by 2002:a17:902:d3c1:b0:14a:8d01:9d30 with SMTP id w1-20020a170902d3c100b0014a8d019d30mr1979443plb.56.1642121023532; Thu, 13 Jan 2022 16:43:43 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:201:cf6e:9fa9:a398:4c9]) by smtp.gmail.com with ESMTPSA id j4sm4061498pfj.217.2022.01.13.16.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jan 2022 16:43:43 -0800 (PST) From: Douglas Anderson To: Bjorn Andersson Cc: quic_rjendra@quicinc.com, sibis@codeaurora.org, kgodara1@codeaurora.org, mka@chromium.org, swboyd@chromium.org, pmaliset@codeaurora.org, Douglas Anderson , Akhil P Oommen , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] arm64: dts: qcom: sc7280: Fix gmu unit address Date: Thu, 13 Jan 2022 16:43:00 -0800 Message-Id: <20220113164233.1.I19f60014e9be4b9dda4d66b5d56ef3d9600b6e10@changeid> X-Mailer: git-send-email 2.34.1.703.g22d0c6ccf7-goog In-Reply-To: <20220114004303.905808-1-dianders@chromium.org> References: <20220114004303.905808-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When processing sc7280 device trees, I can see: Warning (simple_bus_reg): /soc@0/gmu@3d69000: simple-bus unit address format error, expected "3d6a000" There's a clear typo in the node name. Fix it. Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 937c2e0e93eb..eab7a8505053 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1790,7 +1790,7 @@ opp-550000000 { }; }; =20 - gmu: gmu@3d69000 { + gmu: gmu@3d6a000 { compatible=3D"qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; reg =3D <0 0x03d6a000 0 0x34000>, <0 0x3de0000 0 0x10000>, --=20 2.34.1.703.g22d0c6ccf7-goog From nobody Tue Jun 30 15:32:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0950C433EF for ; Fri, 14 Jan 2022 00:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238517AbiANAnu (ORCPT ); Thu, 13 Jan 2022 19:43:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238494AbiANAnp (ORCPT ); Thu, 13 Jan 2022 19:43:45 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 434EDC061574 for ; Thu, 13 Jan 2022 16:43:45 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id u11so6714551plh.13 for ; Thu, 13 Jan 2022 16:43:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oOZFo592UdILGLoDGp89AJsD2A4mJA4MyK/MjP77tbM=; b=KVtjLHwGb6AIYwNB2flGInGHH25R4C1NvHcO4uZ8yoKCbfn0+Msq843IYhj7uZq/vQ MwTR1deqYLnUiV+tPYUT1SxADF8NuBmWTgYjcbJMzW/oveN6bXrJOkXYrAHDOj4IS/6W iTvkVbjk872M6Df84PDyn0W4FMA5Cc0Gik5sE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oOZFo592UdILGLoDGp89AJsD2A4mJA4MyK/MjP77tbM=; b=YuLvxr9snQVxVEDRjjNddxbbilf3Ja4IiJwBz/m8cb+pNlFYgGo2MlpjGFv7c0kbe+ cbtE2/mlcYtHx5iMRePluVEQbpB/XZXnkzD3RRTYQMspjG0fBhM3vUeWL7Ga4r3tdHxi nZSSd+/oVzuW536Rr6QbfnLmXcqKoWVmtsFH5r42EM5QyLSr+4a5JchseM/QH7x/SAgZ 3r9NPEvbTvxXeNO72sI6jcepK/0xjVLota7F6wDRJq1mgfq4wMWjHnLDnxOYFuU9yMWy QSruex/ewbCgiwfm5SvcZ8K4IdTX/S1I3fNt1UVMbZFMgReSri02tPnKCgwCmy070Vp2 v7lQ== X-Gm-Message-State: AOAM530XGEDY+8RUVvTdTb7Xx8nTjpUEBOMM/kLpLm1uiRi7qS9EGMRA j758igj9X5ZoL2zLhcswhndOBQ== X-Google-Smtp-Source: ABdhPJwDuaMnySixe3jTI1iHzgs7G0LVCvvJSBOHLiQ/cTDNRUNlQr2UlYRo6HR3kTGONiNN+mBqXQ== X-Received: by 2002:a17:903:41c4:b0:14a:4baa:4261 with SMTP id u4-20020a17090341c400b0014a4baa4261mr7058413ple.174.1642121024840; Thu, 13 Jan 2022 16:43:44 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:201:cf6e:9fa9:a398:4c9]) by smtp.gmail.com with ESMTPSA id j4sm4061498pfj.217.2022.01.13.16.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jan 2022 16:43:44 -0800 (PST) From: Douglas Anderson To: Bjorn Andersson Cc: quic_rjendra@quicinc.com, sibis@codeaurora.org, kgodara1@codeaurora.org, mka@chromium.org, swboyd@chromium.org, pmaliset@codeaurora.org, Douglas Anderson , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: qcom: sc7280: Move herobrine-r0 to its own dts Date: Thu, 13 Jan 2022 16:43:01 -0800 Message-Id: <20220113164233.2.Id9716db8c133bcb14c9413144048f8d00ae2674f@changeid> X-Mailer: git-send-email 2.34.1.703.g22d0c6ccf7-goog In-Reply-To: <20220114004303.905808-1-dianders@chromium.org> References: <20220114004303.905808-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The upcoming herobrine-r1 board is really not very similar to herobrine-r0. Let's get rid of the "herobrine.dtsi" file and stick all the content in the -r0 dts file directly. We'll also rename the dts so it's obvious that it's just for -r0. While renaming, let's actually name the file so it's obvious that "herobrine" is both the name of the board and the name of the "baseboard". In other words "herobrine" is an actual board but also often used as the name of a whole class of similar boards that forked from a design. While "herobrine-herobrine" is a bit of mouthful it makes it more obvious which things are part of an actual board rather than the baseboard. NOTE: herobrine-rev0's days are likely doomed and this device tree is likely to be deleted in the future. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/Makefile | 2 +- ...rine.dtsi =3D> sc7280-herobrine-herobrine-r0.dts} | 6 ++++++ arch/arm64/boot/dts/qcom/sc7280-herobrine.dts | 14 -------------- 3 files changed, 7 insertions(+), 15 deletions(-) rename arch/arm64/boot/dts/qcom/{sc7280-herobrine.dtsi =3D> sc7280-herobri= ne-herobrine-r0.dts} (99%) delete mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f7232052d286..9db743826391 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -82,7 +82,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine-herobrine-r0.dts similarity index 99% rename from arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi rename to arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 4619fa9fcacd..8676c93590b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -22,6 +22,12 @@ #include "pm8350c.dtsi" #include "pmk8350.dtsi" =20 +/ { + model =3D "Google Herobrine (rev0)"; + compatible =3D "google,herobrine", + "qcom,sc7280"; +}; + /* * Reserved memory changes * diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts b/arch/arm64/boo= t/dts/qcom/sc7280-herobrine.dts deleted file mode 100644 index 7a92679a688b..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Herobrine board device tree source - * - * Copyright 2021 Google LLC. - */ - -#include "sc7280-herobrine.dtsi" - -/ { - model =3D "Google Herobrine"; - compatible =3D "google,herobrine", - "qcom,sc7280"; -}; --=20 2.34.1.703.g22d0c6ccf7-goog From nobody Tue Jun 30 15:32:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10474C433F5 for ; Fri, 14 Jan 2022 00:43:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238544AbiANAnx (ORCPT ); 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Thu, 13 Jan 2022 16:43:45 -0800 (PST) From: Douglas Anderson To: Bjorn Andersson Cc: quic_rjendra@quicinc.com, sibis@codeaurora.org, kgodara1@codeaurora.org, mka@chromium.org, swboyd@chromium.org, pmaliset@codeaurora.org, Douglas Anderson , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: qcom: sc7280: Factor out Chrome common fragment Date: Thu, 13 Jan 2022 16:43:02 -0800 Message-Id: <20220113164233.3.Iac012fa8d727be46448d47027a1813ea716423ce@changeid> X-Mailer: git-send-email 2.34.1.703.g22d0c6ccf7-goog In-Reply-To: <20220114004303.905808-1-dianders@chromium.org> References: <20220114004303.905808-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This factors out a device tree fragment from some sc7280 device trees. It represents the device tree bits that should be included for "Chrome" based sc7280 boards. On these boards the bootloader (Coreboot + Depthcharge) configures things slightly different than the bootloader that Qualcomm provides. The modem firmware on these boards also works differently than on other Qulacomm products and thus the reserved memory map needs to be adjusted. NOTES: - This is _not_ quite a no-op change. The "herobrine" and "idp" fragments here were different and it looks like someone simply forgot to update the herobrine version. This updates a few numbers to match IDP. This will also cause the `pmk8350_pon` to be disabled on idp/crd, which I belive is a correct change. - At the moment this assumes LTE skus. Once it's clearer how WiFi SKUs will work (how much of the memory map they can reclaim) we may add an extra fragment that will rejigger one way or the other. Signed-off-by: Douglas Anderson --- .../boot/dts/qcom/sc7280-chrome-common.dtsi | 97 +++++++++++++++++++ .../qcom/sc7280-herobrine-herobrine-r0.dts | 70 +------------ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 75 +------------- 3 files changed, 101 insertions(+), 141 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sc7280-chrome-common.dtsi new file mode 100644 index 000000000000..9d4f25f77152 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 fragment for devices with Chrome bootloader + * + * This file mainly tries to abstract out the memory protections put into + * place by the Chrome bootloader which are different than what's put into + * place by Qualcomm's typical bootloader. It also has a smattering of oth= er + * things that will hold true for any conceivable Chrome design + * + * Copyright 2022 Google LLC. + */ + +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the setup for Chrome boards. + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &reserved_xbl_uefi_log; +/delete-node/ &sec_apps_mem; + +/ { + reserved-memory { + adsp_mem: memory@86700000 { + reg =3D <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + camera_mem: memory@8ad00000 { + reg =3D <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8b200000 { + reg =3D <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8b800000 { + reg =3D <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: memory@9ae00000 { + reg =3D <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg =3D <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; +}; + +/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things.= */ +&pmk8350_pon { + status =3D "disabled"; +}; + +/* + * Chrome designs always boot from SPI flash hooked up to the qspi. + * + * It's expected that all boards will support "dual SPI" at 37.5 MHz. + * If some boards need a different speed or have a package that allows + * Quad SPI together with WP then those boards can easily override. + */ +&qspi { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + + spi_flash: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + + spi-max-frequency =3D <37500000>; + spi-tx-bus-width =3D <2>; + spi-rx-bus-width =3D <2>; + }; +}; + +/* Modem setup is different on Chrome setups than typical Qualcomm setup */ +&remoteproc_mpss { + status =3D "okay"; + compatible =3D "qcom,sc7280-mss-pil"; + iommus =3D <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + memory-region =3D <&mba_mem &mpss_mem>; +}; + +/* Increase the size from 2.5MB to 8MB */ +&rmtfs_mem { + reg =3D <0x0 0x9c900000 0x0 0x800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 8676c93590b5..67680a13c234 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -22,62 +22,15 @@ #include "pm8350c.dtsi" #include "pmk8350.dtsi" =20 +#include "sc7280-chrome-common.dtsi" + / { model =3D "Google Herobrine (rev0)"; compatible =3D "google,herobrine", "qcom,sc7280"; }; =20 -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg =3D <0x0 0x83600000 0x0 0x800000>; -}; - / { - reserved-memory { - adsp_mem: memory@86700000 { - reg =3D <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg =3D <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg =3D <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg =3D <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg =3D <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg =3D <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; - aliases { serial0 =3D &uart5; serial1 =3D &uart7; @@ -691,10 +644,6 @@ &pmk8350_gpios { status =3D "disabled"; /* No GPIOs are connected */ }; =20 -&pmk8350_pon { - status =3D "disabled"; -}; - &pmk8350_rtc { status =3D "disabled"; }; @@ -717,21 +666,6 @@ &qfprom { vcc-supply =3D <&vdd_qfprom>; }; =20 -&qspi { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - - spi-max-frequency =3D <37500000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - }; -}; - &qupv3_id_0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index d623d71d8bd4..98c8f39ce459 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -13,6 +13,8 @@ #include "pm8350c.dtsi" #include "pmk8350.dtsi" =20 +#include "sc7280-chrome-common.dtsi" + / { gpio-keys { compatible =3D "gpio-keys"; @@ -45,58 +47,6 @@ nvme_3v3_regulator: nvme-3v3-regulator { }; }; =20 -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &reserved_xbl_uefi_log; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2.5MB to 8MB */ -&rmtfs_mem { - reg =3D <0x0 0x9c900000 0x0 0x800000>; -}; - -/ { - reserved-memory { - adsp_mem: memory@86700000 { - reg =3D <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg =3D <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg =3D <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg =3D <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg =3D <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg =3D <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; -}; - &apps_rsc { pm7325-regulators { compatible =3D "qcom,pm7325-rpmh-regulators"; @@ -313,20 +263,6 @@ &qfprom { vcc-supply =3D <&vreg_l1c_1p8>; }; =20 -&qspi { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - spi-max-frequency =3D <37500000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - }; -}; - &qupv3_id_0 { status =3D "okay"; }; @@ -335,13 +271,6 @@ &qupv3_id_1 { status =3D "okay"; }; =20 -&remoteproc_mpss { - status =3D "okay"; - compatible =3D "qcom,sc7280-mss-pil"; - iommus =3D <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; - memory-region =3D <&mba_mem &mpss_mem>; -}; - &sdhc_1 { status =3D "okay"; =20 --=20 2.34.1.703.g22d0c6ccf7-goog From nobody Tue Jun 30 15:32:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 928BEC433EF for ; Fri, 14 Jan 2022 00:43:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238559AbiANAny (ORCPT ); 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Thu, 13 Jan 2022 16:43:47 -0800 (PST) From: Douglas Anderson To: Bjorn Andersson Cc: quic_rjendra@quicinc.com, sibis@codeaurora.org, kgodara1@codeaurora.org, mka@chromium.org, swboyd@chromium.org, pmaliset@codeaurora.org, Douglas Anderson , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: qcom: sc7280: Add herobrine-r1 Date: Thu, 13 Jan 2022 16:43:03 -0800 Message-Id: <20220113164233.4.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid> X-Mailer: git-send-email 2.34.1.703.g22d0c6ccf7-goog In-Reply-To: <20220114004303.905808-1-dianders@chromium.org> References: <20220114004303.905808-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the new herobrine-r1. Note that this is pretty much a re-design compared to herobrine-r0 so we don't attempt any dtsi to share stuff between them. This patch attempts to define things at 3 levels: 1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB is supposed to be the same (modulo stuffing options) across multiple boards, so trying to define what's there hopefully makes sense. NOTE that newer "CRD" boards from Qualcomm also use Qcard. When support for CRD3 is added hopefully it can use the Qcard include (and perhaps we should even evaluate it using herobrine.dtsi?) 2. The herobrine "baseboard" level. Right now most stuff is here with the exception of things that we _know_ will be different per board. We know that not all boards will have the same set of eMMC, nvme, and SD. We also know that the exact pin names are likely to be different. 3. The actual "board" level, AKA herobrine-rev1. NOTES: - This boots to command prompt, but no eDP yet since eDP hasn't been added to sc7280.dtsi yet. - This assumes LTE for now. Once it's clear how WiFi-only SKUs will work we expect some small changes. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sc7280-herobrine-herobrine-r0.dts | 2 +- .../qcom/sc7280-herobrine-herobrine-r1.dts | 314 +++++++ .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 781 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 557 +++++++++++++ 5 files changed, 1654 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.= dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 9db743826391..54998e108092 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3-lte= .dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-herobrine-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 67680a13c234..dcd10d0ead1e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -26,7 +26,7 @@ =20 / { model =3D "Google Herobrine (rev0)"; - compatible =3D "google,herobrine", + compatible =3D "google,herobrine-rev0", "qcom,sc7280"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts new file mode 100644 index 000000000000..c57bd689df23 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model =3D "Google Herobrine (rev1+)"; + compatible =3D "google,herobrine", + "qcom,sc7280"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&ap_spi_fp { + status =3D "okay"; +}; + +/* + * Although the trackpad is really part of the herobrine baseboard, we'll + * put the actual definition in the board device tree since different boar= ds + * might hook up different trackpads (or no i2c trackpad at all in the case + * of tablets / detachables). + */ +ap_tp_i2c: &i2c0 { + status =3D "okay"; + clock-frequency =3D <400000>; + + trackpad: trackpad@15 { + compatible =3D "elan,ekth3000"; + reg =3D <0x15>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tp_int_odl>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <7 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply =3D <&pp3300_z1>; + + wakeup-source; + }; +}; + +/* + * The touchscreen connector might come off the Qcard, at least in the cas= e of + * eDP. Like the trackpad, we'll put it in the board device tree file since + * different boards have different touchscreens. + */ +ts_i2c: &i2c13 { + status =3D "okay"; + clock-frequency =3D <400000>; + + ap_ts: touchscreen@5c { + compatible =3D "hid-over-i2c"; + reg =3D <0x5c>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms =3D <500>; + hid-descr-addr =3D <0x0000>; + + vdd-supply =3D <&ts_avdd>; + }; +}; + +/* For nvme */ +&pcie1 { + status =3D "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status =3D "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status =3D "okay"; +}; + +/* For SD Card */ +&sdhc_2 { + status =3D "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names =3D "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names =3D "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi new file mode 100644 index 000000000000..157da25cc5a8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine baseboard device tree source + * + * The set of things in this file is a bit loosely defined. It's roughly + * defined as the set of things that the child boards happen to have in + * common. Since all of the child boards started from the same original + * design this is hopefully a large set of things but as more derivatives + * appear things may "bubble down" out of this file. For things that are + * part of the reference design but might not exist on child nodes we will + * follow the lead of the SoC dtsi files and leave their status as "disabl= ed". + * + * Copyright 2022 Google LLC. + */ + +#include +#include +#include + +#include "sc7280-qcard.dtsi" +#include "sc7280-chrome-common.dtsi" + +/ { + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + /* + * FIXED REGULATORS + * + * Sort order: + * 1. parents above children. + * 2. higher voltage above lower voltage. + * 3. alphabetically by node name. + */ + + /* This is the top level supply and variable voltage */ + ppvar_sys: ppvar-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + /* This divides ppvar_sys by 2, so voltage is variable */ + src_vph_pwr: src-vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "src_vph_pwr"; + + /* EC turns on with switchcap_on; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&ppvar_sys>; + }; + + pp5000_s5: pp5000-s5-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp5000_s5"; + + /* EC turns on with en_pp5000_s5; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + vin-supply =3D <&ppvar_sys>; + }; + + pp3300_z1: pp3300-z1-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_z1"; + + /* EC turns on with en_pp3300_z1; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + vin-supply =3D <&ppvar_sys>; + }; + + pp3300_codec: pp3300-codec-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_codec"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 105 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_pp3300_codec>; + + vin-supply =3D <&pp3300_z1>; + }; + + pp3300_left_in_mlb: pp3300-left-in-mlb { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_left_in_mlb"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_pp3300_dx_edp>; + + vin-supply =3D <&pp3300_z1>; + }; + + pp3300_mcu_fp: + pp3300_fp_ls: + pp3300_fp_mcu: pp3300-fp-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_fp"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 77 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_fp_rails>; + + vin-supply =3D <&pp3300_z1>; + }; + + pp3300_hub: pp3300-hub-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_hub"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-boot-on; + regulator-always-on; + + gpio =3D <&tlmm 157 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hub_en>; + + vin-supply =3D <&pp3300_z1>; + }; + + pp3300_tp: pp3300-tp-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_tp"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + /* AP turns on with PP1800_L18B_S0; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&pp3300_z1>; + }; + + pp3300_ssd: pp3300-ssd { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_ssd"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ssd_en>; + + vin-supply =3D <&pp3300_z1>; + }; + + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp2850_vcm_wf_cam"; + + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + + gpio =3D <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wf_cam_en>; + + vin-supply =3D <&pp3300_z1>; + }; + + pp2850_wf_cam: pp2850-wf-cam { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp2850_wf_cam"; + + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + + gpio =3D <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names =3D "default"; + * pinctrl-0 =3D <&wf_cam_en>; + */ + + vin-supply =3D <&pp3300_z1>; + }; + + pp1800_fp: pp1800-fp-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_fp"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 77 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_fp_rails>; + + vin-supply =3D <&pp1800_l18b_s0>; + status =3D "disabled"; + }; + + pp1800_wf_cam: pp1800-wf-cam { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_wf_cam"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names =3D "default"; + * pinctrl-0 =3D <&wf_cam_en>; + */ + + vin-supply =3D <&vreg_l19b_s0>; + }; + + pp1200_wf_cam: pp1200-wf-cam { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1200_wf_cam"; + + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + gpio =3D <&tlmm 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names =3D "default"; + * pinctrl-0 =3D <&wf_cam_en>; + */ + + vin-supply =3D <&pp3300_z1>; + }; + + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + pwmleds { + compatible =3D "pwm-leds"; + status =3D "disabled"; + keyboard_backlight: keyboard-backlight { + status =3D "disabled"; + label =3D "cros_ec::kbd_backlight"; + pwms =3D <&cros_ec_pwm 0>; + max-brightness =3D <1023>; + }; + }; +}; + +/* + * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD + * + * Names are only listed here if regulators go somewhere other than a + * testpoint. + */ + +/* From Qcard to our board; ordered by PMIC-ID / rail number */ + +pp1256_s8b: &vreg_s8b_1p256 {}; + +pp1800_l18b_s0: &vreg_l18b_1p8 {}; +pp1800_l18b: &vreg_l18b_1p8 {}; + +vreg_l19b_s0: &vreg_l19b_1p8 {}; + +pp1800_alc5682: &vreg_l2c_1p8 {}; +pp1800_l2c: &vreg_l2c_1p8 {}; + +vreg_l4c: &vreg_l4c_1p8_3p0 {}; + +ppvar_l6c: &vreg_l6c_2p96 {}; + +pp3000_l7c: &vreg_l7c_3p0 {}; + +pp1800_prox: &vreg_l8c_1p8 {}; +pp1800_l8c: &vreg_l8c_1p8 {}; + +pp2950_l9c: &vreg_l9c_2p96 {}; + +pp1800_lcm: &vreg_l12c_1p8 {}; +pp1800_mipi: &vreg_l12c_1p8 {}; +pp1800_l12c: &vreg_l12c_1p8 {}; + +pp3300_lcm: &vreg_l13c_3p0 {}; +pp3300_mipi: &vreg_l13c_3p0 {}; +pp3300_l13c: &vreg_l13c_3p0 {}; + +/* From our board to Qcard; ordered same as node definition above */ + +vreg_edp_bl: &ppvar_sys {}; + +ts_avdd: &pp3300_left_in_mlb {}; +vreg_edp_3p3: &pp3300_left_in_mlb {}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +ap_i2c_tpm: &i2c14 { + status =3D "okay"; + clock-frequency =3D <400000>; + + tpm@50 { + compatible =3D "google,cr50"; + reg =3D <0x50>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gsc_ap_int_odl>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <104 IRQ_TYPE_EDGE_RISING>; + }; +}; + +/* For nvme; not all herobrine boards have; boards set status =3D "okay" */ +&pcie1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; + + perst-gpio =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply =3D <&pp3300_ssd>; +}; + +&pmk8350_rtc { + status =3D "disabled"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +/* For SD Card; not all herobrine boards have; boards set status =3D "okay= " */ +&sdhc_2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc2_on>; + pinctrl-1 =3D <&sdc2_off>; + + vmmc-supply =3D <&pp2950_l9c>; + vqmmc-supply =3D <&ppvar_l6c>; + + cd-gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + +/* Not all herobrine boards have fingerprint; boards set status =3D "okay"= */ +ap_spi_fp: &spi9 { + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_= spi9_cs_gpio>; + + cs-gpios =3D <&tlmm 39 GPIO_ACTIVE_LOW>; + + cros_ec_fp: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupt-parent =3D <&tlmm>; + interrupts =3D <61 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>; + spi-max-frequency =3D <3000000>; + }; +}; + +ap_ec_spi: &spi10 { + status =3D "okay"; + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qu= p_spi10_cs_gpio>; + + cs-gpios =3D <&tlmm 43 GPIO_ACTIVE_LOW>; + + cros_ec: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupt-parent =3D <&tlmm>; + interrupts =3D <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ap_ec_int_l>; + spi-max-frequency =3D <3000000>; + + cros_ec_pwm: ec-pwm { + compatible =3D "google,cros-ec-pwm"; + #pwm-cells =3D <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible =3D "google,cros-ec-i2c-tunnel"; + google,remote-bus =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + typec { + compatible =3D "google,cros-ec-typec"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_c0: connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + label =3D "left"; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + }; + + usb_c1: connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + label =3D "right"; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + }; + }; + }; +}; + +#include +#include + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + status =3D "okay"; +}; + +&usb_1_qmpphy { + status =3D "okay"; +}; + +&usb_2 { + status =3D "okay"; +}; + +&usb_2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_2_hsphy { + status =3D "okay"; +}; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&qspi_cs0 { + drive-strength =3D <8>; + bias-disable; +}; + +&qspi_clk { + drive-strength =3D <8>; + bias-disable; +}; + +&qspi_data01 { + drive-strength =3D <8>; + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; +}; + +/* For ap_tp_i2c */ +&qup_i2c0_data_clk { + drive-strength =3D <2>; + /* Has external pull */ + bias-disable; +}; + +/* For ap_i2c_tpm */ +&qup_i2c14_data_clk { + drive-strength =3D <2>; + /* Has external pull */ + bias-disable; +}; + +/* For ap_spi_fp */ +&qup_spi9_data_clk { + drive-strength =3D <2>; + bias-disable; +}; + +/* For ap_spi_fp */ +&qup_spi9_cs_gpio { + drive-strength =3D <2>; + bias-disable; +}; + +/* For ap_ec_spi */ +&qup_spi10_data_clk { + drive-strength =3D <2>; + bias-disable; +}; + +/* For ap_ec_spi */ +&qup_spi10_cs_gpio { + drive-strength =3D <2>; + bias-disable; +}; + +/* For uart_dbg */ +&qup_uart5_rx { + bias-pull-up; +}; + +/* For uart_dbg */ +&qup_uart5_tx { + drive-strength =3D <2>; + bias-disable; +}; + +&sdc2_on { + clk { + bias-disable; + drive-strength =3D <16>; + }; + + cmd { + bias-pull-up; + drive-strength =3D <10>; + }; + + data { + bias-pull-up; + drive-strength =3D <10>; + }; + + sd-cd { + pins =3D "gpio91"; + bias-pull-up; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&pm7325_gpios { + /* + * On a quick glance it might look like KYPD_VOL_UP_N is used, but + * that only passes through to a debug connector and not to the actual + * volume up key. + */ + status =3D "disabled"; /* No GPIOs are connected */ +}; + +&pmk8350_gpios { + status =3D "disabled"; /* No GPIOs are connected */ +}; + +&tlmm { + /* + * pinctrl settings for pins that have no real owners. + */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bios_flash_wp_od>; + + amp_en: amp-en { + pins =3D "gpio63"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + ap_ec_int_l: ap-ec-int-l { + pins =3D "gpio18"; + function =3D "gpio"; + bias-pull-up; + }; + + bios_flash_wp_od: bios-flash-wp-od { + pins =3D "gpio16"; + function =3D "gpio"; + /* Has external pull */ + bias-disable; + }; + + en_fp_rails: en-fp-rails { + pins =3D "gpio77"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + en_pp3300_codec: en-pp3300-codec { + pins =3D "gpio105"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + en_pp3300_dx_edp: en-pp3300-dx-edp { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + hub_en: hub-en { + pins =3D "gpio157"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + fp_rst_l: fp-rst-l { + pins =3D "gpio78"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + fp_to_ap_irq_l: fp-to-ap-irq-l { + pins =3D "gpio61"; + function =3D "gpio"; + /* Has external pullup */ + bias-disable; + }; + + fpmcu_boot0: fpmcu-boot0 { + pins =3D "gpio68"; + function =3D "gpio"; + bias-disable; + output-low; + }; + + gsc_ap_int_odl: gsc-ap-int-odl { + pins =3D "gpio104"; + function =3D "gpio"; + bias-pull-up; + }; + + hp_irq: hp-irq { + pins =3D "gpio101"; + function =3D "gpio"; + bias-pull-up; + }; + + pe_wake_odl: pe-wake-odl { + pins =3D "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + /* Has external pull */ + bias-disable; + }; + + /* For ap_spi_fp */ + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high { + pins =3D "gpio39"; + function =3D "gpio"; + output-high; + }; + + /* For ap_ec_spi */ + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + pins =3D "gpio43"; + function =3D "gpio"; + output-high; + }; + + sar0_irq_odl: sar0-irq-odl { + pins =3D "gpio141"; + function =3D "gpio"; + bias-pull-up; + }; + + sar1_irq_odl: sar0-irq-odl { + pins =3D "gpio140"; + function =3D "gpio"; + bias-pull-up; + }; + + ssd_en: ssd-en { + pins =3D "gpio51"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + ssd_rst_l: ssd-rst-l { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + tp_int_odl: tp-int-odl { + pins =3D "gpio7"; + function =3D "gpio"; + /* Has external pullup */ + bias-disable; + }; + + wf_cam_en: wf-cam-en { + pins =3D "gpio119"; + function =3D "gpio"; + drive-strength =3D <2>; + /* Has external pulldown */ + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/d= ts/qcom/sc7280-qcard.dtsi new file mode 100644 index 000000000000..caff21d1e588 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 Qcard device tree source + * + * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector = (if + * stuffed) on it. This device tree tries to encapsulate all the things th= at + * all boards using Qcard will have in common. Given that there are stuffi= ng + * options, some things may be left with status "disabled" and enabled in + * the actual board device tree files. + * + * Copyright 2022 Google LLC. + */ + +#include +#include +#include +#include + +#include "sc7280.dtsi" + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/ { + aliases { + bluetooth0 =3D &bluetooth; + serial0 =3D &uart5; + serial1 =3D &uart7; + }; +}; + +&apps_rsc { + /* + * Regulators are given labels corresponding to the various names + * they are referred to on schematics. They are also given labels + * corresponding to named voltage inputs on the SoC or components + * bundled with the SoC (like radio companion chips). We totally + * ignore it when one regulator is the input to another regulator. + * That's handled automatically by the initial config given to + * RPMH by the firmware. + * + * Regulators that the HLOS (High Level OS) doesn't touch at all + * are left out of here since they are managed elsewhere. + */ + + pm7325-regulators { + compatible =3D "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd19_pmu_pcie_i: + vdd19_pmu_rfa_i: + vreg_s1b_1p856: smps1 { + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2040000>; + }; + + vdd_pmu_aon_i: + vdd09_pmu_rfa_i: + vdd095_mx_pmu: + vdd095_pmu: + vreg_s7b_0p952: smps7 { + regulator-min-microvolt =3D <535000>; + regulator-max-microvolt =3D <1120000>; + }; + + vdd13_pmu_rfa_i: + vdd13_pmu_pcie_i: + vreg_s8b_1p256: smps8 { + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1500000>; + }; + + vdd_a_usbssdp_0_core: + vreg_l1b_0p912: ldo1 { + regulator-min-microvolt =3D <825000>; + regulator-max-microvolt =3D <925000>; + regulator-initial-mode =3D ; + }; + + vdd_a_usbhs_3p1: + vreg_l2b_3p072: ldo2 { + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vdd_a_csi_0_1_1p2: + vdd_a_csi_2_3_1p2: + vdd_a_csi_4_1p2: + vdd_a_dsi_0_1p2: + vdd_a_edp_0_1p2: + vdd_a_qlink_0_1p2: + vdd_a_qlink_1_1p2: + vdd_a_pcie_0_1p2: + vdd_a_pcie_1_1p2: + vdd_a_ufs_0_1p2: + vdd_a_usbssdp_0_1p2: + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + /* + * Despite the fact that this is named to be 2.5V on the + * schematic, it powers eMMC which doesn't accept 2.5V + */ + vreg_l7b_2p5: ldo7 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vdd_px_wcd9385: + vdd_txrx: + vddpx_0: + vddpx_3: + vddpx_7: + vreg_l18b_1p8: ldo18 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vdd_1p8: + vdd_px_sdr735: + vdd_pxm: + vdd18_io: + vddio_px_1: + vddio_px_2: + vddio_px_3: + vddpx_ts: + vddpx_wl4otp: + vreg_l19b_1p8: ldo19 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + pm8350c-regulators { + compatible =3D "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd22_wlbtpa_ch0: + vdd22_wlbtpa_ch1: + vdd22_wlbtppa_ch0: + vdd22_wlbtppa_ch1: + vdd22_wlpa5g_ch0: + vdd22_wlpa5g_ch1: + vdd22_wlppa5g_ch0: + vdd22_wlppa5g_ch1: + vreg_s1c_2p2: smps1 { + regulator-min-microvolt =3D <2190000>; + regulator-max-microvolt =3D <2210000>; + }; + + lp4_vdd2_1p052: + vreg_s9c_0p676: smps9 { + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1170000>; + }; + + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_turing_q6_cs_1p8: + vdd_a_cxo_1p8: + vdd_a_qrefs_1p8: + vdd_a_usbhs_1p8: + vdd_qfprom: + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3540000>; + regulator-initial-mode =3D ; + }; + + vddpx_5: + vreg_l4c_1p8_3p0: ldo4 { + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vddpx_6: + vreg_l5c_1p8_3p0: ldo5 { + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vddpx_2: + vreg_l6c_2p96: ldo6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + regulator-initial-mode =3D ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vdd_a_csi_0_1_0p9: + vdd_a_csi_2_3_0p9: + vdd_a_csi_4_0p9: + vdd_a_dsi_0_0p9: + vdd_a_dsi_0_pll_0p9: + vdd_a_edp_0_0p9: + vdd_a_gnss_0p9: + vdd_a_pcie_0_core: + vdd_a_pcie_1_core: + vdd_a_qlink_0_0p9: + vdd_a_qlink_0_0p9_ck: + vdd_a_qlink_1_0p9: + vdd_a_qlink_1_0p9_ck: + vdd_a_qrefs_0p875_0: + vdd_a_qrefs_0p875_1: + vdd_a_qrefs_0p875_2: + vdd_a_qrefs_0p875_3: + vdd_a_qrefs_0p875_4_5: + vdd_a_qrefs_0p875_6: + vdd_a_qrefs_0p875_7: + vdd_a_qrefs_0p875_8: + vdd_a_qrefs_0p875_9: + vdd_a_ufs_0_core: + vdd_a_usbhs_core: + vreg_l10c_0p88: ldo10 { + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <1050000>; + regulator-initial-mode =3D ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vdd_flash: + vdd_iris_rgb: + vdd_mic_bias: + vreg_bob: bob { + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + }; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&ipa { + status =3D "okay"; + modem-init; +}; + +/* For nvme; boards set status =3D "okay" */ +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; +}; + +&pmk8350_vadc { + pmk8350-die-temp@3 { + reg =3D ; + label =3D "pmk8350_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + pmr735a-die-temp@403 { + reg =3D ; + label =3D "pmr735a_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; +}; + +&qfprom { + vcc-supply =3D <&vdd_qfprom>; +}; + +/* For eMMC; not all Qcards have eMMC stuffed; boards set status =3D "okay= " */ +&sdhc_1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc1_on>; + pinctrl-1 =3D <&sdc1_off>; + + vmmc-supply =3D <&vreg_l7b_2p5>; + vqmmc-supply =3D <&vreg_l19b_1p8>; + + non-removable; + no-sd; + no-sdio; +}; + +uart_dbg: &uart5 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +mos_bt_uart: &uart7 { + status =3D "okay"; + + /delete-property/interrupts; + interrupts-extended =3D <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names =3D "default", "sleep"; + pinctrl-1 =3D <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7= _sleep_tx>, <&qup_uart7_sleep_rx>; + + bluetooth: bluetooth { + compatible =3D "qcom,wcn6750-bt"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mos_bt_en>; + enable-gpios =3D <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; + vddaon-supply =3D <&vreg_s7b_0p952>; + vddbtcxmx-supply =3D <&vreg_s7b_0p952>; + vddrfacmn-supply =3D <&vreg_s7b_0p952>; + vddrfa0p8-supply =3D <&vreg_s7b_0p952>; + vddrfa1p7-supply =3D <&vdd19_pmu_rfa_i>; + vddrfa1p2-supply =3D <&vdd13_pmu_rfa_i>; + vddrfa2p2-supply =3D <&vreg_s1c_2p2>; + vddasd-supply =3D <&vreg_l11c_2p8>; + vddio-supply =3D <&vreg_l18b_1p8>; + max-speed =3D <3200000>; + }; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vdd_a_usbhs_core>; + vdda33-supply =3D <&vdd_a_usbhs_3p1>; + vdda18-supply =3D <&vdd_a_usbhs_1p8>; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vdd_a_usbssdp_0_1p2>; + vdda-pll-supply =3D <&vdd_a_usbssdp_0_core>; +}; + +&usb_2_hsphy { + vdda-pll-supply =3D <&vdd_a_usbhs_core>; + vdda33-supply =3D <&vdd_a_usbhs_3p1>; + vdda18-supply =3D <&vdd_a_usbhs_1p8>; +}; + +/* + * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES + * + * NOTE: In general if pins leave the Qcard then the pinctrl goes in the + * baseboard or board device tree, not here. + */ + +/* + * For ts_i2c + * + * Technically this i2c bus actually leaves the Qcard, but it leaves direc= tly + * via the eDP connector (it doesn't hit the baseboard). The external pulls + * are on Qcard. + */ +&qup_i2c13_data_clk { + drive-strength =3D <2>; + /* Has external pull */ + bias-disable; +}; + +/* For mos_bt_uart */ +&qup_uart7_cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; +}; + +/* For mos_bt_uart */ +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength =3D <2>; + bias-disable; +}; + +/* For mos_bt_uart */ +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength =3D <2>; + bias-disable; +}; + +/* For mos_bt_uart */ +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +/* eMMC, if stuffed, is straight on the Qcard */ +&sdc1_on { + clk { + bias-disable; + drive-strength =3D <16>; + }; + + cmd { + bias-pull-up; + drive-strength =3D <10>; + }; + + data { + bias-pull-up; + drive-strength =3D <10>; + }; + + rclk { + bias-pull-down; + }; +}; + +/* + * PINCTRL - QCARD + * + * This has entries that are defined by Qcard even if they go to the main + * board. In cases where the pulls may be board dependent we defer those + * settings to the board device tree. Drive strengths tend to be assinged = here + * but could conceivably be overwridden by board device trees. + */ + +&pm8350c_gpios { + pmic_edp_bl_en: pmic-edp-bl-en { + pins =3D "gpio7"; + function =3D "normal"; + qcom,drive-strength =3D ; + bias-disable; + + /* Force backlight to be disabled to match state at boot. */ + output-low; + }; + + pmic_edp_bl_pwm: pmic-edp-bl-pwm { + pins =3D "gpio8"; + function =3D "func1"; + qcom,drive-strength =3D ; + bias-disable; + output-low; + power-source =3D <0>; + }; +}; + +&tlmm { + mos_bt_en: mos-bt-en { + pins =3D "gpio85"; + function =3D "gpio"; + drive-strength =3D <2>; + output-low; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_cts: qup-uart7-sleep-cts { + pins =3D "gpio28"; + function =3D "gpio"; + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_rts: qup-uart7-sleep-rts { + pins =3D "gpio29"; + function =3D "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_rx: qup-uart7-sleep-rx { + pins =3D "gpio31"; + function =3D "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_tx: qup-uart7-sleep-tx { + pins =3D "gpio30"; + function =3D "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + ts_int_conn: ts-int-conn { + pins =3D "gpio55"; + function =3D "gpio"; + bias-pull-up; + }; + + ts_rst_conn: ts-rst-conn { + pins =3D "gpio54"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <2>; + }; +}; --=20 2.34.1.703.g22d0c6ccf7-goog