From nobody Sun Sep 22 11:36:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 853BBC433EF for ; Wed, 12 Jan 2022 15:37:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354647AbiALPho (ORCPT ); Wed, 12 Jan 2022 10:37:44 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:43104 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1354652AbiALPhb (ORCPT ); Wed, 12 Jan 2022 10:37:31 -0500 X-UUID: 1d33b5f761bb4638be6da5f2e36adf00-20220112 X-UUID: 1d33b5f761bb4638be6da5f2e36adf00-20220112 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2104030689; Wed, 12 Jan 2022 23:37:28 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 23:37:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Jan 2022 23:37:27 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , Rex-BC Chen Subject: [v8, PATCH 1/3] drm/dsi: transfer DSI HS packets ending at the same time Date: Wed, 12 Jan 2022 23:36:37 +0800 Message-ID: <20220112153639.12343-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220112153639.12343-1-rex-bc.chen@mediatek.com> References: <20220112153639.12343-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since a HS transmission is composed of an arbitrary number of bytes that may not be an integer multiple of lanes, some lanes may run out of data before others. (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00) However, for some DSI RX devices (for example, anx7625), there is a limitation that packet number should be the same on all DSI lanes. In other words, they need to end a HS at the same time. Because this limitation is for some specific DSI RX devices, it is more reasonable to put the enable control in these DSI RX drivers. If DSI TX driver knows the information, they can adjust the setting for this situation. Therefore, add a flag to control this situation beacuse the mipi DSI specification is not forbidden this situation. Signed-off-by: Jitao Shi Reviewed-by: Chun-Kuang Hu --- include/drm/drm_mipi_dsi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 147e51b6d241..df4d15345326 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,8 @@ struct mipi_dsi_device_info { * @lp_rate: maximum lane frequency for low power mode in hertz, this shou= ld * be set to the real limits of the hardware, zero is only accepted for * legacy drivers + * @hs_packet_end_aligned: transfer DSI HS packets ending at the same time + * for all DSI lanes */ struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +191,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate; + bool hs_packet_end_aligned; }; =20 #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:" --=20 2.18.0 From nobody Sun Sep 22 11:36:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8661BC433F5 for ; Wed, 12 Jan 2022 15:37:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354670AbiALPhr (ORCPT ); Wed, 12 Jan 2022 10:37:47 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:34294 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1354679AbiALPhn (ORCPT ); Wed, 12 Jan 2022 10:37:43 -0500 X-UUID: e3e0b94b99934b7180973ed2225d3e55-20220112 X-UUID: e3e0b94b99934b7180973ed2225d3e55-20220112 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1914137431; Wed, 12 Jan 2022 23:37:39 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 23:37:37 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 23:37:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Jan 2022 23:37:37 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , Rex-BC Chen Subject: [v8, PATCH 2/3] drm/mediatek: implement the DSI hs packets aligned Date: Wed, 12 Jan 2022 23:36:38 +0800 Message-ID: <20220112153639.12343-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220112153639.12343-1-rex-bc.chen@mediatek.com> References: <20220112153639.12343-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some DSI RX devices require the packets on all lanes aligned at the end. Otherwise, there will be some issues of shift or scroll for screen. Signed-off-by: Jitao Shi Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 5d90d2eb0019..2f3ff9b595a4 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -195,6 +195,8 @@ struct mtk_dsi { struct clk *hs_clk; =20 u32 data_rate; + /* force dsi line end without dsi_null data */ + bool hs_packet_end_aligned; =20 unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *= dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); } =20 + if (dsi->hs_packet_end_aligned) { + horizontal_sync_active_byte =3D roundup(horizontal_sync_active_byte, dsi= ->lanes) - 2; + horizontal_frontporch_byte =3D roundup(horizontal_frontporch_byte, dsi->= lanes) - 2; + horizontal_backporch_byte =3D roundup(horizontal_backporch_byte, dsi->la= nes) - 2; + horizontal_backporch_byte -=3D (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi= ->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -794,6 +803,7 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *ho= st, dsi->lanes =3D device->lanes; dsi->format =3D device->format; dsi->mode_flags =3D device->mode_flags; + dsi->hs_packet_end_aligned =3D device->hs_packet_end_aligned; =20 return 0; } --=20 2.18.0 From nobody Sun Sep 22 11:36:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28768C433F5 for ; Wed, 12 Jan 2022 15:37:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354698AbiALPhx (ORCPT ); Wed, 12 Jan 2022 10:37:53 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:34334 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1354653AbiALPhn (ORCPT ); Wed, 12 Jan 2022 10:37:43 -0500 X-UUID: c0010ea03e1d4bc8b1fd8867459ae98d-20220112 X-UUID: c0010ea03e1d4bc8b1fd8867459ae98d-20220112 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1417043481; Wed, 12 Jan 2022 23:37:39 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Jan 2022 23:37:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Jan 2022 23:37:38 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , Rex-BC Chen Subject: [v8, PATCH 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift Date: Wed, 12 Jan 2022 23:36:39 +0800 Message-ID: <20220112153639.12343-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220112153639.12343-1-rex-bc.chen@mediatek.com> References: <20220112153639.12343-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This device requires the packets on lanes aligned at the end to fix screen shift or scroll. Signed-off-by: Jitao Shi Reviewed-by: Xin Ji Acked-by: Robert Foss --- drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/br= idge/analogix/anx7625.c index 2346dbcc505f..672705a68dae 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1674,6 +1674,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ct= x) dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_HSE; + dsi->hs_packet_end_aligned =3D true; =20 ret =3D devm_mipi_dsi_attach(dev, dsi); if (ret) { --=20 2.18.0