From nobody Sun Sep 22 11:32:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54626C4332F for ; Mon, 10 Jan 2022 00:59:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237691AbiAJA7h (ORCPT ); Sun, 9 Jan 2022 19:59:37 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:51876 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237650AbiAJA72 (ORCPT ); Sun, 9 Jan 2022 19:59:28 -0500 X-UUID: a63949c2b4814797b6094fb056298afb-20220110 X-UUID: a63949c2b4814797b6094fb056298afb-20220110 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 118521613; Mon, 10 Jan 2022 08:59:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 10 Jan 2022 08:59:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 10 Jan 2022 08:59:21 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Chun-Jie Chen Subject: [v2 1/3] clk: mediatek: Add error handle when fail to register clock provider Date: Mon, 10 Jan 2022 08:59:00 +0800 Message-ID: <20220110005902.27148-2-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220110005902.27148-1-chun-jie.chen@mediatek.com> References: <20220110005902.27148-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Need to deference registered clocks when fail to regisiter clock provider. Signed-off-by: Chun-Jie Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 5 ++++- drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 5 +++-- drivers/clk/mediatek/clk-mt8195-topckgen.c | 5 ++++- drivers/clk/mediatek/clk-mt8195-vdo0.c | 5 ++++- drivers/clk/mediatek/clk-mt8195-vdo1.c | 5 ++++- drivers/clk/mediatek/clk-mtk.c | 14 +++++++++++++- drivers/clk/mediatek/clk-mtk.h | 1 + 7 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 6156ceeed71e..be0a716e24d2 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -126,10 +126,13 @@ static int clk_mt8195_apmixed_probe(struct platform_d= evice *pdev) =20 r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_apmixed_data; + goto unregister_clk; =20 return r; =20 +unregister_clk: + mtk_clk_unregister(clk_data); + free_apmixed_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index f1c84186346e..bc5fc84e48dd 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -68,11 +68,12 @@ static int clk_mt8195_apusys_pll_probe(struct platform_= device *pdev) mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_dat= a); r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_apusys_pll_data; + goto unregister_clk; =20 return r; =20 -free_apusys_pll_data: +unregister_clk: + mtk_clk_unregister(clk_data); mtk_free_clk_data(clk_data); return r; } diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index 3e2aba9c40bb..02a1801dfe86 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1254,10 +1254,13 @@ static int clk_mt8195_topck_probe(struct platform_d= evice *pdev) =20 r =3D of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); if (r) - goto free_top_data; + goto unregister_clk; =20 return r; =20 +unregister_clk: + mtk_clk_unregister(top_clk_data); + free_top_data: mtk_free_clk_data(top_clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/= clk-mt8195-vdo0.c index f7ff7618c714..b7ceb6c7a33f 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -105,10 +105,13 @@ static int clk_mt8195_vdo0_probe(struct platform_devi= ce *pdev) =20 r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_vdo0_data; + goto unregister_clk; =20 return r; =20 +unregister_clk: + mtk_clk_unregister(clk_data); + free_vdo0_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/= clk-mt8195-vdo1.c index 03df8eae8838..cca90c2632a1 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -122,10 +122,13 @@ static int clk_mt8195_vdo1_probe(struct platform_devi= ce *pdev) =20 r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_vdo1_data; + goto unregister_clk; =20 return r; =20 +unregister_clk: + mtk_clk_unregister(clk_data); + free_vdo1_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 8d5791b3f460..ee4de1094458 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -303,6 +303,15 @@ void mtk_clk_register_dividers(const struct mtk_clk_di= vider *mcds, } } =20 +void mtk_clk_unregister(struct clk_onecell_data *clk_data) +{ + int i; + + for (i =3D 0; i < clk_data->clk_num; i++) + clk_unregister(clk_data->clks[i]); +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister); + int mtk_clk_simple_probe(struct platform_device *pdev) { const struct mtk_clk_desc *mcd; @@ -324,10 +333,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev) =20 r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_data; + goto unregister_clk; =20 return r; =20 +unregister_clk: + mtk_clk_unregister(clk_data); + free_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 0ff289d93452..4c0958f66f51 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -200,6 +200,7 @@ struct mtk_clk_divider { void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); +void mtk_clk_unregister(struct clk_onecell_data *clk_data); =20 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); void mtk_free_clk_data(struct clk_onecell_data *clk_data); --=20 2.18.0 From nobody Sun Sep 22 11:32:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F51EC433EF for ; Mon, 10 Jan 2022 00:59:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237707AbiAJA7v (ORCPT ); Sun, 9 Jan 2022 19:59:51 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:51962 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237659AbiAJA7a (ORCPT ); Sun, 9 Jan 2022 19:59:30 -0500 X-UUID: e6de86ec2ea54f95b866fcf10a7a682e-20220110 X-UUID: e6de86ec2ea54f95b866fcf10a7a682e-20220110 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1449463707; Mon, 10 Jan 2022 08:59:26 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 10 Jan 2022 08:59:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 10 Jan 2022 08:59:24 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Chun-Jie Chen Subject: [v2 2/3] dt-bindings: ARM: Mediatek: Remove vppsys in MT8195 clock document Date: Mon, 10 Jan 2022 08:59:01 +0800 Message-ID: <20220110005902.27148-3-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220110005902.27148-1-chun-jie.chen@mediatek.com> References: <20220110005902.27148-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vppsys0 and vppsys1 sub-system are both integrated with mmsys driver, should be describe in mediatek,mmsys.yaml Signed-off-by: Chun-Jie Chen --- .../arm/mediatek/mediatek,mt8195-clock.yaml | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195= -clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt819= 5-clock.yaml index 17fcbb45d121..d62d60181147 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.= yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.= yaml @@ -28,11 +28,9 @@ properties: - mediatek,mt8195-imp_iic_wrap_s - mediatek,mt8195-imp_iic_wrap_w - mediatek,mt8195-mfgcfg - - mediatek,mt8195-vppsys0 - mediatek,mt8195-wpesys - mediatek,mt8195-wpesys_vpp0 - mediatek,mt8195-wpesys_vpp1 - - mediatek,mt8195-vppsys1 - mediatek,mt8195-imgsys - mediatek,mt8195-imgsys1_dip_top - mediatek,mt8195-imgsys1_dip_nr @@ -92,13 +90,6 @@ examples: #clock-cells =3D <1>; }; =20 - - | - vppsys0: clock-controller@14000000 { - compatible =3D "mediatek,mt8195-vppsys0"; - reg =3D <0x14000000 0x1000>; - #clock-cells =3D <1>; - }; - - | wpesys: clock-controller@14e00000 { compatible =3D "mediatek,mt8195-wpesys"; @@ -120,13 +111,6 @@ examples: #clock-cells =3D <1>; }; =20 - - | - vppsys1: clock-controller@14f00000 { - compatible =3D "mediatek,mt8195-vppsys1"; - reg =3D <0x14f00000 0x1000>; - #clock-cells =3D <1>; - }; - - | imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; --=20 2.18.0 From nobody Sun Sep 22 11:32:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBA2DC433FE for ; Mon, 10 Jan 2022 00:59:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237675AbiAJA7x (ORCPT ); Sun, 9 Jan 2022 19:59:53 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:41348 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237665AbiAJA7b (ORCPT ); Sun, 9 Jan 2022 19:59:31 -0500 X-UUID: 0eace77e04f34a8a9c97eb8f3321413c-20220110 X-UUID: 0eace77e04f34a8a9c97eb8f3321413c-20220110 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 266559539; Mon, 10 Jan 2022 08:59:28 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 10 Jan 2022 08:59:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 10 Jan 2022 08:59:26 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Chun-Jie Chen Subject: [v2 3/3] clk: mediatek: Integrate vppsys with mtk-mmsys in MT8195 Date: Mon, 10 Jan 2022 08:59:02 +0800 Message-ID: <20220110005902.27148-4-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220110005902.27148-1-chun-jie.chen@mediatek.com> References: <20220110005902.27148-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Integrate vpp0 and vpp1 with mtk-mmsys driver which will populate device by platform_device_register_data to start vppsys clock driver. Signed-off-by: Chun-Jie Chen --- drivers/clk/mediatek/clk-mt8195-vpp0.c | 42 +++++++++++++++++--------- drivers/clk/mediatek/clk-mt8195-vpp1.c | 42 +++++++++++++++++--------- 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/= clk-mt8195-vpp0.c index c3241466a8d0..68c375bfce8b 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -86,25 +86,39 @@ static const struct mtk_gate vpp0_clks[] =3D { GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_= wpe_vpp", 3), }; =20 -static const struct mtk_clk_desc vpp0_desc =3D { - .clks =3D vpp0_clks, - .num_clks =3D ARRAY_SIZE(vpp0_clks), -}; +static int clk_mt8195_vpp0_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + struct clk_onecell_data *clk_data; + int r; =20 -static const struct of_device_id of_match_clk_mt8195_vpp0[] =3D { - { - .compatible =3D "mediatek,mt8195-vppsys0", - .data =3D &vpp0_desc, - }, { - /* sentinel */ - } -}; + clk_data =3D mtk_alloc_clk_data(CLK_VPP0_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r =3D mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_= data); + if (r) + goto free_vpp0_data; + + r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto unregister_clk; + + return r; + +unregister_clk: + mtk_clk_unregister(clk_data); + +free_vpp0_data: + mtk_free_clk_data(clk_data); + return r; +} =20 static struct platform_driver clk_mt8195_vpp0_drv =3D { - .probe =3D mtk_clk_simple_probe, + .probe =3D clk_mt8195_vpp0_probe, .driver =3D { .name =3D "clk-mt8195-vpp0", - .of_match_table =3D of_match_clk_mt8195_vpp0, }, }; builtin_platform_driver(clk_mt8195_vpp0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/= clk-mt8195-vpp1.c index ce0b9a40a179..237077c60f54 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -84,25 +84,39 @@ static const struct mtk_gate vpp1_clks[] =3D { GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26), }; =20 -static const struct mtk_clk_desc vpp1_desc =3D { - .clks =3D vpp1_clks, - .num_clks =3D ARRAY_SIZE(vpp1_clks), -}; +static int clk_mt8195_vpp1_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + struct clk_onecell_data *clk_data; + int r; =20 -static const struct of_device_id of_match_clk_mt8195_vpp1[] =3D { - { - .compatible =3D "mediatek,mt8195-vppsys1", - .data =3D &vpp1_desc, - }, { - /* sentinel */ - } -}; + clk_data =3D mtk_alloc_clk_data(CLK_VPP1_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r =3D mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_= data); + if (r) + goto free_vpp1_data; + + r =3D of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto unregister_clk; + + return r; + +unregister_clk: + mtk_clk_unregister(clk_data); + +free_vpp1_data: + mtk_free_clk_data(clk_data); + return r; +} =20 static struct platform_driver clk_mt8195_vpp1_drv =3D { - .probe =3D mtk_clk_simple_probe, + .probe =3D clk_mt8195_vpp1_probe, .driver =3D { .name =3D "clk-mt8195-vpp1", - .of_match_table =3D of_match_clk_mt8195_vpp1, }, }; builtin_platform_driver(clk_mt8195_vpp1_drv); --=20 2.18.0