From nobody Sun Sep 22 13:29:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AC49C433FE for ; Fri, 7 Jan 2022 09:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346474AbiAGJwI (ORCPT ); Fri, 7 Jan 2022 04:52:08 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:59000 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230338AbiAGJwG (ORCPT ); Fri, 7 Jan 2022 04:52:06 -0500 X-UUID: fa6f5608e40e4e69b345d9fac4b78d54-20220107 X-UUID: fa6f5608e40e4e69b345d9fac4b78d54-20220107 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 215982250; Fri, 07 Jan 2022 17:52:03 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 7 Jan 2022 17:52:02 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 7 Jan 2022 17:52:02 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , , , Guenter Roeck Subject: [PATCH v21 7/8] arm64: dts: mt8192: add svs device information Date: Fri, 7 Jan 2022 17:51:59 +0800 Message-ID: <20220107095200.4389-8-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220107095200.4389-1-roger.lu@mediatek.com> References: <20220107095200.4389-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compitable/reg/irq/clock/efuse/reset setting in svs node. Signed-off-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index c7c7d4e017ae..c111e26489dd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include + =20 / { compatible =3D "mediatek,mt8192"; @@ -268,6 +270,14 @@ compatible =3D "mediatek,mt8192-infracfg", "syscon"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + + infracfg_rst: reset-controller { + compatible =3D "mediatek,infra-reset", "ti,syscon-reset"; + #reset-cells =3D <1>; + ti,reset-bits =3D < + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* = 0: svs */ + >; + }; }; =20 pericfg: syscon@10003000 { @@ -362,6 +372,20 @@ status =3D "disabled"; }; =20 + svs: svs@1100b000 { + compatible =3D "mediatek,mt8192-svs"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + clock-names =3D "main"; + nvmem-cells =3D <&svs_calibration>, + <&lvts_e_data1>; + nvmem-cell-names =3D "svs-calibration-data", + "t-calibration-data"; + resets =3D <&infracfg_rst 0>; + reset-names =3D "svs_rst"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -479,6 +503,21 @@ #clock-cells =3D <1>; }; =20 + efuse: efuse@11c10000 { + compatible =3D "mediatek,efuse"; + reg =3D <0 0x11c10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_e_data1: data1@1c0 { + reg =3D <0x1c0 0x58>; + }; + + svs_calibration: calib@580 { + reg =3D <0x580 0x68>; + }; + }; + i2c3: i2c3@11cb0000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11cb0000 0 0x1000>, --=20 2.18.0