From nobody Sun Sep 22 11:33:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D01FC433F5 for ; Thu, 6 Jan 2022 06:54:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235102AbiAFGyX (ORCPT ); Thu, 6 Jan 2022 01:54:23 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:38696 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234688AbiAFGyW (ORCPT ); Thu, 6 Jan 2022 01:54:22 -0500 X-UUID: f73e721898794e26b8c142e34d23b077-20220106 X-UUID: f73e721898794e26b8c142e34d23b077-20220106 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1059487081; Thu, 06 Jan 2022 14:54:19 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 6 Jan 2022 14:54:18 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Jan 2022 14:54:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Jan 2022 14:54:17 +0800 From: Johnson Wang To: , , CC: , , , , , Johnson Wang Subject: [PATCH 1/4] mfd: Add support for the MediaTek MT6366 PMIC Date: Thu, 6 Jan 2022 14:54:04 +0800 Message-ID: <20220106065407.16036-2-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220106065407.16036-1-johnson.wang@mediatek.com> References: <20220106065407.16036-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds support for the MediaTek MT6366 PMIC. This is a multifunction device with the following sub modules: - Regulator - RTC - Codec - Interrupt It is interfaced to the host controller using SPI interface by a proprietary hardware called PMIC wrapper or pwrap. MT6366 MFD is a child device of the pwrap. Signed-off-by: Johnson Wang --- drivers/mfd/mt6358-irq.c | 1 + include/linux/mfd/mt6358/registers.h | 7 +++++++ include/linux/mfd/mt6397/core.h | 1 + 3 files changed, 9 insertions(+) diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c index 83f3ffbdbb4c..ea5e452510eb 100644 --- a/drivers/mfd/mt6358-irq.c +++ b/drivers/mfd/mt6358-irq.c @@ -212,6 +212,7 @@ int mt6358_irq_init(struct mt6397_chip *chip) =20 switch (chip->chip_id) { case MT6358_CHIP_ID: + case MT6366_CHIP_ID: chip->irq_data =3D &mt6358_irqd; break; =20 diff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt635= 8/registers.h index 201139b12140..3d33517f178c 100644 --- a/include/linux/mfd/mt6358/registers.h +++ b/include/linux/mfd/mt6358/registers.h @@ -94,6 +94,10 @@ #define MT6358_BUCK_VCORE_CON0 0x1488 #define MT6358_BUCK_VCORE_DBG0 0x149e #define MT6358_BUCK_VCORE_DBG1 0x14a0 +#define MT6358_BUCK_VCORE_SSHUB_CON0 0x14a4 +#define MT6358_BUCK_VCORE_SSHUB_CON1 0x14a6 +#define MT6358_BUCK_VCORE_SSHUB_ELR0 MT6358_BUCK_VCORE_SSHUB_CON1 +#define MT6358_BUCK_VCORE_SSHUB_DBG1 MT6358_BUCK_VCORE_DBG1 #define MT6358_BUCK_VCORE_ELR0 0x14aa #define MT6358_BUCK_VGPU_CON0 0x1508 #define MT6358_BUCK_VGPU_DBG0 0x151e @@ -169,6 +173,9 @@ #define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6 #define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0 #define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2 +#define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON0 0x1bc4 +#define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1 0x1bc6 +#define MT6358_LDO_VSRAM_OTHERS_SSHUB_DBG1 MT6358_LDO_VSRAM_OTHERS_DBG1 #define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8 #define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2 #define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4 diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/cor= e.h index 56f210eebc54..1cf78726503b 100644 --- a/include/linux/mfd/mt6397/core.h +++ b/include/linux/mfd/mt6397/core.h @@ -14,6 +14,7 @@ enum chip_id { MT6323_CHIP_ID =3D 0x23, MT6358_CHIP_ID =3D 0x58, MT6359_CHIP_ID =3D 0x59, + MT6366_CHIP_ID =3D 0x66, MT6391_CHIP_ID =3D 0x91, MT6397_CHIP_ID =3D 0x97, }; --=20 2.18.0 From nobody Sun Sep 22 11:33:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59DB1C4332F for ; Thu, 6 Jan 2022 06:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235165AbiAFGy1 (ORCPT ); Thu, 6 Jan 2022 01:54:27 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:38716 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235006AbiAFGyY (ORCPT ); Thu, 6 Jan 2022 01:54:24 -0500 X-UUID: 373089ef56674d4a843a3bf201546a1c-20220106 X-UUID: 373089ef56674d4a843a3bf201546a1c-20220106 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1435882718; Thu, 06 Jan 2022 14:54:19 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Jan 2022 14:54:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Jan 2022 14:54:17 +0800 From: Johnson Wang To: , , CC: , , , , , Johnson Wang Subject: [PATCH 2/4] regulator: mt6366: Add support for MT6366 regulator Date: Thu, 6 Jan 2022 14:54:05 +0800 Message-ID: <20220106065407.16036-3-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220106065407.16036-1-johnson.wang@mediatek.com> References: <20220106065407.16036-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT6366 is a regulator found on boards based on MediaTek MT8186 and probably other SoCs. It is a so called pmic and connects as a slave to SoC using SPI, wrapped inside the pmic-wrapper. Signed-off-by: Johnson Wang --- drivers/regulator/mt6358-regulator.c | 213 ++++++++++++++++++++- include/linux/regulator/mt6358-regulator.h | 45 +++++ 2 files changed, 253 insertions(+), 5 deletions(-) diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt635= 8-regulator.c index eb8027813b99..8a5ce990f1bf 100644 --- a/drivers/regulator/mt6358-regulator.c +++ b/drivers/regulator/mt6358-regulator.c @@ -130,6 +130,102 @@ struct mt6358_regulator_info { .qi =3D BIT(15), \ } =20 +#define MT6366_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \ + _modeset_reg, _modeset_shift) \ +[MT6366_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6358_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6366_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ((max) - (min)) / (step) + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D MT6358_BUCK_##vreg##_ELR0, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D MT6358_BUCK_##vreg##_CON0, \ + .enable_mask =3D BIT(0), \ + .of_map_mode =3D mt6358_map_mode, \ + }, \ + .status_reg =3D MT6358_BUCK_##vreg##_DBG1, \ + .qi =3D BIT(0), \ + .da_vsel_reg =3D _da_vsel_reg, \ + .da_vsel_mask =3D _da_vsel_mask, \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D BIT(_modeset_shift), \ +} + +#define MT6366_LDO(match, vreg, ldo_volt_table, \ + ldo_index_table, enreg, enbit, vosel, \ + vosel_mask) \ +[MT6366_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6358_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6366_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .status_reg =3D MT6358_LDO_##vreg##_CON1, \ + .qi =3D BIT(15), \ + .index_table =3D ldo_index_table, \ + .n_table =3D ARRAY_SIZE(ldo_index_table), \ +} + +#define MT6366_LDO1(match, vreg, min, max, step, \ + volt_ranges, _da_vsel_reg, _da_vsel_mask, \ + vosel, vosel_mask) \ +[MT6366_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6358_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6366_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ((max) - (min)) / (step) + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D MT6358_LDO_##vreg##_CON0, \ + .enable_mask =3D BIT(0), \ + }, \ + .da_vsel_reg =3D _da_vsel_reg, \ + .da_vsel_mask =3D _da_vsel_mask, \ + .status_reg =3D MT6358_LDO_##vreg##_DBG1, \ + .qi =3D BIT(0), \ +} + +#define MT6366_REG_FIXED(match, vreg, \ + enreg, enbit, volt) \ +[MT6366_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6358_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6366_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .min_uV =3D volt, \ + }, \ + .status_reg =3D MT6358_LDO_##vreg##_CON1, \ + .qi =3D BIT(15), \ +} + static const struct linear_range buck_volt_range1[] =3D { REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), }; @@ -409,6 +505,9 @@ static struct mt6358_regulator_info mt6358_regulators[]= =3D { MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250, buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1), + MT6358_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f, + MT6358_VCORE_VGPU_ANA_CON0, 1), MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3), @@ -488,6 +587,10 @@ static struct mt6358_regulator_info mt6358_regulators[= ] =3D { MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f), + MT6358_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000, + 1293750, 6250, buck_volt_range1, + MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f, + MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f), MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250, buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f), @@ -496,24 +599,124 @@ static struct mt6358_regulator_info mt6358_regulator= s[] =3D { MT6358_LDO_VSRAM_CON1, 0x7f), }; =20 +/* The array is indexed by id(MT6366_ID_XXX) */ +static struct mt6358_regulator_info mt6366_regulators[] =3D { + MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500, + buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, + MT6358_VDRAM1_ANA_CON0, 8), + MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, + MT6358_VCORE_VGPU_ANA_CON0, 1), + MT6366_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f, + MT6358_VCORE_VGPU_ANA_CON0, 1), + MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, + MT6358_VPA_ANA_CON0, 3), + MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, + MT6358_VPROC_ANA_CON0, 1), + MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, + MT6358_VPROC_ANA_CON0, 2), + MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, + MT6358_VCORE_VGPU_ANA_CON0, 2), + MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500, + buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, + MT6358_VS2_ANA_CON0, 8), + MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, + MT6358_VMODEM_ANA_CON0, 8), + MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500, + buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, + MT6358_VS1_ANA_CON0, 8), + MT6366_REG_FIXED("ldo_vrf12", VRF12, + MT6358_LDO_VRF12_CON0, 0, 1200000), + MT6366_REG_FIXED("ldo_vio18", VIO18, + MT6358_LDO_VIO18_CON0, 0, 1800000), + MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000), + MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000), + MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000), + MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000), + MT6366_REG_FIXED("ldo_vaux18", VAUX18, + MT6358_LDO_VAUX18_CON0, 0, 1800000), + MT6366_REG_FIXED("ldo_vbif28", VBIF28, + MT6358_LDO_VBIF28_CON0, 0, 2800000), + MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000), + MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000), + MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000), + MT6366_REG_FIXED("ldo_vaud28", VAUD28, + MT6358_LDO_VAUD28_CON0, 0, 2800000), + MT6366_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx, + MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10), + MT6366_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx, + MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00), + MT6366_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx, + MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00), + MT6366_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx, + MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700), + MT6366_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx, + MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00), + MT6366_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx, + MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700), + MT6366_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx, + MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700), + MT6366_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages, + vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0, + 0, MT6358_VCN33_ANA_CON0, 0x300), + MT6366_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages, + vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1, + 0, MT6358_VCN33_ANA_CON0, 0x300), + MT6366_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx, + MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00), + MT6366_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx, + MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00), + MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, + MT6358_LDO_VSRAM_CON0, 0x7f), + MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, + MT6358_LDO_VSRAM_CON2, 0x7f), + MT6366_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000, + 1293750, 6250, buck_volt_range1, + MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f, + MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f), + MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, + MT6358_LDO_VSRAM_CON3, 0x7f), + MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, + MT6358_LDO_VSRAM_CON1, 0x7f), +}; + static int mt6358_regulator_probe(struct platform_device *pdev) { struct mt6397_chip *mt6397 =3D dev_get_drvdata(pdev->dev.parent); struct regulator_config config =3D {}; struct regulator_dev *rdev; - int i; + struct mt6358_regulator_info *mt6358_info; + int i, max_regulator; + + if (mt6397->chip_id =3D=3D MT6366_CHIP_ID) { + max_regulator =3D MT6366_MAX_REGULATOR; + mt6358_info =3D mt6366_regulators; + } else { + max_regulator =3D MT6358_MAX_REGULATOR; + mt6358_info =3D mt6358_regulators; + } =20 - for (i =3D 0; i < MT6358_MAX_REGULATOR; i++) { + for (i =3D 0; i < max_regulator; i++) { config.dev =3D &pdev->dev; - config.driver_data =3D &mt6358_regulators[i]; + config.driver_data =3D &mt6358_info[i]; config.regmap =3D mt6397->regmap; =20 rdev =3D devm_regulator_register(&pdev->dev, - &mt6358_regulators[i].desc, + &mt6358_info[i].desc, &config); if (IS_ERR(rdev)) { dev_err(&pdev->dev, "failed to register %s\n", - mt6358_regulators[i].desc.name); + mt6358_info[i].desc.name); return PTR_ERR(rdev); } } diff --git a/include/linux/regulator/mt6358-regulator.h b/include/linux/reg= ulator/mt6358-regulator.h index 1cc304946d09..bdcf83cd719e 100644 --- a/include/linux/regulator/mt6358-regulator.h +++ b/include/linux/regulator/mt6358-regulator.h @@ -48,9 +48,54 @@ enum { MT6358_ID_VLDO28, MT6358_ID_VAUD28, MT6358_ID_VSIM2, + MT6358_ID_VCORE_SSHUB, + MT6358_ID_VSRAM_OTHERS_SSHUB, MT6358_ID_RG_MAX, }; =20 +enum { + MT6366_ID_VDRAM1 =3D 0, + MT6366_ID_VCORE, + MT6366_ID_VPA, + MT6366_ID_VPROC11, + MT6366_ID_VPROC12, + MT6366_ID_VGPU, + MT6366_ID_VS2, + MT6366_ID_VMODEM, + MT6366_ID_VS1, + MT6366_ID_VDRAM2, + MT6366_ID_VSIM1, + MT6366_ID_VIBR, + MT6366_ID_VRF12, + MT6366_ID_VIO18, + MT6366_ID_VUSB, + MT6366_ID_VCN18, + MT6366_ID_VFE28, + MT6366_ID_VSRAM_PROC11, + MT6366_ID_VCN28, + MT6366_ID_VSRAM_OTHERS, + MT6366_ID_VSRAM_GPU, + MT6366_ID_VXO22, + MT6366_ID_VEFUSE, + MT6366_ID_VAUX18, + MT6366_ID_VMCH, + MT6366_ID_VBIF28, + MT6366_ID_VSRAM_PROC12, + MT6366_ID_VEMC, + MT6366_ID_VIO28, + MT6366_ID_VA12, + MT6366_ID_VRF18, + MT6366_ID_VCN33_BT, + MT6366_ID_VCN33_WIFI, + MT6366_ID_VMC, + MT6366_ID_VAUD28, + MT6366_ID_VSIM2, + MT6366_ID_VCORE_SSHUB, + MT6366_ID_VSRAM_OTHERS_SSHUB, + MT6366_ID_RG_MAX, +}; + #define MT6358_MAX_REGULATOR MT6358_ID_RG_MAX +#define MT6366_MAX_REGULATOR MT6366_ID_RG_MAX =20 #endif /* __LINUX_REGULATOR_MT6358_H */ --=20 2.18.0 From nobody Sun Sep 22 11:33:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 702C4C433F5 for ; Thu, 6 Jan 2022 06:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235250AbiAFGy3 (ORCPT ); Thu, 6 Jan 2022 01:54:29 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:39144 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234688AbiAFGyY (ORCPT ); Thu, 6 Jan 2022 01:54:24 -0500 X-UUID: 8f5367ffbd1a4d41aeb53e0d83121de1-20220106 X-UUID: 8f5367ffbd1a4d41aeb53e0d83121de1-20220106 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1999898728; Thu, 06 Jan 2022 14:54:18 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 6 Jan 2022 14:54:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Jan 2022 14:54:18 +0800 From: Johnson Wang To: , , CC: , , , , , Johnson Wang Subject: [PATCH 3/4] dt-bindings: mfd: Add compatible for the MediaTek MT6366 PMIC Date: Thu, 6 Jan 2022 14:54:06 +0800 Message-ID: <20220106065407.16036-4-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220106065407.16036-1-johnson.wang@mediatek.com> References: <20220106065407.16036-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds compatible for the MediaTek MT6366 PMIC. Signed-off-by: Johnson Wang Acked-by: Rob Herring --- Documentation/devicetree/bindings/mfd/mt6397.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentati= on/devicetree/bindings/mfd/mt6397.txt index 99a84b69a29f..293db2a71ef2 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -20,7 +20,7 @@ This document describes the binding for MFD device and it= s sub module. Required properties: compatible: "mediatek,mt6323" for PMIC MT6323 - "mediatek,mt6358" for PMIC MT6358 + "mediatek,mt6358" for PMIC MT6358 and MT6366 "mediatek,mt6359" for PMIC MT6359 "mediatek,mt6397" for PMIC MT6397 =20 --=20 2.18.0 From nobody Sun Sep 22 11:33:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58804C43217 for ; Thu, 6 Jan 2022 06:54:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235259AbiAFGyc (ORCPT ); Thu, 6 Jan 2022 01:54:32 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:38866 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235172AbiAFGy2 (ORCPT ); Thu, 6 Jan 2022 01:54:28 -0500 X-UUID: 8b137e16475741028ed2340d384d0748-20220106 X-UUID: 8b137e16475741028ed2340d384d0748-20220106 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1150771980; Thu, 06 Jan 2022 14:54:26 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 6 Jan 2022 14:54:24 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Jan 2022 14:54:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Jan 2022 14:54:18 +0800 From: Johnson Wang To: , , CC: , , , , , Johnson Wang Subject: [PATCH 4/4] dt-bindings: regulator: Add MT6358 regulators Date: Thu, 6 Jan 2022 14:54:07 +0800 Message-ID: <20220106065407.16036-5-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220106065407.16036-1-johnson.wang@mediatek.com> References: <20220106065407.16036-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add buck_vcore_sshub and ldo_vsram_others_sshub regulators to binding document for MT6358 and MT6366. Signed-off-by: Johnson Wang Reviewed-by: Rob Herring --- .../bindings/regulator/mt6358-regulator.txt | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/mt6358-regulator.t= xt b/Documentation/devicetree/bindings/regulator/mt6358-regulator.txt index 9a90a92f2d7e..7034cdca54e0 100644 --- a/Documentation/devicetree/bindings/regulator/mt6358-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/mt6358-regulator.txt @@ -8,14 +8,14 @@ Documentation/devicetree/bindings/regulator/regulator.txt. =20 The valid names for regulators are:: BUCK: - buck_vdram1, buck_vcore, buck_vpa, buck_vproc11, buck_vproc12, buck_vgpu, - buck_vs2, buck_vmodem, buck_vs1 + buck_vdram1, buck_vcore, buck_vcore_sshub, buck_vpa, buck_vproc11, + buck_vproc12, buck_vgpu, buck_vs2, buck_vmodem, buck_vs1 LDO: ldo_vdram2, ldo_vsim1, ldo_vibr, ldo_vrf12, ldo_vio18, ldo_vusb, ldo_vca= mio, ldo_vcamd, ldo_vcn18, ldo_vfe28, ldo_vsram_proc11, ldo_vcn28, ldo_vsram_= others, - ldo_vsram_gpu, ldo_vxo22, ldo_vefuse, ldo_vaux18, ldo_vmch, ldo_vbif28, - ldo_vsram_proc12, ldo_vcama1, ldo_vemc, ldo_vio28, ldo_va12, ldo_vrf18, - ldo_vcn33_bt, ldo_vcn33_wifi, ldo_vcama2, ldo_vmc, ldo_vldo28, ldo_vaud2= 8, + ldo_vsram_others_sshub, ldo_vsram_gpu, ldo_vxo22, ldo_vefuse, ldo_vaux18, + ldo_vmch, ldo_vbif28, ldo_vsram_proc12, ldo_vcama1, ldo_vemc, ldo_vio28,= ldo_va12, + ldo_vrf18, ldo_vcn33_bt, ldo_vcn33_wifi, ldo_vcama2, ldo_vmc, ldo_vldo28= , ldo_vaud28, ldo_vsim2 =20 Example: @@ -354,5 +354,17 @@ Example: regulator-max-microvolt =3D <3100000>; regulator-enable-ramp-delay =3D <540>; }; + + mt6358_vcore_sshub_reg: buck_vcore_sshub { + regulator-name =3D "vcore_sshub"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1293750>; + }; + + mt6358_vsram_others_sshub_reg: ldo_vsram_others_sshub { + regulator-name =3D "vsram_others_sshub"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1293750>; + }; }; }; --=20 2.18.0