From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C12C4167B for ; Wed, 5 Jan 2022 18:34:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243077AbiAESe2 (ORCPT ); Wed, 5 Jan 2022 13:34:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243023AbiAESeV (ORCPT ); Wed, 5 Jan 2022 13:34:21 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 706D4C06118A for ; Wed, 5 Jan 2022 10:34:20 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id r17so62265wrc.3 for ; Wed, 05 Jan 2022 10:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7sCt1j81wCP4UN2kM5yRhlJdHRsU1cx9asSc64DRuMM=; b=eQLU05L/hqzVvVvH5aONSF8yLEMm+TgIXGXLEXd7v/cbrUCKAxS/opPr3orYikxaXw zREF3zsKVYm6BlYNIkiq1OB7HUG/j7cGOnRVAx71+rM/mjTk8ZKK2YS5ktl9V89VEiV3 4W4/M9LfKOcDGbGekka5xG5I10KTauXe78W7jzXTnyYpPJpX99lPdojh8rL6LAbjF4fT cHNBaUwSO744FoAn8nJ4qUTnWc/ENqohS4akXAFSygQvhTCeZndDb3pxLNNfwlJavjcn SRL+cswawziA15s6QLIwfPJ9Nbp1+fUQNkTyVlu5qIuGtiWs7i5YcEnEfADIJ8tzTNDT JXmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7sCt1j81wCP4UN2kM5yRhlJdHRsU1cx9asSc64DRuMM=; b=KJUQuzV09xqtmQVLaP6pO6AwhER0/nTZaAM0ihVmcu1jMyyyOmtQwBm8wsKiGjsSzJ 84HBvFrdqIJUUYUsOrUFYZqF5zI34R51YwZe+Mrh2uyTxa4Tf/afMqgMYnLabNO367n3 DooxFL1gN7e8ErnDGVWugdSGORjMXImd7awCWWM0r7UW9YvPFWoZ6wK/CgCVE4SfQLpf BfOmfHT0Ut1TzOGK6okz02dGx5CEbNHsEuvWvLsz2wmdU+gXml52/GnuRjD4juJ64sPv 0pglkTIZbedBXLuRVmrKk+w9HrxsUWrdoaITefMiYPxviLEq6PMeKl2Xyv7id1PwM+WS Gg5A== X-Gm-Message-State: AOAM532uQmNPz3bp3hPur/J34bRNdVaJKWL2/FSPShIk2X5F4DZMuMx5 xmMjscezMcczqu8M/gGdemUjyw== X-Google-Smtp-Source: ABdhPJyaNBR5PHGQ7Fo7MCb7vlriftnsQHD4sOsiOfjjNvo/6uuldE3QqxA4OBMpQnRkRAv7XPnyXg== X-Received: by 2002:a5d:47ab:: with SMTP id 11mr48721927wrb.249.1641407658926; Wed, 05 Jan 2022 10:34:18 -0800 (PST) Received: from localhost.localdomain ([81.178.195.252]) by smtp.gmail.com with ESMTPSA id o1sm3272215wmc.38.2022.01.05.10.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 10:34:18 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v2 1/7] mfd: qcom-spmi-pmic: expose the PMIC revid information to clients Date: Wed, 5 Jan 2022 18:33:47 +0000 Message-Id: <20220105183353.2505744-2-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some PMIC functions such as the RRADC need to be aware of the PMIC chip revision information to implement errata or otherwise adjust behaviour, export the PMIC information to enable this. This is specifically required to enable the RRADC to adjust coefficients based on which chip fab the PMIC was produced in, this can vary per unique device and therefore has to be read at runtime. Signed-off-by: Caleb Connolly --- drivers/mfd/qcom-spmi-pmic.c | 108 +++++++++++++++++------------------ include/soc/qcom/qcom-pmic.h | 63 ++++++++++++++++++++ 2 files changed, 114 insertions(+), 57 deletions(-) create mode 100644 include/soc/qcom/qcom-pmic.h diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 1cacc00aa6c9..6b75c2f52b74 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -3,51 +3,24 @@ * Copyright (c) 2014, The Linux Foundation. All rights reserved. */ =20 +#include +#include #include #include +#include #include #include #include +#include =20 #define PMIC_REV2 0x101 #define PMIC_REV3 0x102 #define PMIC_REV4 0x103 #define PMIC_TYPE 0x104 #define PMIC_SUBTYPE 0x105 - +#define PMIC_FAB_ID 0x1f2 #define PMIC_TYPE_VALUE 0x51 =20 -#define COMMON_SUBTYPE 0x00 -#define PM8941_SUBTYPE 0x01 -#define PM8841_SUBTYPE 0x02 -#define PM8019_SUBTYPE 0x03 -#define PM8226_SUBTYPE 0x04 -#define PM8110_SUBTYPE 0x05 -#define PMA8084_SUBTYPE 0x06 -#define PMI8962_SUBTYPE 0x07 -#define PMD9635_SUBTYPE 0x08 -#define PM8994_SUBTYPE 0x09 -#define PMI8994_SUBTYPE 0x0a -#define PM8916_SUBTYPE 0x0b -#define PM8004_SUBTYPE 0x0c -#define PM8909_SUBTYPE 0x0d -#define PM8028_SUBTYPE 0x0e -#define PM8901_SUBTYPE 0x0f -#define PM8950_SUBTYPE 0x10 -#define PMI8950_SUBTYPE 0x11 -#define PM8998_SUBTYPE 0x14 -#define PMI8998_SUBTYPE 0x15 -#define PM8005_SUBTYPE 0x18 -#define PM660L_SUBTYPE 0x1A -#define PM660_SUBTYPE 0x1B -#define PM8150_SUBTYPE 0x1E -#define PM8150L_SUBTYPE 0x1f -#define PM8150B_SUBTYPE 0x20 -#define PMK8002_SUBTYPE 0x21 -#define PM8009_SUBTYPE 0x24 -#define PM8150C_SUBTYPE 0x26 -#define SMB2351_SUBTYPE 0x29 - static const struct of_device_id pmic_spmi_id_table[] =3D { { .compatible =3D "qcom,pm660", .data =3D (void *)PM660_SUBTYPE }, { .compatible =3D "qcom,pm660l", .data =3D (void *)PM660L_SUBTYPE }, @@ -81,42 +54,47 @@ static const struct of_device_id pmic_spmi_id_table[] = =3D { { } }; =20 -static void pmic_spmi_show_revid(struct regmap *map, struct device *dev) +static int pmic_spmi_load_revid(struct regmap *map, struct device *dev, + struct qcom_spmi_pmic *pmic) { - unsigned int rev2, minor, major, type, subtype; - const char *name =3D "unknown"; int ret, i; =20 - ret =3D regmap_read(map, PMIC_TYPE, &type); + ret =3D regmap_read(map, PMIC_TYPE, &pmic->type); if (ret < 0) - return; + return ret; =20 - if (type !=3D PMIC_TYPE_VALUE) - return; + if (pmic->type !=3D PMIC_TYPE_VALUE) + return ret; =20 - ret =3D regmap_read(map, PMIC_SUBTYPE, &subtype); + ret =3D regmap_read(map, PMIC_SUBTYPE, &pmic->subtype); if (ret < 0) - return; + return ret; =20 for (i =3D 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) { - if (subtype =3D=3D (unsigned long)pmic_spmi_id_table[i].data) + if (pmic->subtype =3D=3D (unsigned long)pmic_spmi_id_table[i].data) break; } =20 if (i !=3D ARRAY_SIZE(pmic_spmi_id_table)) - name =3D pmic_spmi_id_table[i].compatible; + pmic->name =3D devm_kstrdup_const(dev, pmic_spmi_id_table[i].compatible,= GFP_KERNEL); =20 - ret =3D regmap_read(map, PMIC_REV2, &rev2); + ret =3D regmap_read(map, PMIC_REV2, &pmic->rev2); if (ret < 0) - return; + return ret; =20 - ret =3D regmap_read(map, PMIC_REV3, &minor); + ret =3D regmap_read(map, PMIC_REV3, &pmic->minor); if (ret < 0) - return; + return ret; =20 - ret =3D regmap_read(map, PMIC_REV4, &major); + ret =3D regmap_read(map, PMIC_REV4, &pmic->major); if (ret < 0) - return; + return ret; + + if (pmic->subtype =3D=3D PMI8998_SUBTYPE || pmic->subtype =3D=3D PM660_SU= BTYPE) { + ret =3D regmap_read(map, PMIC_FAB_ID, &pmic->fab_id); + if (ret < 0) + return ret; + } =20 /* * In early versions of PM8941 and PM8226, the major revision number @@ -124,14 +102,14 @@ static void pmic_spmi_show_revid(struct regmap *map, = struct device *dev) * Increment the major revision number here if the chip is an early * version of PM8941 or PM8226. */ - if ((subtype =3D=3D PM8941_SUBTYPE || subtype =3D=3D PM8226_SUBTYPE) && - major < 0x02) - major++; + if ((pmic->subtype =3D=3D PM8941_SUBTYPE || pmic->subtype =3D=3D PM8226_S= UBTYPE) && + pmic->major < 0x02) + pmic->major++; =20 - if (subtype =3D=3D PM8110_SUBTYPE) - minor =3D rev2; + if (pmic->subtype =3D=3D PM8110_SUBTYPE) + pmic->minor =3D pmic->rev2; =20 - dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor); + return 0; } =20 static const struct regmap_config spmi_regmap_config =3D { @@ -144,22 +122,38 @@ static const struct regmap_config spmi_regmap_config = =3D { static int pmic_spmi_probe(struct spmi_device *sdev) { struct regmap *regmap; + struct qcom_spmi_pmic *pmic; =20 regmap =3D devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + pmic =3D devm_kzalloc(&sdev->dev, sizeof(*pmic), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + /* Only the first slave id for a PMIC contains this information */ - if (sdev->usid % 2 =3D=3D 0) - pmic_spmi_show_revid(regmap, &sdev->dev); + if (sdev->usid % 2 =3D=3D 0) { + pmic_spmi_load_revid(regmap, &sdev->dev, pmic); + spmi_device_set_drvdata(sdev, pmic); + qcom_pmic_print_info(&sdev->dev, pmic); + } =20 return devm_of_platform_populate(&sdev->dev); } =20 +static void pmic_spmi_remove(struct spmi_device *sdev) +{ + struct qcom_spmi_pmic *pmic =3D spmi_device_get_drvdata(sdev); + + kfree(pmic->name); +} + MODULE_DEVICE_TABLE(of, pmic_spmi_id_table); =20 static struct spmi_driver pmic_spmi_driver =3D { .probe =3D pmic_spmi_probe, + .remove =3D pmic_spmi_remove, .driver =3D { .name =3D "pmic-spmi", .of_match_table =3D pmic_spmi_id_table, diff --git a/include/soc/qcom/qcom-pmic.h b/include/soc/qcom/qcom-pmic.h new file mode 100644 index 000000000000..59114988582d --- /dev/null +++ b/include/soc/qcom/qcom-pmic.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2021 Linaro. All rights reserved. + * Copyright (c) 2021 Caleb Connolly + */ + +#ifndef __QCOM_PMIC_H__ +#define __QCOM_PMIC_H__ + +#define COMMON_SUBTYPE 0x00 +#define PM8941_SUBTYPE 0x01 +#define PM8841_SUBTYPE 0x02 +#define PM8019_SUBTYPE 0x03 +#define PM8226_SUBTYPE 0x04 +#define PM8110_SUBTYPE 0x05 +#define PMA8084_SUBTYPE 0x06 +#define PMI8962_SUBTYPE 0x07 +#define PMD9635_SUBTYPE 0x08 +#define PM8994_SUBTYPE 0x09 +#define PMI8994_SUBTYPE 0x0a +#define PM8916_SUBTYPE 0x0b +#define PM8004_SUBTYPE 0x0c +#define PM8909_SUBTYPE 0x0d +#define PM8028_SUBTYPE 0x0e +#define PM8901_SUBTYPE 0x0f +#define PM8950_SUBTYPE 0x10 +#define PMI8950_SUBTYPE 0x11 +#define PM8998_SUBTYPE 0x14 +#define PMI8998_SUBTYPE 0x15 +#define PM8005_SUBTYPE 0x18 +#define PM660L_SUBTYPE 0x1A +#define PM660_SUBTYPE 0x1B +#define PM8150_SUBTYPE 0x1E +#define PM8150L_SUBTYPE 0x1f +#define PM8150B_SUBTYPE 0x20 +#define PMK8002_SUBTYPE 0x21 +#define PM8009_SUBTYPE 0x24 +#define PM8150C_SUBTYPE 0x26 +#define SMB2351_SUBTYPE 0x29 + +#define PMI8998_FAB_ID_SMIC 0x11 +#define PMI8998_FAB_ID_GF 0x30 + +#define PM660_FAB_ID_GF 0x0 +#define PM660_FAB_ID_TSMC 0x2 +#define PM660_FAB_ID_MX 0x3 + +struct qcom_spmi_pmic { + unsigned int type; + unsigned int subtype; + unsigned int major; + unsigned int minor; + unsigned int rev2; + unsigned int fab_id; + const char *name; +}; + +static inline void qcom_pmic_print_info(struct device *dev, struct qcom_sp= mi_pmic *pmic) +{ + dev_info(dev, "%x: %s v%d.%d\n", + pmic->subtype, pmic->name, pmic->major, pmic->minor); +} + +#endif /* __QCOM_PMIC_H__ */ --=20 2.34.1 From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA32C433F5 for ; Wed, 5 Jan 2022 18:35:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243197AbiAESfI (ORCPT ); Wed, 5 Jan 2022 13:35:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243015AbiAESeW (ORCPT ); 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Wed, 05 Jan 2022 10:34:19 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org, Rob Herring Subject: [PATCH v2 2/7] dt-bindings: iio: adc: document qcom-spmi-rradc Date: Wed, 5 Jan 2022 18:33:48 +0000 Message-Id: <20220105183353.2505744-3-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-binding docs for the Qualcomm SPMI RRADC found in PMICs like PMI8998 and PMI8994 Signed-off-by: Caleb Connolly Reviewed-by: Rob Herring --- .../bindings/iio/adc/qcom,spmi-rradc.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-rra= dc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml= b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml new file mode 100644 index 000000000000..11d47c46a48d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC Round Robin ADC + +maintainers: + - Caleb Connolly + +description: | + The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients = to read the + voltage, current and temperature for supported peripherals such as the b= attery thermistor + die temperature, charger temperature, USB and DC input voltage / current= and battery ID + resistor. + +properties: + compatible: + enum: + - qcom,pmi8998-rradc + - qcom,pm660-rradc + + reg: + description: rradc base address and length in the SPMI PMIC register m= ap + maxItems: 1 + + qcom,batt-id-delay-ms: + description: + Sets the hardware settling time for the battery ID resistor. + enum: [0, 1, 4, 12, 20, 40, 60, 80] + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmic { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic_rradc: adc@4500 { + compatible =3D "qcom,pmi8998-rradc"; + reg =3D <0x4500>; + #io-channel-cells =3D <1>; + }; + }; +... --=20 2.34.1 From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E766C433F5 for ; Wed, 5 Jan 2022 18:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243089AbiAESfQ (ORCPT ); Wed, 5 Jan 2022 13:35:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243042AbiAESeY (ORCPT ); Wed, 5 Jan 2022 13:34:24 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CEEDC034006 for ; Wed, 5 Jan 2022 10:34:22 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id h23so81945wrc.1 for ; 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Wed, 05 Jan 2022 10:34:20 -0800 (PST) Received: from localhost.localdomain ([81.178.195.252]) by smtp.gmail.com with ESMTPSA id o1sm3272215wmc.38.2022.01.05.10.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 10:34:20 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v2 3/7] iio: adc: qcom-spmi-rradc: introduce round robin adc Date: Wed, 5 Jan 2022 18:33:49 +0000 Message-Id: <20220105183353.2505744-4-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Round Robin ADC is responsible for reading data about the rate of charge from the USB or DC in jacks, it can also read the battery ID (resistence) and some temperatures. It is found on the PMI8998 and PM660 Qualcomm PMICs. Signed-off-by: Caleb Connolly Reported-by: kernel test robot --- drivers/iio/adc/Kconfig | 13 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-rradc.c | 1070 +++++++++++++++++++++++++++++ 3 files changed, 1084 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-rradc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3363af15a43f..37f18ee4c4c5 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -812,6 +812,19 @@ config QCOM_PM8XXX_XOADC To compile this driver as a module, choose M here: the module will be called qcom-pm8xxx-xoadc. =20 +config QCOM_SPMI_RRADC + tristate "Qualcomm SPMI RRADC" + depends on MFD_SPMI_PMIC + help + This is for the PMIC Round Robin ADC driver. + + This driver exposes the battery ID resistor, battery thermal, PMIC die + temperature, charger USB in and DC in voltage and current. + + To compile this driver as a module, choose M here: the module will + be called qcom-qpmi-rradc. + + config QCOM_SPMI_IADC tristate "Qualcomm SPMI PMIC current ADC" depends on SPMI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d3f53549720c..ca8bad549175 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_NPCM_ADC) +=3D npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) +=3D palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) +=3D qcom-spmi-adc5.o obj-$(CONFIG_QCOM_SPMI_IADC) +=3D qcom-spmi-iadc.o +obj-$(CONFIG_QCOM_SPMI_RRADC) +=3D qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) +=3D qcom-vadc-common.o obj-$(CONFIG_QCOM_SPMI_VADC) +=3D qcom-spmi-vadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) +=3D qcom-pm8xxx-xoadc.o diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-= rradc.c new file mode 100644 index 000000000000..e5c3b249bc0f --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -0,0 +1,1070 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Linaro Limited. + * Author: Caleb Connolly + * + * This driver is for the Round Robin ADC found in the pmi8998 and pm660 P= MICs. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RR_ADC_EN_CTL 0x46 +#define RR_ADC_SKIN_TEMP_LSB 0x50 +#define RR_ADC_SKIN_TEMP_MSB 0x51 +#define RR_ADC_RR_ADC_CTL 0x52 +#define RR_ADC_ADC_CTL_CONTINUOUS_SEL BIT(3) +#define RR_ADC_ADC_LOG 0x53 +#define RR_ADC_ADC_LOG_CLR_CTRL BIT(0) + +#define RR_ADC_FAKE_BATT_LOW_LSB 0x58 +#define RR_ADC_FAKE_BATT_LOW_MSB 0x59 +#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A +#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B + +#define RR_ADC_BATT_ID_CTRL 0x60 +#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0) +#define RR_ADC_BATT_ID_TRIGGER 0x61 +#define RR_ADC_BATT_ID_STS 0x62 +#define RR_ADC_BATT_ID_CFG 0x63 +#define BATT_ID_SETTLE_MASK GENMASK(7, 5) +#define RR_ADC_BATT_ID_5_LSB 0x66 +#define RR_ADC_BATT_ID_5_MSB 0x67 +#define RR_ADC_BATT_ID_15_LSB 0x68 +#define RR_ADC_BATT_ID_15_MSB 0x69 +#define RR_ADC_BATT_ID_150_LSB 0x6A +#define RR_ADC_BATT_ID_150_MSB 0x6B + +#define RR_ADC_BATT_THERM_CTRL 0x70 +#define RR_ADC_BATT_THERM_TRIGGER 0x71 +#define RR_ADC_BATT_THERM_STS 0x72 +#define RR_ADC_BATT_THERM_CFG 0x73 +#define RR_ADC_BATT_THERM_LSB 0x74 +#define RR_ADC_BATT_THERM_MSB 0x75 +#define RR_ADC_BATT_THERM_FREQ 0x76 + +#define RR_ADC_AUX_THERM_CTRL 0x80 +#define RR_ADC_AUX_THERM_TRIGGER 0x81 +#define RR_ADC_AUX_THERM_STS 0x82 +#define RR_ADC_AUX_THERM_CFG 0x83 +#define RR_ADC_AUX_THERM_LSB 0x84 +#define RR_ADC_AUX_THERM_MSB 0x85 + +#define RR_ADC_SKIN_HOT 0x86 +#define RR_ADC_SKIN_TOO_HOT 0x87 + +#define RR_ADC_AUX_THERM_C1 0x88 +#define RR_ADC_AUX_THERM_C2 0x89 +#define RR_ADC_AUX_THERM_C3 0x8A +#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B + +#define RR_ADC_USB_IN_V_CTRL 0x90 +#define RR_ADC_USB_IN_V_TRIGGER 0x91 +#define RR_ADC_USB_IN_V_STS 0x92 +#define RR_ADC_USB_IN_V_LSB 0x94 +#define RR_ADC_USB_IN_V_MSB 0x95 +#define RR_ADC_USB_IN_I_CTRL 0x98 +#define RR_ADC_USB_IN_I_TRIGGER 0x99 +#define RR_ADC_USB_IN_I_STS 0x9A +#define RR_ADC_USB_IN_I_LSB 0x9C +#define RR_ADC_USB_IN_I_MSB 0x9D + +#define RR_ADC_DC_IN_V_CTRL 0xA0 +#define RR_ADC_DC_IN_V_TRIGGER 0xA1 +#define RR_ADC_DC_IN_V_STS 0xA2 +#define RR_ADC_DC_IN_V_LSB 0xA4 +#define RR_ADC_DC_IN_V_MSB 0xA5 +#define RR_ADC_DC_IN_I_CTRL 0xA8 +#define RR_ADC_DC_IN_I_TRIGGER 0xA9 +#define RR_ADC_DC_IN_I_STS 0xAA +#define RR_ADC_DC_IN_I_LSB 0xAC +#define RR_ADC_DC_IN_I_MSB 0xAD + +#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0 +#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1 +#define RR_ADC_PMI_DIE_TEMP_STS 0xB2 +#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3 +#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4 +#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5 + +#define RR_ADC_CHARGER_TEMP_CTRL 0xB8 +#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9 +#define RR_ADC_CHARGER_TEMP_STS 0xBA +#define RR_ADC_CHARGER_TEMP_CFG 0xBB +#define RR_ADC_CHARGER_TEMP_LSB 0xBC +#define RR_ADC_CHARGER_TEMP_MSB 0xBD +#define RR_ADC_CHARGER_HOT 0xBE +#define RR_ADC_CHARGER_TOO_HOT 0xBF + +#define RR_ADC_GPIO_CTRL 0xC0 +#define RR_ADC_GPIO_TRIGGER 0xC1 +#define RR_ADC_GPIO_STS 0xC2 +#define RR_ADC_GPIO_LSB 0xC4 +#define RR_ADC_GPIO_MSB 0xC5 + +#define RR_ADC_ATEST_CTRL 0xC8 +#define RR_ADC_ATEST_TRIGGER 0xC9 +#define RR_ADC_ATEST_STS 0xCA +#define RR_ADC_ATEST_LSB 0xCC +#define RR_ADC_ATEST_MSB 0xCD +#define RR_ADC_SEC_ACCESS 0xD0 + +#define RR_ADC_PERPH_RESET_CTL2 0xD9 +#define RR_ADC_PERPH_RESET_CTL3 0xDA +#define RR_ADC_PERPH_RESET_CTL4 0xDB +#define RR_ADC_INT_TEST1 0xE0 +#define RR_ADC_INT_TEST_VAL 0xE1 + +#define RR_ADC_TM_TRIGGER_CTRLS 0xE2 +#define RR_ADC_TM_ADC_CTRLS 0xE3 +#define RR_ADC_TM_CNL_CTRL 0xE4 +#define RR_ADC_TM_BATT_ID_CTRL 0xE5 +#define RR_ADC_TM_THERM_CTRL 0xE6 +#define RR_ADC_TM_CONV_STS 0xE7 +#define RR_ADC_TM_ADC_READ_LSB 0xE8 +#define RR_ADC_TM_ADC_READ_MSB 0xE9 +#define RR_ADC_TM_ATEST_MUX_1 0xEA +#define RR_ADC_TM_ATEST_MUX_2 0xEB +#define RR_ADC_TM_REFERENCES 0xED +#define RR_ADC_TM_MISC_CTL 0xEE +#define RR_ADC_TM_RR_CTRL 0xEF + +#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7) +#define RR_ADC_TRIGGER_CTL BIT(0) + +#define RR_ADC_BATT_ID_RANGE 820 + +#define RR_ADC_BITS 10 +#define RR_ADC_CHAN_MAX_VALUE (1 << RR_ADC_BITS) +#define RR_ADC_FS_VOLTAGE_MV 2500 + +/* BATT_THERM 0.25K/LSB */ +#define RR_ADC_BATT_THERM_LSB_K 4 + +#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000 +#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3 +#define RR_ADC_DIE_TEMP_OFFSET 601400 +#define RR_ADC_DIE_TEMP_SLOPE 2 +#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000 + +#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168 +#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 +#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433 +#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 +#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001 +#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403 +#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898 +#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596 +#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779 +#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496 +#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000 +#define RR_ADC_CHG_THRESHOLD_SCALE 4 + +#define RR_ADC_VOLT_INPUT_FACTOR 8 +#define RR_ADC_CURR_INPUT_FACTOR 2000 +#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886 +#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9 +#define RR_ADC_CURR_USBIN_660_UV_VAL 579500 + +#define RR_ADC_GPIO_FS_RANGE 5000 +#define RR_ADC_COHERENT_CHECK_RETRY 5 +#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16 + +#define RR_ADC_STS_CHANNEL_READING_MASK 0x3 +#define RR_ADC_STS_CHANNEL_STS 0x2 + +#define RR_ADC_TP_REV_VERSION1 21 +#define RR_ADC_TP_REV_VERSION2 29 +#define RR_ADC_TP_REV_VERSION3 32 + +#define RRADC_BATT_ID_DELAY_MAX 8 + +enum rradc_channel_id { + RR_ADC_BATT_ID =3D 0, + RR_ADC_BATT_THERM, + RR_ADC_SKIN_TEMP, + RR_ADC_USBIN_I, + RR_ADC_USBIN_V, + RR_ADC_DCIN_I, + RR_ADC_DCIN_V, + RR_ADC_DIE_TEMP, + RR_ADC_CHG_TEMP, + RR_ADC_GPIO, + RR_ADC_CHG_HOT_TEMP, + RR_ADC_CHG_TOO_HOT_TEMP, + RR_ADC_SKIN_HOT_TEMP, + RR_ADC_SKIN_TOO_HOT_TEMP, + RR_ADC_CHAN_MAX +}; + +struct rradc_chip; + +/** + * struct rradc_channel - rradc channel data + * @lsb: Channel least significant byte + * @status: Channel status address + * @size: number of bytes to read + * @trigger_addr: Trigger address, trigger is only used on some channels + * @trigger_mask: Trigger mask + * @scale: Channel scale callback + */ +struct rradc_channel { + u8 lsb; + u8 status; + int size; + int trigger_addr; + int trigger_mask; + int (*scale)(struct rradc_chip *chip, u16 adc_code, int *result); +}; + +struct rradc_chip { + struct device *dev; + struct qcom_spmi_pmic *pmic; + struct mutex lock; + struct regmap *regmap; + u32 base; + int batt_id_delay; + u16 batt_id_data; +}; + +static const int batt_id_delays[] =3D { 0, 1, 4, 12, 20, 40, 60, 80 }; +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; + +static int rradc_read(struct rradc_chip *chip, u16 addr, u8 *data, int len) +{ + int ret, retry_cnt =3D 0; + u8 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN]; + + if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) { + dev_err(chip->dev, + "Can't read more than %d bytes, but asked to read %d bytes.\n", + RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len); + return -EINVAL; + } + + while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) { + ret =3D regmap_bulk_read(chip->regmap, chip->base + addr, data, + len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + ret =3D regmap_bulk_read(chip->regmap, chip->base + addr, + data_check, len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + if (memcmp(data, data_check, len) !=3D 0) { + retry_cnt++; + dev_dbg(chip->dev, + "coherent read error, retry_cnt:%d\n", + retry_cnt); + continue; + } + + break; + } + + if (retry_cnt =3D=3D RR_ADC_COHERENT_CHECK_RETRY) + dev_err(chip->dev, "Retry exceeded for coherrency check\n"); + + return ret; +} + +static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, + int64_t *slope) +{ + if (chip->pmic->subtype =3D=3D PM660_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PM660_FAB_ID_GF: + *offset =3D RR_ADC_CHG_TEMP_660_GF_OFFSET_UV; + *slope =3D RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C; + break; + case PM660_FAB_ID_TSMC: + *offset =3D RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV; + *slope =3D RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C; + break; + default: + *offset =3D RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV; + *slope =3D RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C; + } + } else if (chip->pmic->subtype =3D=3D PMI8998_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PMI8998_FAB_ID_GF: + *offset =3D RR_ADC_CHG_TEMP_GF_OFFSET_UV; + *slope =3D RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C; + break; + case PMI8998_FAB_ID_SMIC: + *offset =3D RR_ADC_CHG_TEMP_SMIC_OFFSET_UV; + *slope =3D RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C; + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + + return 0; +} + +/* + * These functions explicitly cast int64_t to int. + * They will never overflow, as the values are small enough. + */ +static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_cod= e, + int *result_ohms) +{ + uint32_t current_value; + int64_t r_id; + + current_value =3D chip->batt_id_data; + r_id =3D ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV); + r_id =3D div64_s64(r_id, (RR_ADC_CHAN_MAX_VALUE * current_value)); + *result_ohms =3D (int)(r_id * MILLI); + + return 0; +} + +static int rradc_post_process_therm(struct rradc_chip *chip, u16 adc_code, + int *result_millidegc) +{ + int64_t temp; + + /* K =3D code/4 */ + temp =3D ((int64_t)adc_code * MILLI); + temp =3D div64_s64(temp, RR_ADC_BATT_THERM_LSB_K); + *result_millidegc =3D (int)milli_kelvin_to_millicelsius(temp); + + return 0; +} + +static int rradc_post_process_volt(struct rradc_chip *chip, u16 adc_code, + int *result_uv) +{ + int64_t uv; + + /* 8x input attenuation; 2.5V ADC full scale */ + uv =3D ((int64_t)adc_code * RR_ADC_VOLT_INPUT_FACTOR); + uv *=3D (RR_ADC_FS_VOLTAGE_MV * MILLI); + uv =3D div64_s64(uv, RR_ADC_CHAN_MAX_VALUE); + *result_uv =3D (int)uv; + + return 0; +} + +static int rradc_post_process_usbin_curr(struct rradc_chip *chip, u16 adc_= code, + int *result_ua) +{ + int64_t ua; + + /* scale * V/A; 2.5V ADC full scale */ + ua =3D ((int64_t)adc_code * RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL); + ua *=3D (RR_ADC_FS_VOLTAGE_MV * MILLI); + ua =3D div64_s64(ua, (RR_ADC_CHAN_MAX_VALUE * 10)); + *result_ua =3D (int)ua; + + return 0; +} + +static int rradc_post_process_dcin_curr(struct rradc_chip *chip, u16 adc_c= ode, + int *result_ua) +{ + int64_t ua; + + /* 0.5 V/A; 2.5V ADC full scale */ + ua =3D ((int64_t)adc_code * RR_ADC_CURR_INPUT_FACTOR); + ua *=3D (RR_ADC_FS_VOLTAGE_MV * MILLI); + ua =3D div64_s64(ua, (RR_ADC_CHAN_MAX_VALUE * 1000)); + *result_ua =3D (int)ua; + + return 0; +} + +static int rradc_post_process_die_temp(struct rradc_chip *chip, u16 adc_co= de, + int *result_millidegc) +{ + int64_t temp; + + temp =3D ((int64_t)adc_code * RR_ADC_TEMP_FS_VOLTAGE_NUM); + temp =3D div64_s64(temp, + (RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MAX_VALUE)); + temp -=3D RR_ADC_DIE_TEMP_OFFSET; + temp =3D div64_s64(temp, RR_ADC_DIE_TEMP_SLOPE); + temp +=3D RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC; + *result_millidegc =3D (int)temp; + + return 0; +} + +static int rradc_post_process_chg_temp_hot(struct rradc_chip *chip, + u16 adc_code, int *result_millidegc) +{ + int64_t uv, offset, slope; + int ret; + + ret =3D rradc_get_fab_coeff(chip, &offset, &slope); + if (ret < 0) { + dev_err(chip->dev, "Unable to get fab id coefficients\n"); + return -EINVAL; + } + + uv =3D (int64_t)adc_code * RR_ADC_CHG_THRESHOLD_SCALE; + uv =3D uv * RR_ADC_TEMP_FS_VOLTAGE_NUM; + uv =3D div64_s64(uv, + (RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MAX_VALUE)); + uv =3D offset - uv; + uv =3D div64_s64((uv * MILLI), slope); + uv =3D uv + RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC; + *result_millidegc =3D (int)uv; + + return 0; +} + +static int rradc_post_process_skin_temp_hot(struct rradc_chip *chip, + u16 adc_code, int *result_millidegc) +{ + int64_t temp; + + temp =3D (int64_t)adc_code; + temp =3D (div64_s64(temp, 2) - 30) * MILLI; + *result_millidegc =3D (int)temp; + + return 0; +} + +static int rradc_post_process_chg_temp(struct rradc_chip *chip, u16 adc_co= de, + int *result_millidegc) +{ + int64_t uv, offset, slope; + int ret; + + ret =3D rradc_get_fab_coeff(chip, &offset, &slope); + if (ret < 0) { + dev_err(chip->dev, "Unable to get fab id coefficients\n"); + return -EINVAL; + } + + uv =3D ((int64_t)adc_code * RR_ADC_TEMP_FS_VOLTAGE_NUM); + uv =3D div64_s64(uv, + (RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MAX_VALUE)); + uv =3D offset - uv; + uv =3D div64_s64((uv * MILLI), slope); + uv +=3D RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC; + *result_millidegc =3D (int)uv; + + return 0; +} + +static int rradc_post_process_gpio(struct rradc_chip *chip, u16 adc_code, + int *result_mv) +{ + int64_t mv; + + /* 5V ADC full scale, 10 bit */ + mv =3D ((int64_t)adc_code * RR_ADC_GPIO_FS_RANGE); + mv =3D div64_s64(mv, RR_ADC_CHAN_MAX_VALUE); + *result_mv =3D (int)mv; + + return 0; +} + +static int rradc_enable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Clear channel log */ + ret =3D regmap_update_bits(chip->regmap, chip->base + RR_ADC_ADC_LOG, + RR_ADC_ADC_LOG_CLR_CTRL, + RR_ADC_ADC_LOG_CLR_CTRL); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); + return ret; + } + + ret =3D regmap_update_bits(chip->regmap, chip->base + RR_ADC_ADC_LOG, + RR_ADC_ADC_LOG_CLR_CTRL, 0); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", + ret); + return ret; + } + + /* Switch to continuous mode */ + ret =3D regmap_update_bits(chip->regmap, chip->base + RR_ADC_RR_ADC_CTL, + RR_ADC_ADC_CTL_CONTINUOUS_SEL, + RR_ADC_ADC_CTL_CONTINUOUS_SEL); + if (ret < 0) + dev_err(chip->dev, "Update to continuous mode failed:%d\n", + ret); + + return ret; +} + +static int rradc_disable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Switch to non continuous mode */ + ret =3D regmap_update_bits(chip->regmap, chip->base + RR_ADC_RR_ADC_CTL, + RR_ADC_ADC_CTL_CONTINUOUS_SEL, 0); + if (ret < 0) + dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", + ret); + + return ret; +} + +static bool rradc_is_ready(struct rradc_chip *chip, + enum rradc_channel_id chan_id) +{ + const struct rradc_channel *chan =3D &rradc_chans[chan_id]; + int ret; + unsigned int status, mask; + + /* BATT_ID STS bit does not get set initially */ + switch (chan_id) { + case RR_ADC_BATT_ID: + mask =3D RR_ADC_STS_CHANNEL_STS; + break; + default: + mask =3D RR_ADC_STS_CHANNEL_READING_MASK; + break; + } + + ret =3D regmap_read(chip->regmap, chip->base + chan->status, &status); + if (ret < 0 || !(status & mask)) + return false; + + return true; +} + +static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, + enum rradc_channel_id chan_id) +{ + const struct rradc_channel *chan =3D &rradc_chans[chan_id]; + const struct iio_chan_spec *iio_chan =3D &rradc_iio_chans[chan_id]; + int ret; + + if (chan->trigger_mask =3D=3D 0) { + dev_err(chip->dev, "Channel doesn't have a trigger mask\n"); + return -EINVAL; + } + + ret =3D regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, chan->trigger_mask); + if (ret < 0) { + dev_err(chip->dev, + "Failed to apply trigger for channel '%s' ret=3D%d\n", + iio_chan->datasheet_name, ret); + return ret; + } + + ret =3D rradc_enable_continuous_mode(chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to switch to continuous mode\n"); + goto disable_trigger; + } + + if (!rradc_is_ready(chip, chan_id)) + dev_err(chip->dev, "channel '%s' is not ready\n", + iio_chan->datasheet_name); + + ret =3D rradc_disable_continuous_mode(chip); + if (ret < 0) + dev_err(chip->dev, "Failed to switch to non continuous mode\n"); + +disable_trigger: + ret =3D regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, 0); + if (ret < 0) + dev_err(chip->dev, + "Failed to apply trigger for channel '%s' ret=3D%d\n", + iio_chan->datasheet_name, ret); + + return ret; +} + +static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_id, + u16 *data) +{ + int ret, batt_id_delay; + + ret =3D regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); + if (ret < 0) { + dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); + return ret; + } + + if (chip->batt_id_delay !=3D -EINVAL) { + batt_id_delay =3D + FIELD_PREP(BATT_ID_SETTLE_MASK, chip->batt_id_delay); + ret =3D regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_CFG, + batt_id_delay, batt_id_delay); + if (ret < 0) { + dev_err(chip->dev, + "BATT_ID settling time config failed:%d\n", + ret); + goto out_disable_batt_id; + } + } + + ret =3D regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL); + if (ret < 0) { + dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); + goto out_disable_batt_id; + } + + ret =3D rradc_read_status_in_cont_mode(chip, chan_id); + if (ret < 0) + dev_err(chip->dev, "Error reading in continuous mode:%d\n", + ret); + + /* + * Reset registers back to default values + */ + ret =3D regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, 0); + if (ret < 0) + dev_err(chip->dev, "BATT_ID trigger re-set failed:%d\n", ret); + +out_disable_batt_id: + ret =3D regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0); + if (ret < 0) + dev_err(chip->dev, "Disabling BATT ID channel failed:%d\n", + ret); + + return ret; +} + +static int rradc_do_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_id, u16 *data) +{ + const struct rradc_channel *chan =3D &rradc_chans[chan_id]; + const struct iio_chan_spec *iio_chan =3D &rradc_iio_chans[chan_id]; + int ret; + u8 buf[6]; + + mutex_lock(&chip->lock); + + switch (chan_id) { + case RR_ADC_BATT_ID: + ret =3D rradc_prepare_batt_id_conversion(chip, chan_id, data); + if (ret < 0) { + dev_err(chip->dev, "Battery ID conversion failed:%d\n", + ret); + goto unlock_out; + } + break; + + case RR_ADC_USBIN_V: + case RR_ADC_DIE_TEMP: + ret =3D rradc_read_status_in_cont_mode(chip, chan_id); + if (ret < 0) { + dev_err(chip->dev, + "Error reading in continuous mode:%d\n", ret); + goto unlock_out; + } + break; + case RR_ADC_CHG_HOT_TEMP: + case RR_ADC_CHG_TOO_HOT_TEMP: + case RR_ADC_SKIN_HOT_TEMP: + case RR_ADC_SKIN_TOO_HOT_TEMP: + break; + default: + if (!rradc_is_ready(chip, chan_id)) { + /* + * Usually this means the channel isn't attached, for example + * the in_voltage_usbin_v_input channel will not be ready if + * no USB cable is attached + */ + dev_dbg(chip->dev, "channel '%s' is not ready\n", + iio_chan->datasheet_name); + ret =3D -ENODATA; + goto unlock_out; + } + break; + } + + ret =3D rradc_read(chip, chan->lsb, buf, chan->size); + if (ret) { + dev_err(chip->dev, "read data failed\n"); + goto unlock_out; + } + + /* + * For the battery ID we read the register for every ID ADC and then + * see which one is actually connected. + */ + if (chan_id =3D=3D RR_ADC_BATT_ID) { + u16 batt_id_150 =3D get_unaligned_le16(buf + 4); + u16 batt_id_15 =3D get_unaligned_le16(buf + 2); + u16 batt_id_5 =3D get_unaligned_le16(buf); + + if (!batt_id_150 && !batt_id_15 && !batt_id_5) { + dev_err(chip->dev, + "Invalid batt_id values with all zeros\n"); + ret =3D -EINVAL; + goto unlock_out; + } + + if (batt_id_150 <=3D RR_ADC_BATT_ID_RANGE) { + *data =3D batt_id_150; + chip->batt_id_data =3D 150; + } else if (batt_id_15 <=3D RR_ADC_BATT_ID_RANGE) { + *data =3D batt_id_15; + chip->batt_id_data =3D 15; + } else { + *data =3D batt_id_5; + chip->batt_id_data =3D 5; + } + } else { + /* + * All of the other channels are either 1 or 2 bytes. + * We can rely on the second byte being 0 for 1-byte channels. + */ + *data =3D get_unaligned_le16(buf); + } + +unlock_out: + mutex_unlock(&chip->lock); + + return ret; +} + +static int rradc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan_spec, int *val, + int *val2, long mask) +{ + struct rradc_chip *chip =3D iio_priv(indio_dev); + const struct rradc_channel *chan; + int ret; + u16 adc_code; + + if (chan_spec->address >=3D RR_ADC_CHAN_MAX) { + dev_err(chip->dev, "Invalid channel index:%ld\n", + chan_spec->address); + return -EINVAL; + } + + chan =3D &rradc_chans[chan_spec->address]; + ret =3D rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + *val =3D adc_code; + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + chan->scale(chip, adc_code, val); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static const struct iio_info rradc_info =3D { + .read_raw =3D &rradc_read_raw, +}; + +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] =3D { + { + .scale =3D rradc_post_process_batt_id, + .lsb =3D RR_ADC_BATT_ID_5_LSB, + .status =3D RR_ADC_BATT_ID_STS, + .size =3D 6, + .trigger_addr =3D RR_ADC_BATT_ID_TRIGGER, + .trigger_mask =3D BIT(0), + }, + { + .scale =3D rradc_post_process_therm, + .lsb =3D RR_ADC_BATT_THERM_LSB, + .status =3D RR_ADC_BATT_THERM_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_BATT_THERM_TRIGGER, + }, + { + .scale =3D rradc_post_process_therm, + .lsb =3D RR_ADC_SKIN_TEMP_LSB, + .status =3D RR_ADC_AUX_THERM_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_AUX_THERM_TRIGGER, + }, + { + .scale =3D rradc_post_process_usbin_curr, + .lsb =3D RR_ADC_USB_IN_I_LSB, + .status =3D RR_ADC_USB_IN_I_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_USB_IN_I_TRIGGER, + }, + { + .scale =3D rradc_post_process_volt, + .lsb =3D RR_ADC_USB_IN_V_LSB, + .status =3D RR_ADC_USB_IN_V_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_USB_IN_V_TRIGGER, + .trigger_mask =3D BIT(7), + }, + { + .scale =3D rradc_post_process_dcin_curr, + .lsb =3D RR_ADC_DC_IN_I_LSB, + .status =3D RR_ADC_DC_IN_I_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_DC_IN_I_TRIGGER, + }, + { + .scale =3D rradc_post_process_volt, + .lsb =3D RR_ADC_DC_IN_V_LSB, + .status =3D RR_ADC_DC_IN_V_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_DC_IN_V_TRIGGER, + }, + { + .scale =3D rradc_post_process_die_temp, + .lsb =3D RR_ADC_PMI_DIE_TEMP_LSB, + .status =3D RR_ADC_PMI_DIE_TEMP_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_PMI_DIE_TEMP_TRIGGER, + .trigger_mask =3D RR_ADC_TRIGGER_EVERY_CYCLE, + }, + { + .scale =3D rradc_post_process_chg_temp, + .lsb =3D RR_ADC_CHARGER_TEMP_LSB, + .status =3D RR_ADC_CHARGER_TEMP_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_CHARGER_TEMP_TRIGGER, + }, + { + .scale =3D rradc_post_process_gpio, + .lsb =3D RR_ADC_GPIO_LSB, + .status =3D RR_ADC_GPIO_STS, + .size =3D 2, + .trigger_addr =3D RR_ADC_GPIO_TRIGGER, + }, + { + .scale =3D rradc_post_process_chg_temp_hot, + .lsb =3D RR_ADC_CHARGER_HOT, + .status =3D RR_ADC_CHARGER_TEMP_STS, + .size =3D 1, + .trigger_addr =3D RR_ADC_CHARGER_TEMP_TRIGGER, + }, + { + .scale =3D rradc_post_process_chg_temp_hot, + .lsb =3D RR_ADC_CHARGER_TOO_HOT, + .status =3D RR_ADC_CHARGER_TEMP_STS, + .size =3D 1, + .trigger_addr =3D RR_ADC_CHARGER_TEMP_TRIGGER, + }, + { + .scale =3D rradc_post_process_skin_temp_hot, + .lsb =3D RR_ADC_SKIN_HOT, + .status =3D RR_ADC_AUX_THERM_STS, + .size =3D 1, + .trigger_addr =3D RR_ADC_AUX_THERM_TRIGGER, + }, + { + .scale =3D rradc_post_process_skin_temp_hot, + .lsb =3D RR_ADC_SKIN_TOO_HOT, + .status =3D RR_ADC_AUX_THERM_STS, + .size =3D 1, + .trigger_addr =3D RR_ADC_AUX_THERM_TRIGGER, + }, +}; + +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] =3D { + { + .datasheet_name =3D "batt_id", + .type =3D IIO_RESISTANCE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED), + .address =3D RR_ADC_BATT_ID, + }, + { + .datasheet_name =3D "batt_therm", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_BATT_THERM, + }, + { + .datasheet_name =3D "skin_temp", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_SKIN_TEMP, + }, + { + .datasheet_name =3D "usbin_i", + .type =3D IIO_CURRENT, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED), + .address =3D RR_ADC_USBIN_I, + }, + { + .datasheet_name =3D "usbin_v", + .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED), + .address =3D RR_ADC_USBIN_V, + }, + { + .datasheet_name =3D "dcin_i", + .type =3D IIO_CURRENT, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED), + .address =3D RR_ADC_DCIN_I, + }, + { + .datasheet_name =3D "dcin_v", + .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED), + .address =3D RR_ADC_DCIN_V, + }, + { + .datasheet_name =3D "die_temp", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_DIE_TEMP, + }, + { + .datasheet_name =3D "chg_temp", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_CHG_TEMP, + }, + { + .datasheet_name =3D "gpio", + .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_GPIO, + }, + { + .datasheet_name =3D "chg_temp_hot", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_CHG_HOT_TEMP, + }, + { + .datasheet_name =3D "chg_temp_too_hot", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_CHG_TOO_HOT_TEMP, + }, + { + .datasheet_name =3D "skin_temp_hot", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_SKIN_TEMP, + }, + { + .datasheet_name =3D "skin_temp_too_hot", + .type =3D IIO_TEMP, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PROCESSED)| + BIT(IIO_CHAN_INFO_RAW), + .address =3D RR_ADC_SKIN_TEMP, + }, +}; + +static int rradc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct iio_dev *indio_dev; + struct rradc_chip *chip; + int ret, i; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*chip)); + if (!indio_dev) + return -ENOMEM; + + chip =3D iio_priv(indio_dev); + chip->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + dev_err(dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + chip->dev =3D dev; + mutex_init(&chip->lock); + + ret =3D device_property_read_u32(dev, "reg", &chip->base); + if (ret < 0) { + dev_err(chip->dev, "Couldn't find reg address, ret =3D %d\n", + ret); + return ret; + } + + chip->batt_id_delay =3D -EINVAL; + ret =3D device_property_read_u32(dev, "qcom,batt-id-delay-ms", + &chip->batt_id_delay); + if (!ret) { + for (i =3D 0; i < RRADC_BATT_ID_DELAY_MAX; i++) { + if (chip->batt_id_delay =3D=3D batt_id_delays[i]) + break; + } + if (i =3D=3D RRADC_BATT_ID_DELAY_MAX) + chip->batt_id_delay =3D -EINVAL; + } + + /* Get the PMIC revision ID, we need to handle some varying coefficients = */ + chip->pmic =3D (struct qcom_spmi_pmic *)spmi_device_get_drvdata( + to_spmi_device(pdev->dev.parent)); + qcom_pmic_print_info(chip->dev, chip->pmic); + + indio_dev->name =3D pdev->name; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->info =3D &rradc_info; + indio_dev->channels =3D rradc_iio_chans; + indio_dev->num_channels =3D RR_ADC_CHAN_MAX; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rradc_match_table[] =3D { + { .compatible =3D "qcom,pm660-rradc" }, + { .compatible =3D "qcom,pmi8998-rradc" }, + {} +}; +MODULE_DEVICE_TABLE(of, rradc_match_table); + +static struct platform_driver rradc_driver =3D { + .driver =3D { + .name =3D "qcom-rradc", + .of_match_table =3D rradc_match_table, + }, + .probe =3D rradc_probe, +}; +module_platform_driver(rradc_driver); + +MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver"); +MODULE_AUTHOR("Caleb Connolly "); +MODULE_LICENSE("GPL v2"); --=20 2.34.1 From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26C72C433EF for ; Wed, 5 Jan 2022 18:36:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243097AbiAESee (ORCPT ); Wed, 5 Jan 2022 13:34:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id 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o1sm3272215wmc.38.2022.01.05.10.34.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 10:34:21 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v2 4/7] arm64: dts: qcom: pmi8998: add rradc node Date: Wed, 5 Jan 2022 18:33:50 +0000 Message-Id: <20220105183353.2505744-5-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a DT node for the Round Robin ADC found in the PMI8998 PMIC. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qc= om/pmi8998.dtsi index 0fef5f113f05..da10668c361d 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -18,6 +18,14 @@ pmi8998_gpio: gpios@c000 { interrupt-controller; #interrupt-cells =3D <2>; }; + + pmi8998_rradc: rradc@4500 { + compatible =3D "qcom,pmi8998-rradc"; + reg =3D <0x4500>; + #io-channel-cells =3D <1>; + + status =3D "disabled"; + }; }; =20 pmi8998_lsid1: pmic@3 { --=20 2.34.1 From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C9EC433F5 for ; Wed, 5 Jan 2022 18:34:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243128AbiAESes (ORCPT ); Wed, 5 Jan 2022 13:34:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243055AbiAESeZ (ORCPT ); Wed, 5 Jan 2022 13:34:25 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE8A3C0611FF for ; Wed, 5 Jan 2022 10:34:24 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id q8so4267323wra.12 for ; Wed, 05 Jan 2022 10:34:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6owdUrWnsMJbv4dtPOTN1GhRqLZCzET0ZErU0fw/VVw=; b=umyUYyPj8Y8dGWViGQ53lLOC1QgwFrSDaCbaCBHetou6It3/5RZzFXGgS/2MGb1/ke lAGl5C4vkr5el7oFdBXMQ2BFIq3GFcOotddpplp26eaICa7yi2DPzDXuhV4G/lbdSlGy 2aGOY95iyaV4GStJLekVb3u3Lg1n6LreebBEthtB8YpRESs8/MkQ1+gyYOW5eK1mdwxC LkZ5ADQzDUbW0cFUbW7kT4OBkNRY/y2sZOun7Uai4j3UzFl0Otetrvn+C4M0NPfw5RgB AqRr6Rkehvs4uXq14WpZmPQ0iQ32Ob4eMoCzvYh6bfnmTQDaFxQzdr1J8orNeSSqfgPk H4AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6owdUrWnsMJbv4dtPOTN1GhRqLZCzET0ZErU0fw/VVw=; b=GdZTuUZ7XaBQJGPm5E0n1NFdFoqFDFZGNNqTiqI6DWMJHIct3Tlxlp7SiCYimNIM2I 0lTHpyR94qhyiGQHQx6wdLHsiszGT4LgPSUKiCRD4JCJdKvChmEMV8pz+BLNqXFX5Htr R63UUvpY+835xYm/At5jlv355N9S1KSwV32HCk02L7gEvqtczJqkp6vvsuTEm7gWm0/j vGSkzW3xEOXVQor1/WnylThy52EHVybMQDJObtlJZCr+QVOuh8n+JjLIN+3Ut+5dbbiM efOz33lCRBkJ9qrh55Dvd9FreM9U7KYgWhM2vmNUFrtSNWWRggeZ4FHECzoUXRnXpnyi V90Q== X-Gm-Message-State: AOAM533D7a+uvyPfQZVIZUJ00ldwdnEmIcbBR8A2H+9380ATog8zmzQR 6F/sKT1bb70GpVeHUruBOKvuHrdKmphtxg== X-Google-Smtp-Source: ABdhPJyxfDPsbnxdNzdjwnjvGaaXfGJUwL/J85bz0M2Bs9NvtNlOzt0qitd4HXxs0OakcL+q2ZpagA== X-Received: by 2002:a5d:4c48:: with SMTP id n8mr47008816wrt.25.1641407663486; Wed, 05 Jan 2022 10:34:23 -0800 (PST) Received: from localhost.localdomain ([81.178.195.252]) by smtp.gmail.com with ESMTPSA id o1sm3272215wmc.38.2022.01.05.10.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 10:34:22 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v2 5/7] arm64: dts: qcom: sdm845-oneplus: enable rradc Date: Wed, 5 Jan 2022 18:33:51 +0000 Message-Id: <20220105183353.2505744-6-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the RRADC for the OnePlus 6. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm= 64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 3e04aeb479d1..9feda49b2f12 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -450,6 +450,10 @@ pinconf { }; }; =20 +&pmi8998_rradc { + status =3D "okay"; +}; + &qupv3_id_1 { status =3D "okay"; }; --=20 2.34.1 From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B0F0C433EF for ; Wed, 5 Jan 2022 18:34:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243148AbiAESey (ORCPT ); Wed, 5 Jan 2022 13:34:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243063AbiAESe0 (ORCPT ); Wed, 5 Jan 2022 13:34:26 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B57B3C061245 for ; Wed, 5 Jan 2022 10:34:25 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id r17so62891wrc.3 for ; Wed, 05 Jan 2022 10:34:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W8/SX4B6pGqMw5D9hjNeLzM7aFQMvNtbchzA9WgHZ3g=; b=JYkdxgfDavEn2IJ/YM8Q3lfDES0NrdxCExHLploLBfxnYWwtuUh8SR2J9Ns3MyAOCV XA53Zua7Ifz3lQXw06XmeBsYoNPPOtjHk043syVShRw5uZvjKtD1YvIOySXLZotWNJto 0gkzrRK7N8lAMTeWEtjzOS1+MBrpvOGRp8vu84UkishUchCWxOsC4QW/zKrXu9JXUhvF ipaL4oAeQ51z19Gt38+zrBdPaMLoqU6ZliBwSqGkqcYkrOpJn4qQKmJKXGDFZT/tv3p8 mLb1EnCmAEIcyCKm8jmDtNMTImGq5XdlnFrRPgGFR1b4m701fDl2Sgm2qZ9zgBuHcfr9 fr9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W8/SX4B6pGqMw5D9hjNeLzM7aFQMvNtbchzA9WgHZ3g=; b=PLc97bdCUmFLf789/zMCEkuQ4D1Zm4hU73hwB73+bPxKS3bLb7ZvgQrdHso7g2ayvf Tx7sskZd21Exwe3casuzSrvYOVxqfbOBlu2mg83ODBWYPY4auDhnLpkp4NNrmS2Ocgjl k4DtKc8g2ltMXBPceO/69Drm4e53MKOYShC+vJYP5Cq78lS5/XL2gZdJJ4JT7cujXbuP bPDppQVx2Y8Gq7l0ihAaM/QMNoSXCikdipqdSR0T1tDLyH8qzOV1rCid6e4Znk99G3Z9 OR2v4hyyNMdwsNhF/XcPQaIhvaD9MWhKK5TeWIbuR8FhfsAYXoajM8JUO9vby1+TaGMJ rrtw== X-Gm-Message-State: AOAM531nQ1py4Ugkm3WN6mAKveWorqAX7iXEKaKMiXhi/+wRbjGtIEIU ZaurS3Rr1opTRdlBc/3cdqU/SA== X-Google-Smtp-Source: ABdhPJw9AveyAGyJLsI9/c1D+tYG8QKmHLy8rrrqHIrpJ6Ff8Ed5ewFy8XHvr8XWiChuxRFa3umuUw== X-Received: by 2002:a05:6000:144a:: with SMTP id v10mr47100170wrx.357.1641407664405; Wed, 05 Jan 2022 10:34:24 -0800 (PST) Received: from localhost.localdomain ([81.178.195.252]) by smtp.gmail.com with ESMTPSA id o1sm3272215wmc.38.2022.01.05.10.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 10:34:24 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v2 6/7] arm64: dts: qcom: sdm845-db845c: enable rradc Date: Wed, 5 Jan 2022 18:33:52 +0000 Message-Id: <20220105183353.2505744-7-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the Round Robin ADC for the db845c. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/d= ts/qcom/sdm845-db845c.dts index 13f80a0b6faa..1c452b458121 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -595,6 +595,10 @@ resin { }; }; =20 +&pmi8998_rradc { + status =3D "okay"; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@22 { --=20 2.34.1 From nobody Wed Jul 1 00:48:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 487C1C433EF for ; Wed, 5 Jan 2022 18:35:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243122AbiAESe6 (ORCPT ); Wed, 5 Jan 2022 13:34:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243071AbiAESe1 (ORCPT ); Wed, 5 Jan 2022 13:34:27 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB020C034002 for ; Wed, 5 Jan 2022 10:34:26 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id n19-20020a7bc5d3000000b003466ef16375so2451182wmk.1 for ; Wed, 05 Jan 2022 10:34:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2VD8BhFQsi1gAqizHlVU3fMYSmPUmL03WAYruvW0snE=; b=jpVf08kdAsBCv9Fz1w8bfk9PWLBPKBl9jzBJsjlc/B4Uw7dDo0HJSxclDVckHXkeD3 Ed89gG+Jy8B1f91gnAnK6RzuZLwz0ZhG81vZtGMNGWsSxWZUQ5u4S47VBWtdSdemKV+7 RwswXCHkcHRQYKVEI4zbckjsWmLTHwE/KAenkOaaOe0r1lJjjyvYbTNZWONLAks9O8Lt 4uGuc0gatO2kVE6unROXpwzYYmXIGOePVlp4CtzONKWd93tjEamYaKBTH2MmHPohAaA9 qCQ5AWZJlIhH3Jm0eJFA5tWi54zYiHkUoBXtom4WrMPFzCYjWC0WFN+RnCe6ksonxx0t vJag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2VD8BhFQsi1gAqizHlVU3fMYSmPUmL03WAYruvW0snE=; b=aedtvJxneDUB7uU4Gr/sc5z21ws5MSvrnAfZ+WaACjzWoVcTnOQGZqsDDCN6wGhsqY W12INugNnDtCvU+pZdg8d9FEk329xD3RjgRNyqbdJBtKX5BThIrmNM1lU42I1Yy6Bzfp 5d7l8khR6456NELQiKgtNcNFxo10TV5hhuPAZ8A+h510UDjza2K2CNA+E6X4winRqPvu 6W6MIDqbg/YTxbcfDVclPHHk+SRyqxlYgKWEhG3lQqxWUr5DG11kM4SMTm4i4XexFzfm goGQ39onEv88L/DW1PGGstLgiP2Om1r08/23r3u/UEVjrLZogLkqvMvR7zoHo5FPQHRc iw5g== X-Gm-Message-State: AOAM532QpVSpsmWfQkXlatWMZczpNc8xE5S42jDnlV+6gneH4IMPVFoP gaF/8zlC7qaIXUJnY/vYA/WZOA== X-Google-Smtp-Source: ABdhPJy+Q4ONifaTzqm79p0+0JVlKoXxb6uoAj5vX4aBkr8L4Bh2cHFh9pPBz3ji3n1eSLAiTW/vWA== X-Received: by 2002:a05:600c:4013:: with SMTP id i19mr3986331wmm.93.1641407665309; Wed, 05 Jan 2022 10:34:25 -0800 (PST) Received: from localhost.localdomain ([81.178.195.252]) by smtp.gmail.com with ESMTPSA id o1sm3272215wmc.38.2022.01.05.10.34.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 10:34:24 -0800 (PST) From: Caleb Connolly To: caleb.connolly@linaro.org, Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Andy Gross , Bjorn Andersson , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: sumit.semwal@linaro.org, amit.pundir@linaro.org, john.stultz@linaro.org Subject: [PATCH v2 7/7] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable RRADC Date: Wed, 5 Jan 2022 18:33:53 +0000 Message-Id: <20220105183353.2505744-8-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org> References: <20220105183353.2505744-1-caleb.connolly@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the PMI8998 RRADC. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/ar= m64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 580d4cc1296f..481132b0cee4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -312,6 +312,10 @@ resin { }; }; =20 +&pmi8998_rradc { + status =3D "okay"; +}; + /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { qi2s@22 { --=20 2.34.1