From nobody Wed Jul 1 00:48:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0031FC433F5 for ; Wed, 5 Jan 2022 13:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240540AbiAEN7F (ORCPT ); Wed, 5 Jan 2022 08:59:05 -0500 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:44974 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240478AbiAEN6u (ORCPT ); Wed, 5 Jan 2022 08:58:50 -0500 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 205DHUen029809; Wed, 5 Jan 2022 14:58:26 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=oH/k3L/zHYjRhWULeyfOFzDpOyHRsZOdenKG7F1vMq4=; b=SckFupL3jRlwRIAl4L96oWF3Yct3QV01MlLt/azcm6RDQ0PbsAmtjGznExILmHaC/CW/ l/SoySmuk+7IGOvB9n5TPVbxVmBDg7lNpOjdzTh7QlOmglYJGqvcd3Dc6GWWBDQ8DiF2 fL+kQYXTFr6bdEsBtYRENqKKsSzAWan/hz949jaF2AZkejLIddtt9/bD4hNzKrMET1gq /kcSa6+310sAmXjlENxOi5B8uB/4PDCR0J5kYEQVmOLSdxCVwXyDurfub8jpgNkoo5uV wv+XnS600ScMFkmfju1XSGr+4SMICfiFC1C8+6jol5OkvZzMYJo2jFiZOUz8kYL3jhbl Dw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dd7k91mc3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Jan 2022 14:58:26 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A781310002A; Wed, 5 Jan 2022 14:58:25 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9E2F624D5F2; Wed, 5 Jan 2022 14:58:25 +0100 (CET) Received: from localhost (10.75.127.44) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 5 Jan 2022 14:58:24 +0100 From: Christophe Kerello To: , , , , CC: , , , , , Christophe Kerello Subject: [PATCH 1/3] dt-binding: mtd: nand: Document the wp-gpios property Date: Wed, 5 Jan 2022 14:57:32 +0100 Message-ID: <20220105135734.271313-2-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105135734.271313-1-christophe.kerello@foss.st.com> References: <20220105135734.271313-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-05_03,2022-01-04_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" A few drivers use this property to describe the GPIO pin used to protect the NAND during program/erase operations. Signed-off-by: Christophe Kerello Acked-by: Rob Herring --- Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/D= ocumentation/devicetree/bindings/mtd/nand-controller.yaml index bd217e6f5018..53b21aed0ac5 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -154,6 +154,13 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. =20 + wp-gpios: + description: + Contains one GPIO descriptor for the Write Protect pin. + Active state refers to the NAND Write Protect state and should be + set to GPIOD_ACTIVE_LOW unless the signal is inverted. + maxItems: 1 + secure-regions: $ref: /schemas/types.yaml#/definitions/uint64-matrix description: --=20 2.25.1 From nobody Wed Jul 1 00:48:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 216BEC433F5 for ; Wed, 5 Jan 2022 13:59:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240509AbiAEN65 (ORCPT ); Wed, 5 Jan 2022 08:58:57 -0500 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:44958 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240477AbiAEN6t (ORCPT ); Wed, 5 Jan 2022 08:58:49 -0500 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 205DZ65I029790; Wed, 5 Jan 2022 14:58:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=vJYKJrfoZTOxidHtgmggToIXf7luT4gK50tpphfihR8=; b=iDQ7JsyMZ+Di+15I2+AGXfp/O7Qf/wD9cBgZhtVJ3+S5zAzYLO4HYCCtJ2x5uMz9JY1a FDOVtCXYT6IjwOHInxb+xq7ok9vWJd6wD/UthA7KtCInFUPm96L+pL/kuVY1XAulec6l 0VBkwNyG+iT6P/wh2AAH7/9TJ5ZYibSihkaZAq7Fbzmh5zIeJAQp6RRh/eYIbEF1bzKe n4hgM27Uk35SXUiDIFgRGL2Tk5QvGVJhMPwCPXDxUK9/MZiTUNT8/40aVwrm3AenrkCy HxohIwADFX+DG0mv1p8WdEJsm6QBFxReO01coFNR/NfNeDznkLqr/6KXWCXtNeebiVLb TA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dd7k91mce-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Jan 2022 14:58:32 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B42710002A; Wed, 5 Jan 2022 14:58:32 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 22B6D24D5F4; Wed, 5 Jan 2022 14:58:32 +0100 (CET) Received: from localhost (10.75.127.46) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 5 Jan 2022 14:58:31 +0100 From: Christophe Kerello To: , , , , CC: , , , , , Christophe Kerello Subject: [PATCH 2/3] mtd: rawnand: stm32_fmc2: Add NAND Write Protect support Date: Wed, 5 Jan 2022 14:57:33 +0100 Message-ID: <20220105135734.271313-3-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105135734.271313-1-christophe.kerello@foss.st.com> References: <20220105135734.271313-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-05_03,2022-01-04_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds the support of the WP# signal. WP will be disabled in probe/resume callbacks and will be enabled in remove/suspend callbacks. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 40 +++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index 97b4e02e43e4..87c1c7dd97eb 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,7 @@ struct stm32_fmc2_timings { =20 struct stm32_fmc2_nand { struct nand_chip chip; + struct gpio_desc *wp_gpio; struct stm32_fmc2_timings timings; int ncs; int cs_used[FMC2_MAX_CE]; @@ -1747,6 +1749,18 @@ static const struct nand_controller_ops stm32_fmc2_n= fc_controller_ops =3D { .setup_interface =3D stm32_fmc2_nfc_setup_interface, }; =20 +static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand) +{ + if (nand->wp_gpio) + gpiod_set_value(nand->wp_gpio, 1); +} + +static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand) +{ + if (nand->wp_gpio) + gpiod_set_value(nand->wp_gpio, 0); +} + static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, struct device_node *dn) { @@ -1785,6 +1799,18 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_f= mc2_nfc *nfc, nand->cs_used[i] =3D cs; } =20 + nand->wp_gpio =3D devm_gpiod_get_from_of_node(nfc->dev, dn, + "wp-gpios", 0, + GPIOD_OUT_HIGH, "wp"); + if (IS_ERR(nand->wp_gpio)) { + ret =3D PTR_ERR(nand->wp_gpio); + if (ret !=3D -ENOENT) + return dev_err_probe(nfc->dev, ret, + "failed to request WP GPIO\n"); + + nand->wp_gpio =3D NULL; + } + nand_set_flash_node(&nand->chip, dn); =20 return 0; @@ -1956,10 +1982,12 @@ static int stm32_fmc2_nfc_probe(struct platform_dev= ice *pdev) chip->options |=3D NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA; =20 + stm32_fmc2_nfc_wp_disable(nand); + /* Scan to find existence of the device */ ret =3D nand_scan(chip, nand->ncs); if (ret) - goto err_release_dma; + goto err_wp_enable; =20 ret =3D mtd_device_register(mtd, NULL, 0); if (ret) @@ -1972,6 +2000,9 @@ static int stm32_fmc2_nfc_probe(struct platform_devic= e *pdev) err_nand_cleanup: nand_cleanup(chip); =20 +err_wp_enable: + stm32_fmc2_nfc_wp_enable(nand); + err_release_dma: if (nfc->dma_ecc_ch) dma_release_channel(nfc->dma_ecc_ch); @@ -2012,15 +2043,20 @@ static int stm32_fmc2_nfc_remove(struct platform_de= vice *pdev) =20 clk_disable_unprepare(nfc->clk); =20 + stm32_fmc2_nfc_wp_enable(nand); + return 0; } =20 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev) { struct stm32_fmc2_nfc *nfc =3D dev_get_drvdata(dev); + struct stm32_fmc2_nand *nand =3D &nfc->nand; =20 clk_disable_unprepare(nfc->clk); =20 + stm32_fmc2_nfc_wp_enable(nand); + pinctrl_pm_select_sleep_state(dev); =20 return 0; @@ -2042,6 +2078,8 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struc= t device *dev) =20 stm32_fmc2_nfc_init(nfc); =20 + stm32_fmc2_nfc_wp_disable(nand); + for (chip_cs =3D 0; chip_cs < FMC2_MAX_CE; chip_cs++) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; --=20 2.25.1 From nobody Wed Jul 1 00:48:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EA02C433EF for ; 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Wed, 05 Jan 2022 14:58:36 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 519A8100034; Wed, 5 Jan 2022 14:58:35 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4918524D5F4; Wed, 5 Jan 2022 14:58:35 +0100 (CET) Received: from localhost (10.75.127.47) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 5 Jan 2022 14:58:34 +0100 From: Christophe Kerello To: , , , , CC: , , , , , Christophe Kerello Subject: [PATCH 3/3] nvmem: core: Fix a conflict between MTD and NVMEM on wp-gpios property Date: Wed, 5 Jan 2022 14:57:34 +0100 Message-ID: <20220105135734.271313-4-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105135734.271313-1-christophe.kerello@foss.st.com> References: <20220105135734.271313-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-05_03,2022-01-04_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wp-gpios property can be used on NVMEN nodes and the same property can be also used on MTD NAND nodes. In case of the wp-gpios property is defined at NAND level node, the GPIO management is done at NAND driver level. Write protect is disabled when the driver is probed or resumed and is enabled when the driver is released or suspended. When no partitions are defined in the NAND DT node, then the NAND DT node will be passed to NVMEM framework. If wp-gpios property is defined in this node, the GPIO resource is taken twice and the NAND controller driver fails to probe. It would be possible to set config->wp_gpio at MTD level before calling nvmem_register function but NVMEM framework will toggled this GPIO on each write when this GPIO should only be controlled at NAND level driver to ensure that the Write Protect has not been enabled. As MTD framework is only using NVMEN framework in read only, a way to fix this conflict is to get the GPIO resource at NVMEM level only if reg_write API is defined. This GPIO is only toggled if reg_write ops is defined. Signed-off-by: Christophe Kerello --- drivers/nvmem/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index e765d3d0542e..e11c74db64f9 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -769,7 +769,7 @@ struct nvmem_device *nvmem_register(const struct nvmem_= config *config) =20 if (config->wp_gpio) nvmem->wp_gpio =3D config->wp_gpio; - else + else if (config->reg_write) nvmem->wp_gpio =3D gpiod_get_optional(config->dev, "wp", GPIOD_OUT_HIGH); if (IS_ERR(nvmem->wp_gpio)) { --=20 2.25.1