From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85B25C433FE for ; Tue, 4 Jan 2022 19:49:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231450AbiADTta (ORCPT ); Tue, 4 Jan 2022 14:49:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231409AbiADTt3 (ORCPT ); Tue, 4 Jan 2022 14:49:29 -0500 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E5DEC061785 for ; Tue, 4 Jan 2022 11:49:29 -0800 (PST) Received: by mail-pj1-x104a.google.com with SMTP id d3-20020a17090a2a4300b001b22191073dso368114pjg.4 for ; Tue, 04 Jan 2022 11:49:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=A6x6Pw7kLwqSVAYV5QWuRkaeBaCvukF54j0t8jOjIWo=; b=ptX0vg9YdIJXEIv+bPi9miN6Phs8Gqz7sBU2QWQsUtqw2kQGQwiABtW992ywk4hZ+W 0Yjxd+YrHiAZDx5j9yYFCFkPbsVaZ0Me2jeZ8/Yp1nLtpTRU3glZ/AFWrivJ3Ne9PxOZ wEEkRcAX+0GHmJL3/IL+wNt/VFmeQ8X8mW6bJyPiNxpnLVbR0aLEbdEA2Ze9gi6qqQ3C poU1KuO3mU1pkPlTHi2tto1rMBI3uHO8ySMfK3Luj4uIlnnCmLez6qNGPpgKaKGbE9tx WkPLsVqsmNEpEEThs9CKJ8Tw+DYsrLXtA1p0adzY5K5eZnk7V3wXfESrD7ST2e9CTHW1 RFAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=A6x6Pw7kLwqSVAYV5QWuRkaeBaCvukF54j0t8jOjIWo=; b=l2/SEkQStjmEcZoRmbkqDxRPOpeCvU7eUDM3uPualfu56nV1/wSdjebKj1ahMZ90Es XFFP3qkJs7IFqBFkLNHwV0DcLMAN+rnjXCqxUC47ddlYMctO9g/SEUGQhrEbhrJSY9Jg eMO41XGqVNxKzcLDl3qSk/uoH43P+UgQR/BVs9zlNGgu8UH5idrg4YgunnpIKWMICa9p a/ycsumJ7mJm6oQ2OA3m8mNHMCFxskFJoooUqRz0vnAXdsTqd7aOMCQkdEnBjeNDpW8f KCj1/5NKiW0z2Z2sLrluPONclBoLpu+0ftUOLcqitcMY++7eJHNM2f0PpPev9HfqfNQe u0MA== X-Gm-Message-State: AOAM531AtndSlPURb6JtTaA9tp+akP457bmL+xUrdqx+lP0r8Y+AWQp3 LCCvGFOT4cvu3dyAVIfuuq87jq8Hsu71 X-Google-Smtp-Source: ABdhPJwl3NnGF1TfkZRlci6WjMWULIHIZ/BPa4U45UMKx/oZHTzTtRdYJEOxN/Xl1feLxe+jPtf4xNYvI4PH X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:90b:3809:: with SMTP id mq9mr62274740pjb.245.1641325768929; Tue, 04 Jan 2022 11:49:28 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:08 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-2-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 01/11] KVM: Capture VM start From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Capture the start of the KVM VM, which is basically the start of any vCPU run. This state of the VM is helpful in the upcoming patches to prevent user-space from configuring certain VM features after the VM has started running. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Reiji Watanabe --- include/linux/kvm_host.h | 3 +++ virt/kvm/kvm_main.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index c310648cc8f1..d0bd8f7a026c 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -623,6 +623,7 @@ struct kvm { struct notifier_block pm_notifier; #endif char stats_id[KVM_STATS_NAME_SIZE]; + bool vm_started; }; =20 #define kvm_err(fmt, ...) \ @@ -1666,6 +1667,8 @@ static inline bool kvm_check_request(int req, struct = kvm_vcpu *vcpu) } } =20 +#define kvm_vm_has_started(kvm) (kvm->vm_started) + extern bool kvm_rebooting; =20 extern unsigned int halt_poll_ns; diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 72c4e6b39389..962b91ac2064 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -3686,6 +3686,7 @@ static long kvm_vcpu_ioctl(struct file *filp, int r; struct kvm_fpu *fpu =3D NULL; struct kvm_sregs *kvm_sregs =3D NULL; + struct kvm *kvm =3D vcpu->kvm; =20 if (vcpu->kvm->mm !=3D current->mm || vcpu->kvm->vm_dead) return -EIO; @@ -3723,6 +3724,14 @@ static long kvm_vcpu_ioctl(struct file *filp, if (oldpid) synchronize_rcu(); put_pid(oldpid); + + /* + * Since we land here even on the first vCPU run, + * we can mark that the VM has started running. + */ + mutex_lock(&kvm->lock); + kvm->vm_started =3D true; + mutex_unlock(&kvm->lock); } r =3D kvm_arch_vcpu_ioctl_run(vcpu); trace_kvm_userspace_exit(vcpu->run->exit_reason, r); --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95EC5C433F5 for ; Tue, 4 Jan 2022 19:49:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231448AbiADTtl (ORCPT ); Tue, 4 Jan 2022 14:49:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231416AbiADTtc (ORCPT ); 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d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=WOQR0x45o+OfHKeVBsrSlnY9CdZeeg7PtH18n9vnXnA=; b=jzWoO9/mPIaWfK1DqTA8SdJoC8MOCaKv0L1QkfZcIb+PLb+99LxFjYtd802aBpgpM4 21/wdLebEN5bo8hC0xovXSB5QFuT/WUBP7SrDz7gL/l+GNJE2bxQNVIdsXol8n1uGvK+ TaFFVgCWm/flX6mXWX1R+9iRqMH5Nic3ZgjxFezwfVvDzfdvFP+pQdemJGizbz1lam+p YKccJQKAlrwM9jRg+4mEFXbPyyzRkE0GmRHQrPd7NUg3UgbQ6AgbIrBWbwNP1h0NkwMR T8rHUNqCRVozMY8oYvqdLxcJH2+R6/eGlh0gOQpCK/Pog9aPlH0Sl1op32fFte/KP5D7 3nfA== X-Gm-Message-State: AOAM533UpjoqhDYEKH1GWHew3BWdyIsIN7jzxu8x/7bL+qqKZc1y3cye My1XMsdVTYuq4fZc5j1pNh3yyo+Mi00Q X-Google-Smtp-Source: ABdhPJy4tj6cLKOVUVB+3uN6Lxc2oi/1CUIrrNriLYLr8YFh0+FHYTCblyAJ5u5+6dJa85R0lc9Otvmgzcan X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:90b:3e83:: with SMTP id rj3mr60585465pjb.132.1641325771561; Tue, 04 Jan 2022 11:49:31 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:09 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-3-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 02/11] KVM: arm64: Factor out firmware register handling from psci.c From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Common hypercall firmware register handing is currently employed by psci.c. Since the upcoming patches add more of these registers, it's better to move the generic handling to hypercall.c for a cleaner presentation. While we are at it, collect all the firmware registers under fw_reg_ids[] to help implement kvm_arm_get_fw_num_regs() and kvm_arm_copy_fw_reg_indices() in a generic way. No functional change intended. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/kvm/guest.c | 2 +- arch/arm64/kvm/hypercalls.c | 170 +++++++++++++++++++++++++++++++++++ arch/arm64/kvm/psci.c | 166 ---------------------------------- include/kvm/arm_hypercalls.h | 7 ++ include/kvm/arm_psci.h | 7 -- 5 files changed, 178 insertions(+), 174 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index e116c7767730..8238e52d890d 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 30da78f72b3b..3c2fcf31ad3d 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -146,3 +146,173 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) smccc_set_retval(vcpu, val[0], val[1], val[2], val[3]); return 1; } + +static const u64 kvm_arm_fw_reg_ids[] =3D { + KVM_REG_ARM_PSCI_VERSION, + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, +}; + +int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) +{ + return ARRAY_SIZE(kvm_arm_fw_reg_ids); +} + +int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) { + if (put_user(kvm_arm_fw_reg_ids[i], uindices++)) + return -EFAULT; + } + + return 0; +} + +#define KVM_REG_FEATURE_LEVEL_WIDTH 4 +#define KVM_REG_FEATURE_LEVEL_MASK (BIT(KVM_REG_FEATURE_LEVEL_WIDTH) - 1) + +/* + * Convert the workaround level into an easy-to-compare number, where high= er + * values mean better protection. + */ +static int get_kernel_wa_level(u64 regid) +{ + switch (regid) { + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: + switch (arm64_get_spectre_v2_state()) { + case SPECTRE_VULNERABLE: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; + case SPECTRE_MITIGATED: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL; + case SPECTRE_UNAFFECTED: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED; + } + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: + switch (arm64_get_spectre_v4_state()) { + case SPECTRE_MITIGATED: + /* + * As for the hypercall discovery, we pretend we + * don't have any FW mitigation if SSBS is there at + * all times. + */ + if (cpus_have_final_cap(ARM64_SSBS)) + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; + fallthrough; + case SPECTRE_UNAFFECTED: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; + case SPECTRE_VULNERABLE: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; + } + } + + return -EINVAL; +} + +int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + void __user *uaddr =3D (void __user *)(long)reg->addr; + u64 val; + + switch (reg->id) { + case KVM_REG_ARM_PSCI_VERSION: + val =3D kvm_psci_version(vcpu, vcpu->kvm); + break; + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: + val =3D get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; + break; + default: + return -ENOENT; + } + + if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + void __user *uaddr =3D (void __user *)(long)reg->addr; + u64 val; + int wa_level; + + if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + switch (reg->id) { + case KVM_REG_ARM_PSCI_VERSION: + { + bool wants_02; + + wants_02 =3D test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features); + + switch (val) { + case KVM_ARM_PSCI_0_1: + if (wants_02) + return -EINVAL; + vcpu->kvm->arch.psci_version =3D val; + return 0; + case KVM_ARM_PSCI_0_2: + case KVM_ARM_PSCI_1_0: + if (!wants_02) + return -EINVAL; + vcpu->kvm->arch.psci_version =3D val; + return 0; + } + break; + } + + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: + if (val & ~KVM_REG_FEATURE_LEVEL_MASK) + return -EINVAL; + + if (get_kernel_wa_level(reg->id) < val) + return -EINVAL; + + return 0; + + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: + if (val & ~(KVM_REG_FEATURE_LEVEL_MASK | + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED)) + return -EINVAL; + + /* The enabled bit must not be set unless the level is AVAIL. */ + if ((val & KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED) && + (val & KVM_REG_FEATURE_LEVEL_MASK) !=3D KVM_REG_ARM_SMCCC_ARCH_WORKA= ROUND_2_AVAIL) + return -EINVAL; + + /* + * Map all the possible incoming states to the only two we + * really want to deal with. + */ + switch (val & KVM_REG_FEATURE_LEVEL_MASK) { + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL: + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN: + wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; + break; + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL: + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED: + wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; + break; + default: + return -EINVAL; + } + + /* + * We can deal with NOT_AVAIL on NOT_REQUIRED, but not the + * other way around. + */ + if (get_kernel_wa_level(reg->id) < wa_level) + return -EINVAL; + + return 0; + default: + return -ENOENT; + } + + return -EINVAL; +} diff --git a/arch/arm64/kvm/psci.c b/arch/arm64/kvm/psci.c index 74c47d420253..6c8323ae32f2 100644 --- a/arch/arm64/kvm/psci.c +++ b/arch/arm64/kvm/psci.c @@ -403,169 +403,3 @@ int kvm_psci_call(struct kvm_vcpu *vcpu) return -EINVAL; }; } - -int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) -{ - return 3; /* PSCI version and two workaround registers */ -} - -int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) -{ - if (put_user(KVM_REG_ARM_PSCI_VERSION, uindices++)) - return -EFAULT; - - if (put_user(KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, uindices++)) - return -EFAULT; - - if (put_user(KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, uindices++)) - return -EFAULT; - - return 0; -} - -#define KVM_REG_FEATURE_LEVEL_WIDTH 4 -#define KVM_REG_FEATURE_LEVEL_MASK (BIT(KVM_REG_FEATURE_LEVEL_WIDTH) - 1) - -/* - * Convert the workaround level into an easy-to-compare number, where high= er - * values mean better protection. - */ -static int get_kernel_wa_level(u64 regid) -{ - switch (regid) { - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - switch (arm64_get_spectre_v2_state()) { - case SPECTRE_VULNERABLE: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; - case SPECTRE_MITIGATED: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL; - case SPECTRE_UNAFFECTED: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED; - } - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - switch (arm64_get_spectre_v4_state()) { - case SPECTRE_MITIGATED: - /* - * As for the hypercall discovery, we pretend we - * don't have any FW mitigation if SSBS is there at - * all times. - */ - if (cpus_have_final_cap(ARM64_SSBS)) - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - fallthrough; - case SPECTRE_UNAFFECTED: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; - case SPECTRE_VULNERABLE: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - } - } - - return -EINVAL; -} - -int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) -{ - void __user *uaddr =3D (void __user *)(long)reg->addr; - u64 val; - - switch (reg->id) { - case KVM_REG_ARM_PSCI_VERSION: - val =3D kvm_psci_version(vcpu, vcpu->kvm); - break; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - val =3D get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; - break; - default: - return -ENOENT; - } - - if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) - return -EFAULT; - - return 0; -} - -int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) -{ - void __user *uaddr =3D (void __user *)(long)reg->addr; - u64 val; - int wa_level; - - if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) - return -EFAULT; - - switch (reg->id) { - case KVM_REG_ARM_PSCI_VERSION: - { - bool wants_02; - - wants_02 =3D test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features); - - switch (val) { - case KVM_ARM_PSCI_0_1: - if (wants_02) - return -EINVAL; - vcpu->kvm->arch.psci_version =3D val; - return 0; - case KVM_ARM_PSCI_0_2: - case KVM_ARM_PSCI_1_0: - if (!wants_02) - return -EINVAL; - vcpu->kvm->arch.psci_version =3D val; - return 0; - } - break; - } - - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - if (val & ~KVM_REG_FEATURE_LEVEL_MASK) - return -EINVAL; - - if (get_kernel_wa_level(reg->id) < val) - return -EINVAL; - - return 0; - - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - if (val & ~(KVM_REG_FEATURE_LEVEL_MASK | - KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED)) - return -EINVAL; - - /* The enabled bit must not be set unless the level is AVAIL. */ - if ((val & KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED) && - (val & KVM_REG_FEATURE_LEVEL_MASK) !=3D KVM_REG_ARM_SMCCC_ARCH_WORKA= ROUND_2_AVAIL) - return -EINVAL; - - /* - * Map all the possible incoming states to the only two we - * really want to deal with. - */ - switch (val & KVM_REG_FEATURE_LEVEL_MASK) { - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN: - wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - break; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED: - wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; - break; - default: - return -EINVAL; - } - - /* - * We can deal with NOT_AVAIL on NOT_REQUIRED, but not the - * other way around. - */ - if (get_kernel_wa_level(reg->id) < wa_level) - return -EINVAL; - - return 0; - default: - return -ENOENT; - } - - return -EINVAL; -} diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 0e2509d27910..5d38628a8d04 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -40,4 +40,11 @@ static inline void smccc_set_retval(struct kvm_vcpu *vcp= u, vcpu_set_reg(vcpu, 3, a3); } =20 +struct kvm_one_reg; + +int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu); +int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s); +int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); +int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); + #endif diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index 5b58bd2fe088..080c2d0bd6e7 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -42,11 +42,4 @@ static inline int kvm_psci_version(struct kvm_vcpu *vcpu= , struct kvm *kvm) =20 int kvm_psci_call(struct kvm_vcpu *vcpu); =20 -struct kvm_one_reg; - -int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu); -int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s); -int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); -int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); - #endif /* __KVM_ARM_PSCI_H__ */ --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9165C4332F for ; Tue, 4 Jan 2022 19:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231732AbiADTtp (ORCPT ); Tue, 4 Jan 2022 14:49:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231655AbiADTth (ORCPT ); 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charset="utf-8" Introduce the KVM ARM64 capability, KVM_CAP_ARM_HVC_FW_REG_BMAP, to indicate the support for psuedo-firmware bitmap extension. Each of these registers holds a feature-set exposed to the guest in the form of a bitmap. If supported, a simple 'read' of the capability should return the number of psuedo-firmware registers supported. User-space can utilize this to discover the registers. It can further explore or modify the features using the classical GET/SET_ONE_REG interface. Signed-off-by: Raghavendra Rao Ananta --- Documentation/virt/kvm/api.rst | 21 +++++++++++++++++++++ include/uapi/linux/kvm.h | 1 + 2 files changed, 22 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index aeeb071c7688..646176537f2c 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6925,6 +6925,27 @@ indicated by the fd to the VM this is called on. This is intended to support intra-host migration of VMs between userspace = VMMs, upgrading the VMM process without interrupting the guest. =20 +7.30 KVM_CAP_ARM_HVC_FW_REG_BMAP +-------------------------------- + +:Architectures: arm64 +:Parameters: None +:Returns: Number of psuedo-firmware registers supported + +This capability indicates that KVM for arm64 supports the psuedo-firmware +register bitmap extension. Each of these registers represent the features +supported by a particular type in the form of a bitmap. By default, these +registers are set with the upper limit of the features that are supported. + +The registers can be accessed via the standard SET_ONE_REG and KVM_GET_ONE= _REG +interfaces. The user-space is expected to read the number of these registe= rs +available by reading KVM_CAP_ARM_HVC_FW_REG_BMAP, read the current bitmap +configuration via GET_ONE_REG for each register, and then write back the +desired bitmap of features that it wishes the guest to see via SET_ONE_REG. + +Note that KVM doesn't allow the user-space to modify these registers after +the VM (any of the vCPUs) has started running. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 1daa45268de2..209b43dbbc3c 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204 #define KVM_CAP_ARM_MTE 205 #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206 +#define KVM_CAP_ARM_HVC_FW_REG_BMAP 207 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF0E2C433FE for ; Tue, 4 Jan 2022 19:49:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232036AbiADTty (ORCPT ); Tue, 4 Jan 2022 14:49:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231712AbiADTti (ORCPT ); Tue, 4 Jan 2022 14:49:38 -0500 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AB36C061785 for ; Tue, 4 Jan 2022 11:49:38 -0800 (PST) Received: by mail-pg1-x549.google.com with SMTP id p6-20020a63ab06000000b0033fcc84d4f6so20260143pgf.5 for ; Tue, 04 Jan 2022 11:49:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=yfWDJrgheE6EJzsXpJMIRXHEkqTr0RVehHDg0xmihp8=; b=W0AXiLpl2S7gXtCBksq+thzqaUHb/7bLFRjviizxzYnABqvhnuGn4bzUwgFxoksDs/ bbhcaFZXCIqhJiEKR3OvwN5sCm8XNxcjGYxdvM7MpZzTUBEDpSRg6DdiVe7kpkv1WPRu UWdPkuCepwzBv+aDaGPBwQmoqrWixSXMfkInP/PXY4A8R61FN6Ml1pmnDrZRltieP2WI kg/1XqsTRCAFDli+/o0o0AFZOPxlsUbk8JZfVSiS572Z9UtAgp3lH5YYbBdW7FhIpPRj WmoMFyH7/1LRnaumoUA/0OqKBqP12ak2nt05qNETVU0iexosHP9hHL8WlLvP1w0VWxL2 ckUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=yfWDJrgheE6EJzsXpJMIRXHEkqTr0RVehHDg0xmihp8=; b=Ay3MS7SoSbNSy/FDSzP7wGiMuJiTJ7jxketfM0AWVRjRjuVjPDNypHjwUPfRbMnoct HjMCiUAmmuWHE81cTksP/cZntZUup2qxHGv6yrBCpD31/EAS/YUnbq+C6xPMpkODibnm cm6018uR0I5in9El4ULavShy2gZ9SwjTLWp7R1XvEcE6OJocp+HkNuEyJvzdcwKUzYf1 7WurDD3iAx/2H08+5+b+RkIvoWcLCuCrjtAjPqTcpWqq2llXQyQFXu/bN2gcMMUx6WDQ BQcSS5tYjsZ5dGesJj85dNRSBQADQnAin4xnJqJtzKa/UDNM+PkaakBmjnNXKqUlXgyi SkIQ== X-Gm-Message-State: AOAM530XcpNRhppqvj3AODVsVeDnJd7JOpMNCrq3qpMgWrRAXrkKaJTC zCyauBMYZGaRYL007za5ca8bYY3AkUhz X-Google-Smtp-Source: ABdhPJzt7q6w1jFERyOAw2+AtYhDsaPLLpmCxdrGIzTeujAMo2uRVcJyfPB4fALmXk6r1dYw2Cm98vwiSARV X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:b201:b0:149:4b25:332d with SMTP id t1-20020a170902b20100b001494b25332dmr52005386plr.17.1641325777691; Tue, 04 Jan 2022 11:49:37 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:11 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-5-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 04/11] KVM: arm64: Setup a framework for hypercall bitmap firmware registers From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM regularly introduces new hypercall services to the guests without any consent from the Virtual Machine Manager (VMM). This means, the guests can observe hypercall services in and out as they migrate across various host kernel versions. This could be a major problem if the guest discovered a hypercall, started using it, and after getting migrated to an older kernel realizes that it's no longer available. Depending on how the guest handles the change, there's a potential chance that the guest would just panic. As a result, there's a need for the VMM to elect the services that it wishes the guest to discover. VMM can elect these services based on the kernels spread across its (migration) fleet. To remedy this, extend the existing firmware psuedo-registers, such as KVM_REG_ARM_PSCI_VERSION, for all the hypercall services available. These firmware registers are categorized based on the service call owners, and unlike the existing firmware psuedo-registers, they hold the features supported in the form of a bitmap. The capability, KVM_CAP_ARM_HVC_FW_REG_BMAP, is used to announce this extension, which returns the number of psuedo-firmware registers supported. During the VM initialization, the registers holds an upper-limit of the features supported by the corresponding registers. It's expected that the VMMs discover the features provided by each register via GET_ONE_REG, and writeback the desired values using SET_ONE_REG. KVM allows this modification only until the VM has started. Older VMMs can simply ignore the capability and the hypercall services will be exposed unconditionally to the guests, thus ensuring backward compatibility. In this patch, the framework adds the register only for ARM's standard secure services (owner value 4). Currently, this includes support only for ARM True Random Number Generator (TRNG) service, with bit-0 of the register representing mandatory features of v1.0. Other services are momentarily added in the upcoming patches. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 12 ++++ arch/arm64/include/uapi/asm/kvm.h | 4 ++ arch/arm64/kvm/arm.c | 4 ++ arch/arm64/kvm/hypercalls.c | 103 +++++++++++++++++++++++++++++- arch/arm64/kvm/trng.c | 8 +-- include/kvm/arm_hypercalls.h | 6 ++ 6 files changed, 129 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 2a5f7f38006f..a32cded0371b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -102,6 +102,15 @@ struct kvm_s2_mmu { struct kvm_arch_memory_slot { }; =20 +/** + * struct kvm_hvc_desc: KVM ARM64 hypercall descriptor + * + * @hvc_std_bmap: Bitmap of standard secure service calls + */ +struct kvm_hvc_desc { + u64 hvc_std_bmap; +}; + struct kvm_arch { struct kvm_s2_mmu mmu; =20 @@ -137,6 +146,9 @@ struct kvm_arch { =20 /* Memory Tagging Extension enabled for the guest */ bool mte_enabled; + + /* Hypercall firmware register' descriptor */ + struct kvm_hvc_desc hvc_desc; }; =20 struct kvm_vcpu_fault_info { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index b3edde68bc3e..0d6f29c58456 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -281,6 +281,10 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) =20 +#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_REG(3) +#define KVM_REG_ARM_STD_BIT_TRNG_V1_0 BIT(0) +#define KVM_REG_ARM_STD_BMAP_BIT_MAX 0 /* Last valid bit */ + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index e4727dc771bf..56fe81565235 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -156,6 +156,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long typ= e) kvm->arch.max_vcpus =3D kvm_arm_default_max_vcpus(); =20 set_default_spectre(kvm); + kvm_arm_init_hypercalls(kvm); =20 return ret; out_free_stage2_pgd: @@ -283,6 +284,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) case KVM_CAP_ARM_PTRAUTH_GENERIC: r =3D system_has_full_ptr_auth(); break; + case KVM_CAP_ARM_HVC_FW_REG_BMAP: + r =3D kvm_arm_num_fw_bmap_regs(); + break; default: r =3D 0; } diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 3c2fcf31ad3d..06243e4670eb 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -58,6 +58,29 @@ static void kvm_ptp_get_time(struct kvm_vcpu *vcpu, u64 = *val) val[3] =3D lower_32_bits(cycles); } =20 +static bool kvm_arm_fw_reg_feat_enabled(u64 reg_bmap, u64 feat_bit) +{ + return reg_bmap & feat_bit; +} + +bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu, u32 func_id) +{ + struct kvm_hvc_desc *hvc_desc =3D &vcpu->kvm->arch.hvc_desc; + + switch (func_id) { + case ARM_SMCCC_TRNG_VERSION: + case ARM_SMCCC_TRNG_FEATURES: + case ARM_SMCCC_TRNG_GET_UUID: + case ARM_SMCCC_TRNG_RND32: + case ARM_SMCCC_TRNG_RND64: + return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_bmap, + KVM_REG_ARM_STD_BIT_TRNG_V1_0); + default: + /* By default, allow the services that aren't listed here */ + return true; + } +} + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) { u32 func_id =3D smccc_get_function(vcpu); @@ -65,6 +88,9 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) u32 feature; gpa_t gpa; =20 + if (!kvm_hvc_call_supported(vcpu, func_id)) + goto out; + switch (func_id) { case ARM_SMCCC_VERSION_FUNC_ID: val[0] =3D ARM_SMCCC_VERSION_1_1; @@ -143,6 +169,7 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) return kvm_psci_call(vcpu); } =20 +out: smccc_set_retval(vcpu, val[0], val[1], val[2], val[3]); return 1; } @@ -153,9 +180,25 @@ static const u64 kvm_arm_fw_reg_ids[] =3D { KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, }; =20 +static const u64 kvm_arm_fw_reg_bmap_ids[] =3D { + KVM_REG_ARM_STD_BMAP, +}; + +void kvm_arm_init_hypercalls(struct kvm *kvm) +{ + struct kvm_hvc_desc *hvc_desc =3D &kvm->arch.hvc_desc; + + hvc_desc->hvc_std_bmap =3D ARM_SMCCC_STD_FEATURES; +} + +int kvm_arm_num_fw_bmap_regs(void) +{ + return ARRAY_SIZE(kvm_arm_fw_reg_bmap_ids); +} + int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) { - return ARRAY_SIZE(kvm_arm_fw_reg_ids); + return ARRAY_SIZE(kvm_arm_fw_reg_ids) + kvm_arm_num_fw_bmap_regs(); } =20 int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) @@ -167,6 +210,11 @@ int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu,= u64 __user *uindices) return -EFAULT; } =20 + for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_bmap_ids); i++) { + if (put_user(kvm_arm_fw_reg_bmap_ids[i], uindices++)) + return -EFAULT; + } + return 0; } =20 @@ -211,9 +259,20 @@ static int get_kernel_wa_level(u64 regid) return -EINVAL; } =20 +static void +kvm_arm_get_fw_reg_bmap(struct kvm_vcpu *vcpu, u64 fw_reg_bmap, u64 *val) +{ + struct kvm *kvm =3D vcpu->kvm; + + mutex_lock(&kvm->lock); + *val =3D fw_reg_bmap; + mutex_unlock(&kvm->lock); +} + int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { void __user *uaddr =3D (void __user *)(long)reg->addr; + struct kvm_hvc_desc *hvc_desc =3D &vcpu->kvm->arch.hvc_desc; u64 val; =20 switch (reg->id) { @@ -224,6 +283,9 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: val =3D get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; break; + case KVM_REG_ARM_STD_BMAP: + kvm_arm_get_fw_reg_bmap(vcpu, hvc_desc->hvc_std_bmap, &val); + break; default: return -ENOENT; } @@ -234,6 +296,43 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const st= ruct kvm_one_reg *reg) return 0; } =20 +static int kvm_arm_set_fw_reg_bmap(struct kvm_vcpu *vcpu, u64 reg_id, u64 = val) +{ + int ret =3D 0; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_hvc_desc *hvc_desc =3D &kvm->arch.hvc_desc; + u64 *fw_reg_bmap, fw_reg_features; + + switch (reg_id) { + case KVM_REG_ARM_STD_BMAP: + fw_reg_bmap =3D &hvc_desc->hvc_std_bmap; + fw_reg_features =3D ARM_SMCCC_STD_FEATURES; + break; + default: + return -ENOENT; + } + + /* Check for unsupported bit */ + if (val & ~fw_reg_features) + return -EINVAL; + + mutex_lock(&kvm->lock); + + /* + * If the VM (any vCPU) has already started running, return success + * if there's no change in the value. Else, return -EBUSY. + */ + if (kvm_vm_has_started(kvm)) { + ret =3D *fw_reg_bmap !=3D val ? -EBUSY : 0; + goto out; + } + + *fw_reg_bmap =3D val; +out: + mutex_unlock(&kvm->lock); + return ret; +} + int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { void __user *uaddr =3D (void __user *)(long)reg->addr; @@ -310,6 +409,8 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) return -EINVAL; =20 return 0; + case KVM_REG_ARM_STD_BMAP: + return kvm_arm_set_fw_reg_bmap(vcpu, reg->id, val); default: return -ENOENT; } diff --git a/arch/arm64/kvm/trng.c b/arch/arm64/kvm/trng.c index 99bdd7103c9c..23f912514b06 100644 --- a/arch/arm64/kvm/trng.c +++ b/arch/arm64/kvm/trng.c @@ -60,14 +60,8 @@ int kvm_trng_call(struct kvm_vcpu *vcpu) val =3D ARM_SMCCC_TRNG_VERSION_1_0; break; case ARM_SMCCC_TRNG_FEATURES: - switch (smccc_get_arg1(vcpu)) { - case ARM_SMCCC_TRNG_VERSION: - case ARM_SMCCC_TRNG_FEATURES: - case ARM_SMCCC_TRNG_GET_UUID: - case ARM_SMCCC_TRNG_RND32: - case ARM_SMCCC_TRNG_RND64: + if (kvm_hvc_call_supported(vcpu, smccc_get_arg1(vcpu))) val =3D TRNG_SUCCESS; - } break; case ARM_SMCCC_TRNG_GET_UUID: smccc_set_retval(vcpu, le32_to_cpu(u[0]), le32_to_cpu(u[1]), diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 5d38628a8d04..8fe68d8d6d96 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -6,6 +6,9 @@ =20 #include =20 +#define ARM_SMCCC_STD_FEATURES \ + GENMASK_ULL(KVM_REG_ARM_STD_BMAP_BIT_MAX, 0) + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); =20 static inline u32 smccc_get_function(struct kvm_vcpu *vcpu) @@ -42,9 +45,12 @@ static inline void smccc_set_retval(struct kvm_vcpu *vcp= u, =20 struct kvm_one_reg; =20 +void kvm_arm_init_hypercalls(struct kvm *kvm); +int kvm_arm_num_fw_bmap_regs(void); int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu); int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s); int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); +bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu, u32 func_id); =20 #endif --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 783A2C433F5 for ; Tue, 4 Jan 2022 19:50:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232134AbiADTuB (ORCPT ); Tue, 4 Jan 2022 14:50:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231609AbiADTtk (ORCPT ); Tue, 4 Jan 2022 14:49:40 -0500 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4E57C061784 for ; Tue, 4 Jan 2022 11:49:40 -0800 (PST) Received: by mail-pg1-x549.google.com with SMTP id s16-20020a63ff50000000b0033b6e4cedc8so20236699pgk.8 for ; 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Tue, 04 Jan 2022 11:49:40 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:12 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-6-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 05/11] KVM: arm64: Add standard hypervisor firmware register From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the firmware register to hold the standard hypervisor service calls (owner value 5) as a bitmap. The bitmap represents the features that'll be enabled for the guest, as configured by the user-space. Currently, this includes support only for Paravirtualized time, represented by bit-0. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/uapi/asm/kvm.h | 4 ++++ arch/arm64/kvm/hypercalls.c | 17 ++++++++++++++++- arch/arm64/kvm/pvtime.c | 3 +++ include/kvm/arm_hypercalls.h | 3 +++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index a32cded0371b..1daf2c0b3b85 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -106,9 +106,11 @@ struct kvm_arch_memory_slot { * struct kvm_hvc_desc: KVM ARM64 hypercall descriptor * * @hvc_std_bmap: Bitmap of standard secure service calls + * @hvc_std_hyp_bmap: Bitmap of standard hypervisor service calls */ struct kvm_hvc_desc { u64 hvc_std_bmap; + u64 hvc_std_hyp_bmap; }; =20 struct kvm_arch { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 0d6f29c58456..af59c434ae33 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -285,6 +285,10 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_STD_BIT_TRNG_V1_0 BIT(0) #define KVM_REG_ARM_STD_BMAP_BIT_MAX 0 /* Last valid bit */ =20 +#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_REG(4) +#define KVM_REG_ARM_STD_HYP_BIT_PV_TIME BIT(0) +#define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0 /* Last valid bit */ + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) =20 diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 06243e4670eb..9df0221834a3 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -75,6 +75,10 @@ bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu, u32 f= unc_id) case ARM_SMCCC_TRNG_RND64: return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_bmap, KVM_REG_ARM_STD_BIT_TRNG_V1_0); + case ARM_SMCCC_HV_PV_TIME_FEATURES: + case ARM_SMCCC_HV_PV_TIME_ST: + return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_hyp_bmap, + KVM_REG_ARM_STD_HYP_BIT_PV_TIME); default: /* By default, allow the services that aren't listed here */ return true; @@ -134,7 +138,8 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) } break; case ARM_SMCCC_HV_PV_TIME_FEATURES: - val[0] =3D SMCCC_RET_SUCCESS; + if (kvm_hvc_call_supported(vcpu, feature)) + val[0] =3D SMCCC_RET_SUCCESS; break; } break; @@ -182,6 +187,7 @@ static const u64 kvm_arm_fw_reg_ids[] =3D { =20 static const u64 kvm_arm_fw_reg_bmap_ids[] =3D { KVM_REG_ARM_STD_BMAP, + KVM_REG_ARM_STD_HYP_BMAP, }; =20 void kvm_arm_init_hypercalls(struct kvm *kvm) @@ -189,6 +195,7 @@ void kvm_arm_init_hypercalls(struct kvm *kvm) struct kvm_hvc_desc *hvc_desc =3D &kvm->arch.hvc_desc; =20 hvc_desc->hvc_std_bmap =3D ARM_SMCCC_STD_FEATURES; + hvc_desc->hvc_std_hyp_bmap =3D ARM_SMCCC_STD_HYP_FEATURES; } =20 int kvm_arm_num_fw_bmap_regs(void) @@ -286,6 +293,9 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) case KVM_REG_ARM_STD_BMAP: kvm_arm_get_fw_reg_bmap(vcpu, hvc_desc->hvc_std_bmap, &val); break; + case KVM_REG_ARM_STD_HYP_BMAP: + kvm_arm_get_fw_reg_bmap(vcpu, hvc_desc->hvc_std_hyp_bmap, &val); + break; default: return -ENOENT; } @@ -308,6 +318,10 @@ static int kvm_arm_set_fw_reg_bmap(struct kvm_vcpu *vc= pu, u64 reg_id, u64 val) fw_reg_bmap =3D &hvc_desc->hvc_std_bmap; fw_reg_features =3D ARM_SMCCC_STD_FEATURES; break; + case KVM_REG_ARM_STD_HYP_BMAP: + fw_reg_bmap =3D &hvc_desc->hvc_std_hyp_bmap; + fw_reg_features =3D ARM_SMCCC_STD_HYP_FEATURES; + break; default: return -ENOENT; } @@ -410,6 +424,7 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) =20 return 0; case KVM_REG_ARM_STD_BMAP: + case KVM_REG_ARM_STD_HYP_BMAP: return kvm_arm_set_fw_reg_bmap(vcpu, reg->id, val); default: return -ENOENT; diff --git a/arch/arm64/kvm/pvtime.c b/arch/arm64/kvm/pvtime.c index 78a09f7a6637..4fa436dbd0b7 100644 --- a/arch/arm64/kvm/pvtime.c +++ b/arch/arm64/kvm/pvtime.c @@ -37,6 +37,9 @@ long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu) u32 feature =3D smccc_get_arg1(vcpu); long val =3D SMCCC_RET_NOT_SUPPORTED; =20 + if (!kvm_hvc_call_supported(vcpu, feature)) + return val; + switch (feature) { case ARM_SMCCC_HV_PV_TIME_FEATURES: case ARM_SMCCC_HV_PV_TIME_ST: diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 8fe68d8d6d96..1a79b5f89a24 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -9,6 +9,9 @@ #define ARM_SMCCC_STD_FEATURES \ GENMASK_ULL(KVM_REG_ARM_STD_BMAP_BIT_MAX, 0) =20 +#define ARM_SMCCC_STD_HYP_FEATURES \ + GENMASK_ULL(KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX, 0) + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); =20 static inline u32 smccc_get_function(struct kvm_vcpu *vcpu) --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29E8DC433EF for ; Tue, 4 Jan 2022 19:50:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232255AbiADTuG (ORCPT ); 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charset="utf-8" Introduce the firmware register to hold the vendor specific hypervisor service calls (owner value 6) as a bitmap. The bitmap represents the features that'll be enabled for the guest, as configured by the user-space. Currently, this includes support only for Precision Time Protocol (PTP), represented by bit-0. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/uapi/asm/kvm.h | 4 ++++ arch/arm64/kvm/hypercalls.c | 23 ++++++++++++++++++++++- include/kvm/arm_hypercalls.h | 3 +++ 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 1daf2c0b3b85..877096737ee1 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -107,10 +107,12 @@ struct kvm_arch_memory_slot { * * @hvc_std_bmap: Bitmap of standard secure service calls * @hvc_std_hyp_bmap: Bitmap of standard hypervisor service calls + * @hvc_vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls */ struct kvm_hvc_desc { u64 hvc_std_bmap; u64 hvc_std_hyp_bmap; + u64 hvc_vendor_hyp_bmap; }; =20 struct kvm_arch { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index af59c434ae33..7f076da55f30 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -289,6 +289,10 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_STD_HYP_BIT_PV_TIME BIT(0) #define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0 /* Last valid bit */ =20 +#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_REG(5) +#define KVM_REG_ARM_VENDOR_HYP_BIT_PTP BIT(0) +#define KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX 0 /* Last valid bit */ + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) =20 diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 9df0221834a3..2403ad50d759 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -79,6 +79,9 @@ bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu, u32 fu= nc_id) case ARM_SMCCC_HV_PV_TIME_ST: return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_hyp_bmap, KVM_REG_ARM_STD_HYP_BIT_PV_TIME); + case ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID: + return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_vendor_hyp_bmap, + KVM_REG_ARM_VENDOR_HYP_BIT_PTP); default: /* By default, allow the services that aren't listed here */ return true; @@ -87,6 +90,7 @@ bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu, u32 fu= nc_id) =20 int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) { + struct kvm_hvc_desc *hvc_desc =3D &vcpu->kvm->arch.hvc_desc; u32 func_id =3D smccc_get_function(vcpu); u64 val[4] =3D {SMCCC_RET_NOT_SUPPORTED}; u32 feature; @@ -159,7 +163,14 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) break; case ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID: val[0] =3D BIT(ARM_SMCCC_KVM_FUNC_FEATURES); - val[0] |=3D BIT(ARM_SMCCC_KVM_FUNC_PTP); + + /* + * The feature bits exposed to user-space doesn't include + * ARM_SMCCC_KVM_FUNC_FEATURES. However, we expose this to + * the guest as bit-0. Hence, left-shift the user-space + * exposed bitmap by 1 to accommodate this. + */ + val[0] |=3D hvc_desc->hvc_vendor_hyp_bmap << 1; break; case ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID: kvm_ptp_get_time(vcpu, val); @@ -188,6 +199,7 @@ static const u64 kvm_arm_fw_reg_ids[] =3D { static const u64 kvm_arm_fw_reg_bmap_ids[] =3D { KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, + KVM_REG_ARM_VENDOR_HYP_BMAP, }; =20 void kvm_arm_init_hypercalls(struct kvm *kvm) @@ -196,6 +208,7 @@ void kvm_arm_init_hypercalls(struct kvm *kvm) =20 hvc_desc->hvc_std_bmap =3D ARM_SMCCC_STD_FEATURES; hvc_desc->hvc_std_hyp_bmap =3D ARM_SMCCC_STD_HYP_FEATURES; + hvc_desc->hvc_vendor_hyp_bmap =3D ARM_SMCCC_VENDOR_HYP_FEATURES; } =20 int kvm_arm_num_fw_bmap_regs(void) @@ -296,6 +309,9 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) case KVM_REG_ARM_STD_HYP_BMAP: kvm_arm_get_fw_reg_bmap(vcpu, hvc_desc->hvc_std_hyp_bmap, &val); break; + case KVM_REG_ARM_VENDOR_HYP_BMAP: + kvm_arm_get_fw_reg_bmap(vcpu, hvc_desc->hvc_vendor_hyp_bmap, &val); + break; default: return -ENOENT; } @@ -322,6 +338,10 @@ static int kvm_arm_set_fw_reg_bmap(struct kvm_vcpu *vc= pu, u64 reg_id, u64 val) fw_reg_bmap =3D &hvc_desc->hvc_std_hyp_bmap; fw_reg_features =3D ARM_SMCCC_STD_HYP_FEATURES; break; + case KVM_REG_ARM_VENDOR_HYP_BMAP: + fw_reg_bmap =3D &hvc_desc->hvc_vendor_hyp_bmap; + fw_reg_features =3D ARM_SMCCC_VENDOR_HYP_FEATURES; + break; default: return -ENOENT; } @@ -425,6 +445,7 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) return 0; case KVM_REG_ARM_STD_BMAP: case KVM_REG_ARM_STD_HYP_BMAP: + case KVM_REG_ARM_VENDOR_HYP_BMAP: return kvm_arm_set_fw_reg_bmap(vcpu, reg->id, val); default: return -ENOENT; diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 1a79b5f89a24..8f54cacfbf40 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -12,6 +12,9 @@ #define ARM_SMCCC_STD_HYP_FEATURES \ GENMASK_ULL(KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX, 0) =20 +#define ARM_SMCCC_VENDOR_HYP_FEATURES \ + GENMASK_ULL(KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX, 0) + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); =20 static inline u32 smccc_get_function(struct kvm_vcpu *vcpu) --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5D16C433F5 for ; Tue, 4 Jan 2022 19:50:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232320AbiADTuJ (ORCPT ); Tue, 4 Jan 2022 14:50:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231748AbiADTtq (ORCPT ); Tue, 4 Jan 2022 14:49:46 -0500 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB8A9C061761 for ; Tue, 4 Jan 2022 11:49:45 -0800 (PST) Received: by mail-pg1-x54a.google.com with SMTP id m14-20020a633f0e000000b0033fc903c6a4so20230671pga.12 for ; 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Tue, 04 Jan 2022 11:49:45 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:14 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-8-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 07/11] Docs: KVM: Add doc for the bitmap firmware registers From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the documentation for the bitmap firmware registers in psci.rst. This includes the details for KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, and KVM_REG_ARM_VENDOR_HYP_BMAP registers. Signed-off-by: Raghavendra Rao Ananta --- Documentation/virt/kvm/arm/psci.rst | 85 +++++++++++++++++++++++------ 1 file changed, 68 insertions(+), 17 deletions(-) diff --git a/Documentation/virt/kvm/arm/psci.rst b/Documentation/virt/kvm/a= rm/psci.rst index d52c2e83b5b8..edc3caf927ae 100644 --- a/Documentation/virt/kvm/arm/psci.rst +++ b/Documentation/virt/kvm/arm/psci.rst @@ -1,32 +1,32 @@ .. SPDX-License-Identifier: GPL-2.0 =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Power State Coordination Interface (PSCI) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +ARM Hypercall Interface +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -KVM implements the PSCI (Power State Coordination Interface) -specification in order to provide services such as CPU on/off, reset -and power-off to the guest. +KVM handles the hypercall services as requested by the guests. New hyperca= ll +services are regularly made available by the ARM specification or by KVM (= as +vendor services) if they make sense from a virtualization point of view. =20 -The PSCI specification is regularly updated to provide new features, -and KVM implements these updates if they make sense from a virtualization -point of view. - -This means that a guest booted on two different versions of KVM can -observe two different "firmware" revisions. This could cause issues if -a given guest is tied to a particular PSCI revision (unlikely), or if -a migration causes a different PSCI version to be exposed out of the -blue to an unsuspecting guest. +This means that a guest booted on two different versions of KVM can observe +two different "firmware" revisions. This could cause issues if a given gue= st +is tied to a particular version of a hypercall service, or if a migration +causes a different version to be exposed out of the blue to an unsuspecting +guest. =20 In order to remedy this situation, KVM exposes a set of "firmware pseudo-registers" that can be manipulated using the GET/SET_ONE_REG interface. These registers can be saved/restored by userspace, and set to a convenient value if required. =20 -The following register is defined: +The following registers are defined: =20 * KVM_REG_ARM_PSCI_VERSION: =20 + KVM implements the PSCI (Power State Coordination Interface) + specification in order to provide services such as CPU on/off, reset + and power-off to the guest. + - Only valid if the vcpu has the KVM_ARM_VCPU_PSCI_0_2 feature set (and thus has already been initialized) - Returns the current PSCI version on GET_ONE_REG (defaulting to the @@ -74,4 +74,55 @@ The following register is defined: KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED: The workaround is always active on this vCPU or it is not needed. =20 -.. [1] https://developer.arm.com/-/media/developer/pdf/ARM_DEN_0070A_Firmw= are_interfaces_for_mitigating_CVE-2017-5715.pdf +Contrary to the above registers, the following registers exposes the hyper= call +services in the form of a feature-bitmap. This bitmap is translated to the +services that are exposed to the guest. There is a register defined per se= rvice +call owner and can be accessed via GET/SET_ONE_REG interface. + +A new KVM capability, KVM_CAP_ARM_HVC_FW_REG_BMAP, is introduced to let +user-space know of this extension. A simple 'read' of the capability would +return the number of bitmapped registers. The user-space is expected to +make a not of this value and configure each of the register. + +By default, these registers are set with the upper limit of the features t= hat +are supported. User-space can discover this configuration via GET_ONE_REG.= If +unsatisfied, the user-space can write back the desired bitmap back via +SET_ONE_REG. + +The psuedo-firmware bitmap register are as follows: + +* KVM_REG_ARM_STD_BMAP: + Controls the bitmap of the ARM Standard Secure Service Calls. + + The following bits are accepted: + + KVM_REG_ARM_STD_BIT_TRNG_V1_0: + The bit represents the services offered under v1.0 of ARM True Random + Number Generator (TRNG) specification, ARM DEN0098. + +* KVM_REG_ARM_STD_HYP_BMAP: + Controls the bitmap of the ARM Standard Hypervisor Service Calls. + + The following bits are accepted: + + KVM_REG_ARM_STD_HYP_BIT_PV_TIME: + The bit represents the Paravirtualized Time service as represented by + ARM DEN0057A. + +* KVM_REG_ARM_VENDOR_HYP_BMAP: + Controls the bitmap of the Vendor specific Hypervisor Service Calls. + + The following bits are accepted: + + KVM_REG_ARM_VENDOR_HYP_BIT_PTP: + The bit represents the Precision Time Protocol KVM service. + +Errors: + + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + -ENOENT Unknown register accessed. + -EBUSY Attempt a 'write' to the register after the VM has started. + -EINVAL Invalid bitmap written to the register. + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. [1] https://developer.arm.com/-/media/developer/pdf/ARM_DEN_0070A_Firmw= are_interfaces_for_mitigating_CVE-2017-5715.pdf \ No newline at end of file --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49BD9C433FE for ; Tue, 4 Jan 2022 19:50:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232328AbiADTuM (ORCPT ); Tue, 4 Jan 2022 14:50:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231840AbiADTts (ORCPT ); Tue, 4 Jan 2022 14:49:48 -0500 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3427BC061799 for ; Tue, 4 Jan 2022 11:49:48 -0800 (PST) Received: by mail-pf1-x449.google.com with SMTP id n4-20020aa79044000000b004bcd447b6easo784393pfo.22 for ; Tue, 04 Jan 2022 11:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=T6hXHkZPRWaJl03x2QXMcgYQnVlGJ4p7Dp80AmXpDqA=; b=AJ0bPZ1NpwYWYRZhLndCTSqogOo7XiUaZ/UjLqVU7cHLs9Mdi7SUhYWX2x/576gx2r tCLIGd6Pr6yHqtDaYDXsqcwF6ITe6QPsyRqxaOReY21N7Kl6+Sx0+V0uK2csFJY6XybX 0xVsPtfmN+qRC5kGYfgt0H1p8vYf+hx+DY3VgQn157Yrt9QxI7PwsTwKW/eYXwq/OMsP Se9XKtz2lEF3/2kC0pimss9ZxccQiX4bCZtcruP4575qQvSGJySRVLFi2vqkcLM772ha kFILLe4Btz7d++g14WBdW4sIHMdzE6yJ71iPC6HdvWb7M4xW8tOAl5X7Pubxi3+fJov5 AKjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=T6hXHkZPRWaJl03x2QXMcgYQnVlGJ4p7Dp80AmXpDqA=; b=NwISXiu4nclNEXZ9tkO2F8txHksc7VVHd3bDdqWnP22dlp04m4jmfb+i2EBqycCdLE kKYcWnnRaVVxkerlUNFth8ILiXjOCtGnAc+4uWXP0UJ5yf3rpChC8QO/g6hndqKfJwve F39zvblIiIwO/kWNOaAhCx6KVKdJ2v7UqJwsBLEqGkv58KGsl7772pkxGWIX8vKiS2oZ L5Kd8Mq+aPTHvYxJO3Rh0A43tit4eqAkfXRFK1amlJ5sE0E7s4/Fpms0AhWIvXa6fBJF evyQMvDKn7HAkq/BAQDh4SXo88wd18mPmcyUOfF52UInyahxPFose01DWk5pUppv/852 h8lQ== X-Gm-Message-State: AOAM530QkW7zNZus7aVLTsZwUkWEg7qbjgsZKNE0khks0yISAi3WSfyJ +JGLhcoYYEzDXwNm4HSHqXTjC3J3RDLt X-Google-Smtp-Source: ABdhPJwQF9Sh0A8e10VxttETJKJYLzfkIBz9hQW4ADfKatROuxTA+/JgjcWs4dTYR/RUwb0w/HuKzInAFEzp X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a05:6a00:139b:b0:4ba:a476:364e with SMTP id t27-20020a056a00139b00b004baa476364emr52491553pfg.59.1641325787730; Tue, 04 Jan 2022 11:49:47 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:15 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-9-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 08/11] Docs: KVM: Rename psci.rst to hypercalls.rst From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the doc now covers more of general hypercalls' details, rather than just PSCI, rename the file to a more appropriate name- hypercalls.rst. Signed-off-by: Raghavendra Rao Ananta --- Documentation/virt/kvm/arm/{psci.rst =3D> hypercalls.rst} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/virt/kvm/arm/{psci.rst =3D> hypercalls.rst} (100%) diff --git a/Documentation/virt/kvm/arm/psci.rst b/Documentation/virt/kvm/a= rm/hypercalls.rst similarity index 100% rename from Documentation/virt/kvm/arm/psci.rst rename to Documentation/virt/kvm/arm/hypercalls.rst --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1FB8C433EF for ; Tue, 4 Jan 2022 19:50:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232385AbiADTuP (ORCPT ); Tue, 4 Jan 2022 14:50:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232058AbiADTtz (ORCPT ); Tue, 4 Jan 2022 14:49:55 -0500 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE771C0617A0 for ; Tue, 4 Jan 2022 11:49:50 -0800 (PST) Received: by mail-pf1-x44a.google.com with SMTP id f5-20020a62db05000000b004ba9efaaf08so18989868pfg.10 for ; Tue, 04 Jan 2022 11:49:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Qh+Ta1S1fpLiR/qxOoRTJEsN2xZx8MgQiasnAqhdpKI=; b=qodIf5Sp0toMDWuz4GnHwkIJE7T0eJwJj7XdaK4HqwgEu61RrjXaMGtG5bAQYFHgVU XQcbOArXF9hWDYXtgUBPFe5RyyNHqj8HKDG02or+gF7hxJERFIWFsZHnwRYBGF2RrLA7 prLizFfZU0oVimzxlpTk/p/99n5bho38zEkuFfff1jJdzeML07UR8iJYyS1CtXONZ5rs AljuEwculfNWBzfaqhoKHArHZUo3q3zZwuRTeLhq13TdxnCWghpnjMsPTu2eprtgW5nZ jWzFSYNxr+6LetRwqZtkS11nYTGkvBl4tJTOFtZyoV7NLuTS/ruVNZ1ISutQcLymDVfF m1jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Qh+Ta1S1fpLiR/qxOoRTJEsN2xZx8MgQiasnAqhdpKI=; b=wE+E/hCNDi7f4ZIWF3bs0XB4BEi0c7AjI68XUDHy/OPqG5OW0xmBNwpqeh7V3ziqx+ YPb4jXQwbDEEonXm1q0+tab3TYvporYruvtI/0uD0c5TnUJAOtH7TYL+tXZjIHvh5W7o EAucMkF05FhTwedNx6GXeffslAO9NLs9f6a+TpjZ+BQh+KoWr0PvHZWIvhXQDYxScgJi Nwmw0HiVSI1YKlgWYO4fO7OrRf5KUDpsBAyF7NlgZWo1NCSNusqPQDP30apU5gKz2wfj GPe0Z03wzggrtS8J5CY0ZR70Z+OF8FwekE63oNLR74Alnm9nTxnklkFGelIMJfJimi8L Ogug== X-Gm-Message-State: AOAM5315CWRRy4PNZJJ5ZymPqqpwvfQULw0V4CHpGbK4Y0qOUZwmFJrf NBPlylZoHJPo6dWrqBnm/Hr9XAMTTVy3 X-Google-Smtp-Source: ABdhPJzEcOK1lKVsqRgejas/1/ODbiZ6XD+PSPqokzg/dQ4xnV0fHqas6nJzWvta/wCbrQlVjD2PNFNdskdz X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:aa7:9f09:0:b0:4bc:683b:439 with SMTP id g9-20020aa79f09000000b004bc683b0439mr22142412pfr.86.1641325790162; Tue, 04 Jan 2022 11:49:50 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:16 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-10-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 09/11] tools: Import ARM SMCCC definitions From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Import the standard SMCCC definitions from include/linux/arm-smccc.h. Signed-off-by: Raghavendra Rao Ananta --- tools/include/linux/arm-smccc.h | 188 ++++++++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 tools/include/linux/arm-smccc.h diff --git a/tools/include/linux/arm-smccc.h b/tools/include/linux/arm-smcc= c.h new file mode 100644 index 000000000000..a11c0bbabd5b --- /dev/null +++ b/tools/include/linux/arm-smccc.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015, Linaro Limited + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +#include + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * https://developer.arm.com/docs/den0028/latest + * + * This code is up-to-date with version DEN 0028 C + */ + +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_STANDARD_HYP 5 +#define ARM_SMCCC_OWNER_VENDOR_HYP 6 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01 + +#define ARM_SMCCC_QUIRK_NONE 0 +#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ + +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 +#define ARM_SMCCC_VERSION_1_2 0x10002 +#define ARM_SMCCC_VERSION_1_3 0x10003 + +#define ARM_SMCCC_1_3_SVE_HINT 0x10000 + +#define ARM_SMCCC_VERSION_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0) + +#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 1) + +#define ARM_SMCCC_ARCH_SOC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 2) + +#define ARM_SMCCC_ARCH_WORKAROUND_1 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x8000) + +#define ARM_SMCCC_ARCH_WORKAROUND_2 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x7fff) + +#define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + ARM_SMCCC_FUNC_QUERY_CALL_UID) + +/* KVM UID value: 28b46fb6-2ec5-11e9-a9ca-4b564d003a74 */ +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0 0xb66fb428U +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1 0xe911c52eU +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_2 0x564bcaa9U +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_3 0x743a004dU + +/* KVM "vendor specific" services */ +#define ARM_SMCCC_KVM_FUNC_FEATURES 0 +#define ARM_SMCCC_KVM_FUNC_PTP 1 +#define ARM_SMCCC_KVM_FUNC_FEATURES_2 127 +#define ARM_SMCCC_KVM_NUM_FUNCS 128 + +#define ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + ARM_SMCCC_KVM_FUNC_FEATURES) + +#define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED 1 + +/* + * ptp_kvm is a feature used for time sync between vm and host. + * ptp_kvm module in guest kernel will get service from host using + * this hypercall ID. + */ +#define ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + ARM_SMCCC_KVM_FUNC_PTP) + +/* ptp_kvm counter type ID */ +#define KVM_PTP_VIRT_COUNTER 0 +#define KVM_PTP_PHYS_COUNTER 1 + +/* Paravirtualised time calls (defined by ARM DEN0057A) */ +#define ARM_SMCCC_HV_PV_TIME_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD_HYP, \ + 0x20) + +#define ARM_SMCCC_HV_PV_TIME_ST \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD_HYP, \ + 0x21) + +/* TRNG entropy source calls (defined by ARM DEN0098) */ +#define ARM_SMCCC_TRNG_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x50) + +#define ARM_SMCCC_TRNG_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x51) + +#define ARM_SMCCC_TRNG_GET_UUID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x52) + +#define ARM_SMCCC_TRNG_RND32 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x53) + +#define ARM_SMCCC_TRNG_RND64 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x53) + +/* + * Return codes defined in ARM DEN 0070A + * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C + */ +#define SMCCC_RET_SUCCESS 0 +#define SMCCC_RET_NOT_SUPPORTED -1 +#define SMCCC_RET_NOT_REQUIRED -2 +#define SMCCC_RET_INVALID_PARAMETER -3 + +#endif /*__LINUX_ARM_SMCCC_H*/ --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=OKuVphlnu4rk/jRKph0yCcFS6yDHp3kGjcHbTzf7Ozk=; b=lYtsmMoZFeMzSsESHg/NOQkb3EDVKPeOmXaQK2dtbU98FNxhwKlx8uK0/z5bbFWXep nL0Hv9D8JqyrE9loCYE26pX+MELpZ/G4aBIT6x/eX7xBhkYpAeku/SW7TEIkDKcMDcxa 7DcctkVzJUONxNqxqyHum0cBvUt1/0hcJL6mDm+hAkI+q7LCl6/mRwsGwWgqODSn0/Ok sBbsBnjIBfIbK8WjE2ieyT7p6/Nz10ucCg4UkWEcaBbmacnQNgEEa+7fuAG9Kd+1HNwW CYvI6ON/agkm8tiMM/Cj+SIfO/VTY/4VEJuSqGujUSXtxWa8sSr6FdfBLEhyp+cgeVU0 5Oyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=OKuVphlnu4rk/jRKph0yCcFS6yDHp3kGjcHbTzf7Ozk=; b=ujiMVOXUX72PZkzIcSWJyL2375lnR47OnLAQBx1diVGyeApU0xWoej3Re/ghpZ30fZ 0fSoSaoYRHxjnrXCFdSi8NpSq+zh1EWRuy6rVgNxob/fuEdHBTanR/xxprwrG2XPrGnH 205gCBQ08E+/mE4imF9Gvf/HXiIi1005lf/9gy19fUk6H4QMMPX+Gds7iTP/s3zW//+x /InFvwvf5Hn6DcYsuzlV8pOp0bNZFHuNd5Wc3FZWmd83zHCa18wn0OTExxXMOFQB/If+ Urb152eZ9l8moCFQfdPmfCLooOqM0d11LMe5zaDTz89csfBu8UKajRm8issrjXKY7CQO 9GnQ== X-Gm-Message-State: AOAM533V31PenOq9/rt8IDmhchznu0lP3ra5p+ztsf9p8ieRU2dR7YTA V2x41QYqOHEYHJKUFAn3qJKf2NtEPPPd X-Google-Smtp-Source: ABdhPJybXe3CmtQCeJ2OE6n2CiN0QtTrY1mwjxcpcnUzkJ/vtS+VM6/Kq4TPu2f6P1d9Ryn0a5GUdH11/yAa X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:d512:b0:149:3915:6537 with SMTP id b18-20020a170902d51200b0014939156537mr52444403plg.152.1641325792458; Tue, 04 Jan 2022 11:49:52 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:17 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-11-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 10/11] selftests: KVM: aarch64: Introduce hypercall ABI test From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a KVM selftest to check the hypercall interface for arm64 platforms. The test validates the user-space's IOCTL interface to read/write the psuedo-firmware registers as well as its effects on the guest upon certain configurations. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/hypercalls.c | 358 ++++++++++++++++++ 3 files changed, 360 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/hypercalls.c diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftes= ts/kvm/.gitignore index 99ed78ddd63f..bdecb27411ad 100644 --- a/tools/testing/selftests/kvm/.gitignore +++ b/tools/testing/selftests/kvm/.gitignore @@ -2,6 +2,7 @@ /aarch64/arch_timer /aarch64/debug-exceptions /aarch64/get-reg-list +/aarch64/hypercalls /aarch64/psci_test /aarch64/vgic_init /s390x/memop diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 5be2690168a8..ea96a92493d5 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -94,6 +94,7 @@ TEST_GEN_PROGS_x86_64 +=3D system_counter_offset_test TEST_GEN_PROGS_aarch64 +=3D aarch64/arch_timer TEST_GEN_PROGS_aarch64 +=3D aarch64/debug-exceptions TEST_GEN_PROGS_aarch64 +=3D aarch64/get-reg-list +TEST_GEN_PROGS_aarch64 +=3D aarch64/hypercalls TEST_GEN_PROGS_aarch64 +=3D aarch64/psci_test TEST_GEN_PROGS_aarch64 +=3D aarch64/vgic_init TEST_GEN_PROGS_aarch64 +=3D demand_paging_test diff --git a/tools/testing/selftests/kvm/aarch64/hypercalls.c b/tools/testi= ng/selftests/kvm/aarch64/hypercalls.c new file mode 100644 index 000000000000..386f754ca99d --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/hypercalls.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +#include "processor.h" + +#define FW_REG_ULIMIT_VAL(max_feat_bit) (GENMASK_ULL(max_feat_bit, 0)) + +struct kvm_fw_reg_info { + uint64_t reg; /* Register definition */ + uint64_t max_feat_bit; /* Bit that represents the upper limit of the feat= ure-map */ +}; + +#define FW_REG_INFO(r, bit_max) \ + { \ + .reg =3D r, \ + .max_feat_bit =3D bit_max, \ + } + +static const struct kvm_fw_reg_info fw_reg_info[] =3D { + FW_REG_INFO(KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_BMAP_BIT_MAX), + FW_REG_INFO(KVM_REG_ARM_STD_HYP_BMAP, KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX), + FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP, KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_= MAX), +}; + +enum test_stage { + TEST_STAGE_REG_IFACE, + TEST_STAGE_HVC_IFACE_FEAT_DISABLED, + TEST_STAGE_HVC_IFACE_FEAT_ENABLED, + TEST_STAGE_END, +}; + +static int stage; + +struct test_hvc_info { + uint32_t func_id; + int64_t arg0; + + void (*test_hvc_disabled)(const struct test_hvc_info *hc_info, + struct arm_smccc_res *res); + void (*test_hvc_enabled)(const struct test_hvc_info *hc_info, + struct arm_smccc_res *res); +}; + +#define TEST_HVC_INFO(f, a0, test_disabled, test_enabled) \ + { \ + .func_id =3D f, \ + .arg0 =3D a0, \ + .test_hvc_disabled =3D test_disabled, \ + .test_hvc_enabled =3D test_enabled, \ + } + +static void +test_ptp_feat_hvc_disabled(const struct test_hvc_info *hc_info, struct arm= _smccc_res *res) +{ + GUEST_ASSERT_3((res->a0 & BIT(ARM_SMCCC_KVM_FUNC_PTP)) =3D=3D 0, + res->a0, hc_info->func_id, hc_info->arg0); +} + +static void +test_ptp_feat_hvc_enabled(const struct test_hvc_info *hc_info, struct arm_= smccc_res *res) +{ + GUEST_ASSERT_3((res->a0 & BIT(ARM_SMCCC_KVM_FUNC_PTP)) !=3D 0, + res->a0, hc_info->func_id, hc_info->arg0); +} + +static const struct test_hvc_info hvc_info[] =3D { + /* KVM_REG_ARM_STD_BMAP: KVM_REG_ARM_STD_BIT_TRNG_V1_0 */ + TEST_HVC_INFO(ARM_SMCCC_TRNG_VERSION, 0, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND64, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_GET_UUID, 0, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_RND32, 0, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_RND64, 0, NULL, NULL), + + /* KVM_REG_ARM_STD_HYP_BMAP: KVM_REG_ARM_STD_HYP_BIT_PV_TIME */ + TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_HV_PV_TIME_FEATURES, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, + ARM_SMCCC_HV_PV_TIME_ST, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_ST, 0, NULL, NULL), + + /* KVM_REG_ARM_VENDOR_HYP_BMAP: KVM_REG_ARM_VENDOR_HYP_BIT_PTP */ + TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID, + ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, + test_ptp_feat_hvc_disabled, test_ptp_feat_hvc_enabled), + TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, + KVM_PTP_VIRT_COUNTER, NULL, NULL), +}; + +static void guest_test_hvc(int stage) +{ + unsigned int i; + struct arm_smccc_res res; + + for (i =3D 0; i < ARRAY_SIZE(hvc_info); i++) { + const struct test_hvc_info *hc_info =3D &hvc_info[i]; + + memset(&res, 0, sizeof(res)); + smccc_hvc(hc_info->func_id, hc_info->arg0, 0, 0, 0, 0, 0, 0, &res); + + switch (stage) { + case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: + if (hc_info->test_hvc_disabled) + hc_info->test_hvc_disabled(hc_info, &res); + else + GUEST_ASSERT_3(res.a0 =3D=3D SMCCC_RET_NOT_SUPPORTED, + res.a0, hc_info->func_id, hc_info->arg0); + break; + case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: + if (hc_info->test_hvc_enabled) + hc_info->test_hvc_enabled(hc_info, &res); + else + GUEST_ASSERT_3(res.a0 !=3D SMCCC_RET_NOT_SUPPORTED, + res.a0, hc_info->func_id, hc_info->arg0); + break; + default: + GUEST_ASSERT_1(0, stage); + } + } +} + +static void guest_code(void) +{ + while (stage !=3D TEST_STAGE_END) { + switch (stage) { + case TEST_STAGE_REG_IFACE: + break; + case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: + case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: + guest_test_hvc(stage); + break; + default: + GUEST_ASSERT_1(0, stage); + } + + GUEST_SYNC(stage); + } + + GUEST_DONE(); +} + +static int set_fw_reg(struct kvm_vm *vm, uint64_t id, uint64_t val) +{ + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM_FW_REG(id), + .addr =3D (uint64_t)&val, + }; + + return _vcpu_ioctl(vm, 0, KVM_SET_ONE_REG, ®); +} + +static void get_fw_reg(struct kvm_vm *vm, uint64_t id, uint64_t *addr) +{ + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM_FW_REG(id), + .addr =3D (uint64_t)addr, + }; + + return vcpu_ioctl(vm, 0, KVM_GET_ONE_REG, ®); +} + +struct st_time { + uint32_t rev; + uint32_t attr; + uint64_t st_time; +}; + +#define STEAL_TIME_SIZE ((sizeof(struct st_time) + 63) & ~63) +#define ST_GPA_BASE (1 << 30) + +static void steal_time_init(struct kvm_vm *vm) +{ + uint64_t st_ipa =3D (ulong)ST_GPA_BASE; + unsigned int gpages; + struct kvm_device_attr dev =3D { + .group =3D KVM_ARM_VCPU_PVTIME_CTRL, + .attr =3D KVM_ARM_VCPU_PVTIME_IPA, + .addr =3D (uint64_t)&st_ipa, + }; + + gpages =3D vm_calc_num_guest_pages(VM_MODE_DEFAULT, STEAL_TIME_SIZE); + vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, ST_GPA_BASE, 1, gpa= ges, 0); + + vcpu_ioctl(vm, 0, KVM_SET_DEVICE_ATTR, &dev); +} + +static void test_fw_regs_before_vm_start(struct kvm_vm *vm) +{ + uint64_t val; + unsigned int i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(fw_reg_info); i++) { + const struct kvm_fw_reg_info *reg_info =3D &fw_reg_info[i]; + + /* First read should be an upper limit of the features supported */ + get_fw_reg(vm, reg_info->reg, &val); + TEST_ASSERT(val =3D=3D FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), + "Expected all the features to be set for reg: 0x%lx; expected: 0x%llx; = read: 0x%lx\n", + reg_info->reg, GENMASK_ULL(reg_info->max_feat_bit, 0), val); + + /* Test 'write' by disabling all the features of the register map */ + ret =3D set_fw_reg(vm, reg_info->reg, 0); + TEST_ASSERT(ret =3D=3D 0, + "Failed to clear all the features of reg: 0x%lx; ret: %d\n", + reg_info->reg, errno); + + get_fw_reg(vm, reg_info->reg, &val); + TEST_ASSERT(val =3D=3D 0, + "Expected all the features to be cleared for reg: 0x%lx\n", reg_info->r= eg); + + /* + * Test enabling a feature that's not supported. + * Avoid this check if all the bits are occupied. + */ + if (reg_info->max_feat_bit < 63) { + ret =3D set_fw_reg(vm, reg_info->reg, BIT(reg_info->max_feat_bit + 1)); + TEST_ASSERT(ret !=3D 0 && errno =3D=3D EINVAL, + "Unexpected behavior or return value (%d) while setting an unsupported = feature for reg: 0x%lx\n", + errno, reg_info->reg); + } + } +} + +static void test_fw_regs_after_vm_start(struct kvm_vm *vm) +{ + uint64_t val; + unsigned int i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(fw_reg_info); i++) { + const struct kvm_fw_reg_info *reg_info =3D &fw_reg_info[i]; + + /* + * Before starting the VM, the test clears all the bits. + * Check if that's still the case. + */ + get_fw_reg(vm, reg_info->reg, &val); + TEST_ASSERT(val =3D=3D 0, + "Expected all the features to be cleared for reg: 0x%lx\n", + reg_info->reg); + + /* + * Test setting the last known value. KVM should allow this + * even if VM has started running. + */ + ret =3D set_fw_reg(vm, reg_info->reg, val); + TEST_ASSERT(ret =3D=3D 0, + "Failed to clear all the features of reg: 0x%lx; ret: %d\n", + reg_info->reg, errno); + + /* + * Set all the features for this register again. KVM shouldn't + * allow this as the VM is running. + */ + ret =3D set_fw_reg(vm, reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_fe= at_bit)); + TEST_ASSERT(ret !=3D 0 && errno =3D=3D EBUSY, + "Unexpected behavior or return value (%d) while setting a feature while = VM is running for reg: 0x%lx\n", + errno, reg_info->reg); + } +} + +static struct kvm_vm *test_vm_create(void) +{ + struct kvm_vm *vm; + + vm =3D vm_create_default(0, 0, guest_code); + + ucall_init(vm, NULL); + steal_time_init(vm); + + return vm; +} + +static struct kvm_vm *test_guest_stage(struct kvm_vm *vm) +{ + struct kvm_vm *ret_vm =3D vm; + + pr_debug("Stage: %d\n", stage); + + switch (stage) { + case TEST_STAGE_REG_IFACE: + test_fw_regs_after_vm_start(vm); + break; + case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: + /* Start a new VM so that all the features are now enabled by default */ + kvm_vm_free(vm); + ret_vm =3D test_vm_create(); + break; + case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: + break; + default: + TEST_FAIL("Unknown test stage: %d\n", stage); + } + + stage++; + sync_global_to_guest(vm, stage); + + return ret_vm; +} + +static void test_run(void) +{ + struct kvm_vm *vm; + struct ucall uc; + bool guest_done =3D false; + + vm =3D test_vm_create(); + + test_fw_regs_before_vm_start(vm); + + while (!guest_done) { + vcpu_run(vm, 0); + + switch (get_ucall(vm, 0, &uc)) { + case UCALL_SYNC: + vm =3D test_guest_stage(vm); + break; + case UCALL_DONE: + guest_done =3D true; + break; + case UCALL_ABORT: + TEST_FAIL("%s at %s:%ld\n\tvalues: 0x%lx, %lu; %lu, stage: %u", + (const char *)uc.args[0], __FILE__, uc.args[1], + uc.args[2], uc.args[3], uc.args[4], stage); + break; + default: + TEST_FAIL("Unexpected guest exit\n"); + } + } + + kvm_vm_free(vm); +} + +int main(void) +{ + unsigned int num_fw_bmap_regs; + + setbuf(stdout, NULL); + + num_fw_bmap_regs =3D kvm_check_cap(KVM_CAP_ARM_HVC_FW_REG_BMAP); + if (!num_fw_bmap_regs) { + print_skip("ARM64 fw registers bitmap not supported\n"); + exit(KSFT_SKIP); + } else if (num_fw_bmap_regs !=3D ARRAY_SIZE(fw_reg_info)) { + print_skip("Mismatched fw registers between kernel (%u) and test (%lu)\n= ", + num_fw_bmap_regs, ARRAY_SIZE(fw_reg_info)); + exit(KSFT_SKIP); + } + + pr_info("Number of firmware bitmap registers discovered: %u\n", num_fw_bm= ap_regs); + + test_run(); + return 0; +} --=20 2.34.1.448.ga2b2bfdf31-goog From nobody Wed Jul 1 01:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E0F1C433EF for ; Tue, 4 Jan 2022 19:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231514AbiADTun (ORCPT ); Tue, 4 Jan 2022 14:50:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231964AbiADTuK (ORCPT ); Tue, 4 Jan 2022 14:50:10 -0500 Received: from mail-qt1-x84a.google.com (mail-qt1-x84a.google.com [IPv6:2607:f8b0:4864:20::84a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DCAFC06139C for ; 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Tue, 04 Jan 2022 11:49:54 -0800 (PST) Date: Tue, 4 Jan 2022 19:49:18 +0000 In-Reply-To: <20220104194918.373612-1-rananta@google.com> Message-Id: <20220104194918.373612-12-rananta@google.com> Mime-Version: 1.0 References: <20220104194918.373612-1-rananta@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v3 11/11] selftests: KVM: aarch64: Add the bitmap firmware registers to get-reg-list From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the psuedo-firmware registers KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, and KVM_REG_ARM_VENDOR_HYP_BMAP to the base_regs[] list. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/tes= ting/selftests/kvm/aarch64/get-reg-list.c index cc898181faab..6321f4472fdf 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -686,6 +686,9 @@ static __u64 base_regs[] =3D { KVM_REG_ARM_FW_REG(0), KVM_REG_ARM_FW_REG(1), KVM_REG_ARM_FW_REG(2), + KVM_REG_ARM_FW_REG(3), /* KVM_REG_ARM_STD_BMAP */ + KVM_REG_ARM_FW_REG(4), /* KVM_REG_ARM_STD_HYP_BMAP */ + KVM_REG_ARM_FW_REG(5), /* KVM_REG_ARM_VENDOR_HYP_BMAP */ ARM64_SYS_REG(3, 3, 14, 3, 1), /* CNTV_CTL_EL0 */ ARM64_SYS_REG(3, 3, 14, 3, 2), /* CNTV_CVAL_EL0 */ ARM64_SYS_REG(3, 3, 14, 0, 2), --=20 2.34.1.448.ga2b2bfdf31-goog