From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2E78C433F5 for ; Tue, 4 Jan 2022 08:01:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233791AbiADIBt (ORCPT ); Tue, 4 Jan 2022 03:01:49 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:33276 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233683AbiADIBr (ORCPT ); Tue, 4 Jan 2022 03:01:47 -0500 X-UUID: 02713625995c40a393f4fd473de133bc-20220104 X-UUID: 02713625995c40a393f4fd473de133bc-20220104 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1310995970; Tue, 04 Jan 2022 16:01:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:41 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:40 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , Steve Cho , , , , , , , Subject: [PATCH v3, 01/13] media: mtk-vcodec: Add vdec enable/disable hardware helpers Date: Tue, 4 Jan 2022 16:01:26 +0800 Message-ID: <20220104080138.7472-2-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Lock, power and clock are highly coupled operations. Adds vdec enable/disable hardware helpers and uses them. Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih --- .../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 5 - .../platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 168 +++++++++++------- .../platform/mtk-vcodec/mtk_vcodec_dec_pm.h | 6 +- .../media/platform/mtk-vcodec/vdec_drv_if.c | 20 +-- .../platform/mtk-vcodec/vdec_msg_queue.c | 2 + 5 files changed, 117 insertions(+), 84 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drive= rs/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index d44894fa2f6e..fc3e272d2059 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -195,9 +195,6 @@ static int fops_vcodec_open(struct file *file) mtk_vcodec_dec_set_default_params(ctx); =20 if (v4l2_fh_is_singular(&ctx->fh)) { - ret =3D mtk_vcodec_dec_pw_on(dev, MTK_VDEC_LAT0); - if (ret < 0) - goto err_load_fw; /* * Does nothing if firmware was already loaded. */ @@ -254,8 +251,6 @@ static int fops_vcodec_release(struct file *file) v4l2_m2m_ctx_release(ctx->m2m_ctx); mtk_vcodec_dec_release(ctx); =20 - if (v4l2_fh_is_singular(&ctx->fh)) - mtk_vcodec_dec_pw_off(dev, MTK_VDEC_LAT0); v4l2_fh_del(&ctx->fh); v4l2_fh_exit(&ctx->fh); v4l2_ctrl_handler_free(&ctx->ctrl_hdl); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/driver= s/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c index b9f5ef979c69..c2ed79bce686 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c @@ -80,74 +80,31 @@ int mtk_vcodec_init_dec_clk(struct platform_device *pde= v, } EXPORT_SYMBOL_GPL(mtk_vcodec_init_dec_clk); =20 -int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; int ret; =20 - if (vdec_dev->vdec_pdata->is_subdev_supported) { - subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { - mtk_v4l2_err("Failed to get hw dev\n"); - return -EINVAL; - } - pm =3D &subdev_dev->pm; - } else { - pm =3D &vdec_dev->pm; - } - ret =3D pm_runtime_resume_and_get(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_resume_and_get fail %d", ret); =20 return ret; } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_on); =20 -void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; int ret; =20 - if (vdec_dev->vdec_pdata->is_subdev_supported) { - subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { - mtk_v4l2_err("Failed to get hw dev\n"); - return; - } - pm =3D &subdev_dev->pm; - } else { - pm =3D &vdec_dev->pm; - } - ret =3D pm_runtime_put_sync(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_off); =20 -void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; struct mtk_vcodec_clk *dec_clk; int ret, i; =20 - if (vdec_dev->vdec_pdata->is_subdev_supported) { - subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { - mtk_v4l2_err("Failed to get hw dev\n"); - return; - } - pm =3D &subdev_dev->pm; - enable_irq(subdev_dev->dec_irq); - } else { - pm =3D &vdec_dev->pm; - enable_irq(vdec_dev->dec_irq); - } - dec_clk =3D &pm->vdec_clk; for (i =3D 0; i < dec_clk->clk_num; i++) { ret =3D clk_prepare_enable(dec_clk->clk_info[i].vcodec_clk); @@ -169,31 +126,120 @@ void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *= vdec_dev, int hw_idx) for (i -=3D 1; i >=3D 0; i--) clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_on); =20 -void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; struct mtk_vcodec_clk *dec_clk; int i; =20 + dec_clk =3D &pm->vdec_clk; + mtk_smi_larb_put(pm->larbvdec); + for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) + clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); +} + +static void mtk_vcodec_dec_enable_irq(struct mtk_vcodec_dev *vdec_dev, int= hw_idx) + { + struct mtk_vdec_hw_dev *subdev_dev; + + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) + return; + if (vdec_dev->vdec_pdata->is_subdev_supported) { subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { + if (subdev_dev) + enable_irq(subdev_dev->dec_irq); + else + mtk_v4l2_err("Failed to get hw dev\n"); + } else { + enable_irq(vdec_dev->dec_irq); + } +} + +static void mtk_vcodec_dec_disable_irq(struct mtk_vcodec_dev *vdec_dev, in= t hw_idx) +{ + struct mtk_vdec_hw_dev *subdev_dev; + + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) + return; + + if (vdec_dev->vdec_pdata->is_subdev_supported) { + subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); + if (subdev_dev) + disable_irq(subdev_dev->dec_irq); + else mtk_v4l2_err("Failed to get hw dev\n"); - return; - } - pm =3D &subdev_dev->pm; - disable_irq(subdev_dev->dec_irq); } else { - pm =3D &vdec_dev->pm; disable_irq(vdec_dev->dec_irq); } +} =20 - dec_clk =3D &pm->vdec_clk; - mtk_smi_larb_put(pm->larbvdec); - for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) - clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); +static struct mtk_vcodec_pm *mtk_vcodec_dec_get_pm(struct mtk_vcodec_dev *= vdec_dev, + int hw_idx) +{ + struct mtk_vdec_hw_dev *subdev_dev; + + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) + return NULL; + + if (vdec_dev->vdec_pdata->is_subdev_supported) { + subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); + if (subdev_dev) + return &subdev_dev->pm; + + mtk_v4l2_err("Failed to get hw dev\n"); + return NULL; + } + + return &vdec_dev->pm; +} + +static void mtk_vcodec_dec_child_dev_on(struct mtk_vcodec_dev *vdec_dev, + int hw_idx) +{ + struct mtk_vcodec_pm *pm; + + pm =3D mtk_vcodec_dec_get_pm(vdec_dev, hw_idx); + if (pm) { + mtk_vcodec_dec_pw_on(pm); + mtk_vcodec_dec_clock_on(pm); + } +} + +static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev, + int hw_idx) +{ + struct mtk_vcodec_pm *pm; + + pm =3D mtk_vcodec_dec_get_pm(vdec_dev, hw_idx); + if (pm) { + mtk_vcodec_dec_clock_off(pm); + mtk_vcodec_dec_pw_off(pm); + } +} + +void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx) +{ + mutex_lock(&ctx->dev->dec_mutex[hw_idx]); + + if (IS_VDEC_LAT_ARCH(ctx->dev->vdec_pdata->hw_arch) && + hw_idx =3D=3D MTK_VDEC_CORE) + mtk_vcodec_dec_child_dev_on(ctx->dev, MTK_VDEC_LAT0); + mtk_vcodec_dec_child_dev_on(ctx->dev, hw_idx); + + mtk_vcodec_dec_enable_irq(ctx->dev, hw_idx); +} +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_enable_hardware); + +void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_id= x) +{ + mtk_vcodec_dec_disable_irq(ctx->dev, hw_idx); + + mtk_vcodec_dec_child_dev_off(ctx->dev, hw_idx); + if (IS_VDEC_LAT_ARCH(ctx->dev->vdec_pdata->hw_arch) && + hw_idx =3D=3D MTK_VDEC_CORE) + mtk_vcodec_dec_child_dev_off(ctx->dev, MTK_VDEC_LAT0); + + mutex_unlock(&ctx->dev->dec_mutex[hw_idx]); } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_off); +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_disable_hardware); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h b/driver= s/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h index c4121df9764f..b420739b373d 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h @@ -12,9 +12,7 @@ int mtk_vcodec_init_dec_clk(struct platform_device *pdev, struct mtk_vcodec_pm *pm); =20 -int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx); -void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx); -void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx); -void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx); +void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx= ); +void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_id= x); =20 #endif /* _MTK_VCODEC_DEC_PM_H_ */ diff --git a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c b/drivers/medi= a/platform/mtk-vcodec/vdec_drv_if.c index 05a5b240e906..c93dd0ea3537 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec_drv_if.c @@ -38,11 +38,9 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned in= t fourcc) return -EINVAL; } =20 - mtk_vdec_lock(ctx); - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); ret =3D ctx->dec_if->init(ctx); - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); - mtk_vdec_unlock(ctx); + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); =20 return ret; } @@ -70,15 +68,11 @@ int vdec_if_decode(struct mtk_vcodec_ctx *ctx, struct m= tk_vcodec_mem *bs, if (!ctx->drv_handle) return -EIO; =20 - mtk_vdec_lock(ctx); - + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); mtk_vcodec_set_curr_ctx(ctx->dev, ctx, ctx->hw_id); - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); ret =3D ctx->dec_if->decode(ctx->drv_handle, bs, fb, res_chg); - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); mtk_vcodec_set_curr_ctx(ctx->dev, NULL, ctx->hw_id); - - mtk_vdec_unlock(ctx); + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); =20 return ret; } @@ -103,11 +97,9 @@ void vdec_if_deinit(struct mtk_vcodec_ctx *ctx) if (!ctx->drv_handle) return; =20 - mtk_vdec_lock(ctx); - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); ctx->dec_if->deinit(ctx->drv_handle); - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); - mtk_vdec_unlock(ctx); + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); =20 ctx->drv_handle =3D NULL; } diff --git a/drivers/media/platform/mtk-vcodec/vdec_msg_queue.c b/drivers/m= edia/platform/mtk-vcodec/vdec_msg_queue.c index 576e08200a10..900d04fd4e66 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_msg_queue.c +++ b/drivers/media/platform/mtk-vcodec/vdec_msg_queue.c @@ -212,11 +212,13 @@ static void vdec_msg_queue_core_work(struct work_stru= ct *work) return; =20 ctx =3D lat_buf->ctx; + mtk_vcodec_dec_enable_hardware(ctx, MTK_VDEC_CORE); mtk_vcodec_set_curr_ctx(dev, ctx, MTK_VDEC_CORE); =20 lat_buf->core_decode(lat_buf); =20 mtk_vcodec_set_curr_ctx(dev, NULL, MTK_VDEC_CORE); + mtk_vcodec_dec_disable_hardware(ctx, MTK_VDEC_CORE); vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); =20 if (!list_empty(&ctx->msg_queue.lat_ctx.ready_queue)) { --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3250FC4332F for ; Tue, 4 Jan 2022 08:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233803AbiADIBv (ORCPT ); Tue, 4 Jan 2022 03:01:51 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52670 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232800AbiADIBs (ORCPT ); Tue, 4 Jan 2022 03:01:48 -0500 X-UUID: 3786ccecbbc341e28c41f245be610e9a-20220104 X-UUID: 3786ccecbbc341e28c41f245be610e9a-20220104 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 988934347; Tue, 04 Jan 2022 16:01:45 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:44 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:43 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:41 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 02/13] media: mtk-vcodec: Using firmware type to separate different firmware architecture Date: Tue, 4 Jan 2022 16:01:27 +0800 Message-ID: <20220104080138.7472-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT8173 platform use vpu firmware, mt8183/mt8192 will use scp firmware instead, using chip name is not reasonable to separate different firmware architecture. Using firmware type is much better. Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c | 1 - .../media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c | 2 -- drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 2 -- drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.c | 6 ++++++ drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.h | 1 + drivers/media/platform/mtk-vcodec/vdec_vpu_if.c | 4 ++-- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c b/= drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c index 04ca43c77e5f..7966c132be8f 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c @@ -613,7 +613,6 @@ static struct vb2_ops mtk_vdec_frame_vb2_ops =3D { }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata =3D { - .chip =3D MTK_MT8173, .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_frame_vb2_ops, diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c b= /drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c index 23d997ac114d..5aebf88f997b 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c @@ -343,7 +343,6 @@ static struct vb2_ops mtk_vdec_request_vb2_ops =3D { }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata =3D { - .chip =3D MTK_MT8183, .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, @@ -362,7 +361,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { =20 /* This platform data is used for one lat and one core architecture. */ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata =3D { - .chip =3D MTK_MT8192, .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_drv.h index 3fc747cea5c9..a23a7646437c 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -367,7 +367,6 @@ enum mtk_vdec_hw_arch { * @vdec_framesizes: supported video decoder frame sizes * @num_framesizes: count of video decoder frame sizes * - * @chip: chip this decoder is compatible with * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_c= ore * * @is_subdev_supported: whether support parent-node architecture(subdev) @@ -390,7 +389,6 @@ struct mtk_vcodec_dec_pdata { const struct mtk_codec_framesizes *vdec_framesizes; const int num_framesizes; =20 - enum mtk_chip chip; enum mtk_vdec_hw_arch hw_arch; =20 bool is_subdev_supported; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.c b/drivers/me= dia/platform/mtk-vcodec/mtk_vcodec_fw.c index 94b39ae5c2e1..556e54aadac9 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.c @@ -65,3 +65,9 @@ int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int = id, void *buf, return fw->ops->ipi_send(fw, id, buf, len, wait); } EXPORT_SYMBOL_GPL(mtk_vcodec_fw_ipi_send); + +int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw) +{ + return fw->type; +} +EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_type); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.h b/drivers/me= dia/platform/mtk-vcodec/mtk_vcodec_fw.h index 539bb626772c..acd355961e3a 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_fw.h @@ -39,5 +39,6 @@ int mtk_vcodec_fw_ipi_register(struct mtk_vcodec_fw *fw, = int id, const char *name, void *priv); int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id, void *buf, unsigned int len, unsigned int wait); +int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw); =20 #endif /* _MTK_VCODEC_FW_H_ */ diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/medi= a/platform/mtk-vcodec/vdec_vpu_if.c index c84fac52fe26..21f6d9c5a371 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c @@ -33,8 +33,8 @@ static void handle_init_ack_msg(const struct vdec_vpu_ipi= _init_ack *msg) */ vpu->inst_id =3D 0xdeadbeef; =20 - /* Firmware version field does not exist on MT8173. */ - if (vpu->ctx->dev->vdec_pdata->chip =3D=3D MTK_MT8173) + /* VPU firmware does not contain a version field. */ + if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) =3D=3D VPU) return; =20 /* Check firmware version. */ --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FDC2C433FE for ; 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Tue, 4 Jan 2022 16:01:44 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:43 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 03/13] media: mtk-vcodec: get capture queue buffer size from scp Date: Tue, 4 Jan 2022 16:01:28 +0800 Message-ID: <20220104080138.7472-4-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Different capture buffer format has different buffer size, need to get real buffer size according to buffer type from scp. Signed-off-by: Yunfei Dong --- comments: +static void handle_get_param_msg_ack( + const struct vdec_vpu_ipi_get_param_ack *msg) +{ + struct vdec_vpu_inst *vpu =3D (struct vdec_vpu_inst *) + (unsigned long)msg->ap_inst_addr; > ap inst addr is uint64_t, but for 32bit system, only use 32bit address, s= o add unsigned long. + case GET_PARAM_PIC_INFO: + vpu->fb_sz[0] =3D msg->data[0]; + vpu->fb_sz[1] =3D msg->data[1]; > fb_sz is used here. --- .../media/platform/mtk-vcodec/vdec_ipi_msg.h | 37 ++++++++++++++ .../media/platform/mtk-vcodec/vdec_vpu_if.c | 51 +++++++++++++++++++ .../media/platform/mtk-vcodec/vdec_vpu_if.h | 15 ++++++ 3 files changed, 103 insertions(+) diff --git a/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h b/drivers/med= ia/platform/mtk-vcodec/vdec_ipi_msg.h index 5daca8d52ebb..476fc5777a0f 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h +++ b/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h @@ -20,6 +20,7 @@ enum vdec_ipi_msgid { AP_IPIMSG_DEC_RESET =3D 0xA004, AP_IPIMSG_DEC_CORE =3D 0xA005, AP_IPIMSG_DEC_CORE_END =3D 0xA006, + AP_IPIMSG_DEC_GET_PARAM =3D 0xA007, =20 VPU_IPIMSG_DEC_INIT_ACK =3D 0xB000, VPU_IPIMSG_DEC_START_ACK =3D 0xB001, @@ -28,6 +29,7 @@ enum vdec_ipi_msgid { VPU_IPIMSG_DEC_RESET_ACK =3D 0xB004, VPU_IPIMSG_DEC_CORE_ACK =3D 0xB005, VPU_IPIMSG_DEC_CORE_END_ACK =3D 0xB006, + VPU_IPIMSG_DEC_GET_PARAM_ACK =3D 0xB007, }; =20 /** @@ -114,4 +116,39 @@ struct vdec_vpu_ipi_init_ack { uint32_t inst_id; }; =20 +/** + * struct vdec_ap_ipi_get_param - for AP_IPIMSG_GET_PARAM + * @msg_id : AP_IPIMSG_DEC_GET_PARAM + * @inst_id : instance ID. Used if the ABI version >=3D 2. + * @data : picture information + * @param_type : get param type + * @codec_type : Codec fourcc + */ +struct vdec_ap_ipi_get_param { + uint32_t msg_id; + uint32_t inst_id; + uint32_t data[4]; + uint32_t param_type; + uint32_t codec_type; +}; + + +/** + * struct vdec_vpu_ipi_get_param_ack - for VPU_IPIMSG_DEC_GET_PARAM_ACK + * @msg_id : VPU_IPIMSG_DEC_GET_PARAM_ACK + * @status : VPU exeuction result + * @ap_inst_addr : AP vcodec_vpu_inst instance address + * @data : picture information from SCP. + * @param_type : get param type + * @reserved : reserved param + */ +struct vdec_vpu_ipi_get_param_ack { + uint32_t msg_id; + int32_t status; + uint64_t ap_inst_addr; + uint32_t data[4]; + uint32_t param_type; + uint32_t reserved; +}; + #endif diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/medi= a/platform/mtk-vcodec/vdec_vpu_if.c index 21f6d9c5a371..2fb9a4184b27 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c @@ -6,6 +6,7 @@ =20 #include "mtk_vcodec_drv.h" #include "mtk_vcodec_util.h" +#include "vdec_drv_if.h" #include "vdec_ipi_msg.h" #include "vdec_vpu_if.h" #include "mtk_vcodec_fw.h" @@ -54,6 +55,27 @@ static void handle_init_ack_msg(const struct vdec_vpu_ip= i_init_ack *msg) } } =20 +static void handle_get_param_msg_ack( + const struct vdec_vpu_ipi_get_param_ack *msg) +{ + struct vdec_vpu_inst *vpu =3D (struct vdec_vpu_inst *) + (unsigned long)msg->ap_inst_addr; + + mtk_vcodec_debug(vpu, "+ ap_inst_addr =3D 0x%llx", msg->ap_inst_addr); + + /* param_type is enum vdec_get_param_type */ + switch(msg->param_type) { + case GET_PARAM_PIC_INFO: + vpu->fb_sz[0] =3D msg->data[0]; + vpu->fb_sz[1] =3D msg->data[1]; + break; + default: + mtk_vcodec_err(vpu, "invalid get param type=3D%d", msg->param_type); + vpu->failure =3D 1; + break; + } +} + /* * vpu_dec_ipi_handler - Handler for VPU ipi message. * @@ -89,6 +111,9 @@ static void vpu_dec_ipi_handler(void *data, unsigned int= len, void *priv) case VPU_IPIMSG_DEC_CORE_END_ACK: break; =20 + case VPU_IPIMSG_DEC_GET_PARAM_ACK: + handle_get_param_msg_ack(data); + break; default: mtk_vcodec_err(vpu, "invalid msg=3D%X", msg->msg_id); break; @@ -217,6 +242,32 @@ int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t = *data, unsigned int len) return err; } =20 +int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data, + unsigned int len, unsigned int param_type) +{ + struct vdec_ap_ipi_get_param msg; + int i; + int err; + + mtk_vcodec_debug_enter(vpu); + + if (len > ARRAY_SIZE(msg.data)) { + mtk_vcodec_err(vpu, "invalid len =3D %d\n", len); + return -EINVAL; + } + + memset(&msg, 0, sizeof(msg)); + msg.msg_id =3D AP_IPIMSG_DEC_GET_PARAM; + msg.inst_id =3D vpu->inst_id; + memcpy(msg.data, data, sizeof(unsigned int) * i); + msg.param_type =3D param_type; + msg.codec_type =3D vpu->codec_type; + + err =3D vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg)); + mtk_vcodec_debug(vpu, "- ret=3D%d", err); + return err; +} + int vpu_dec_core(struct vdec_vpu_inst *vpu) { return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_CORE); diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h b/drivers/medi= a/platform/mtk-vcodec/vdec_vpu_if.h index 4cb3c7f5a3ad..963f8d4877b7 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h @@ -28,6 +28,8 @@ struct mtk_vcodec_ctx; * @wq : wait queue to wait VPU message ack * @handler : ipi handler for each decoder * @codec_type : use codec type to separate different codecs + * @capture_type : used capture type to separate different capture form= at + * @fb_sz : frame buffer size of each plane */ struct vdec_vpu_inst { int id; @@ -42,6 +44,8 @@ struct vdec_vpu_inst { wait_queue_head_t wq; mtk_vcodec_ipi_handler handler; unsigned int codec_type; + unsigned int capture_type; + unsigned int fb_sz[2]; }; =20 /** @@ -104,4 +108,15 @@ int vpu_dec_core(struct vdec_vpu_inst *vpu); */ int vpu_dec_core_end(struct vdec_vpu_inst *vpu); =20 +/** + * vpu_dec_get_param - get param from scp + * + * @vpu : instance for vdec_vpu_inst + * @data: meta data to pass bitstream info to VPU decoder + * @len : meta data length + * @param_type : get param type + */ +int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data, + unsigned int len, unsigned int param_type); + #endif --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF5A8C433F5 for ; Tue, 4 Jan 2022 08:01:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233823AbiADIBw (ORCPT ); Tue, 4 Jan 2022 03:01:52 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:33510 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233792AbiADIBu (ORCPT ); Tue, 4 Jan 2022 03:01:50 -0500 X-UUID: 8c17f17c1f054f499d13de9904318068-20220104 X-UUID: 8c17f17c1f054f499d13de9904318068-20220104 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1101405294; Tue, 04 Jan 2022 16:01:46 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:46 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:44 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , Steve Cho , , , , , , , Subject: [PATCH v3, 04/13] media: mtk-vcodec: Read max resolution from dec_capability Date: Tue, 4 Jan 2022 16:01:29 +0800 Message-ID: <20220104080138.7472-5-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Supported max resolution for different platforms are not the same: 2K or 4K, getting it according to dec_capability. Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih --- .../platform/mtk-vcodec/mtk_vcodec_dec.c | 31 +++++++++++-------- .../platform/mtk-vcodec/mtk_vcodec_drv.h | 4 +++ 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_dec.c index 130ecef2e766..65a224d788bf 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -152,13 +152,15 @@ void mtk_vcodec_dec_set_default_params(struct mtk_vco= dec_ctx *ctx) q_data->coded_height =3D DFT_CFG_HEIGHT; q_data->fmt =3D ctx->dev->vdec_pdata->default_cap_fmt; q_data->field =3D V4L2_FIELD_NONE; + ctx->max_width =3D MTK_VDEC_MAX_W; + ctx->max_height =3D MTK_VDEC_MAX_H; =20 v4l_bound_align_image(&q_data->coded_width, MTK_VDEC_MIN_W, - MTK_VDEC_MAX_W, 4, + ctx->max_width, 4, &q_data->coded_height, MTK_VDEC_MIN_H, - MTK_VDEC_MAX_H, 5, 6); + ctx->max_height, 5, 6); =20 q_data->sizeimage[0] =3D q_data->coded_width * q_data->coded_height; q_data->bytesperline[0] =3D q_data->coded_width; @@ -217,17 +219,17 @@ static int vidioc_vdec_subscribe_evt(struct v4l2_fh *= fh, } } =20 -static int vidioc_try_fmt(struct v4l2_format *f, - const struct mtk_video_fmt *fmt) +static int vidioc_try_fmt(struct mtk_vcodec_ctx *ctx, + struct v4l2_format *f, const struct mtk_video_fmt *fmt) { struct v4l2_pix_format_mplane *pix_fmt_mp =3D &f->fmt.pix_mp; =20 pix_fmt_mp->field =3D V4L2_FIELD_NONE; =20 pix_fmt_mp->width =3D - clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, MTK_VDEC_MAX_W); + clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, ctx->max_width); pix_fmt_mp->height =3D - clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, MTK_VDEC_MAX_H); + clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, ctx->max_height); =20 if (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { pix_fmt_mp->num_planes =3D 1; @@ -245,16 +247,16 @@ static int vidioc_try_fmt(struct v4l2_format *f, tmp_h =3D pix_fmt_mp->height; v4l_bound_align_image(&pix_fmt_mp->width, MTK_VDEC_MIN_W, - MTK_VDEC_MAX_W, 6, + ctx->max_width, 6, &pix_fmt_mp->height, MTK_VDEC_MIN_H, - MTK_VDEC_MAX_H, 6, 9); + ctx->max_height, 6, 9); =20 if (pix_fmt_mp->width < tmp_w && - (pix_fmt_mp->width + 64) <=3D MTK_VDEC_MAX_W) + (pix_fmt_mp->width + 64) <=3D ctx->max_width) pix_fmt_mp->width +=3D 64; if (pix_fmt_mp->height < tmp_h && - (pix_fmt_mp->height + 64) <=3D MTK_VDEC_MAX_H) + (pix_fmt_mp->height + 64) <=3D ctx->max_height) pix_fmt_mp->height +=3D 64; =20 mtk_v4l2_debug(0, @@ -294,7 +296,7 @@ static int vidioc_try_fmt_vid_cap_mplane(struct file *f= ile, void *priv, fmt =3D mtk_vdec_find_format(f, dec_pdata); } =20 - return vidioc_try_fmt(f, fmt); + return vidioc_try_fmt(ctx, f, fmt); } =20 static int vidioc_try_fmt_vid_out_mplane(struct file *file, void *priv, @@ -317,7 +319,7 @@ static int vidioc_try_fmt_vid_out_mplane(struct file *f= ile, void *priv, return -EINVAL; } =20 - return vidioc_try_fmt(f, fmt); + return vidioc_try_fmt(ctx, f, fmt); } =20 static int vidioc_vdec_g_selection(struct file *file, void *priv, @@ -445,7 +447,7 @@ static int vidioc_vdec_s_fmt(struct file *file, void *p= riv, return -EINVAL; =20 q_data->fmt =3D fmt; - vidioc_try_fmt(f, q_data->fmt); + vidioc_try_fmt(ctx, f, q_data->fmt); if (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { q_data->sizeimage[0] =3D pix_mp->plane_fmt[0].sizeimage; q_data->coded_width =3D pix_mp->width; @@ -545,6 +547,9 @@ static int vidioc_enum_framesizes(struct file *file, vo= id *priv, fsize->stepwise.min_height, fsize->stepwise.max_height, fsize->stepwise.step_height); + + ctx->max_width =3D fsize->stepwise.max_width; + ctx->max_height =3D fsize->stepwise.max_height; return 0; } =20 diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_drv.h index a23a7646437c..2d7ec1e16423 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -287,6 +287,8 @@ struct vdec_pic_info { * mtk_video_dec_buf. * @hw_id: hardware index used to identify different hardware. * + * @max_width: hardware supported max width + * @max_height: hardware supported max height * @msg_queue: msg queue used to store lat buffer information. */ struct mtk_vcodec_ctx { @@ -332,6 +334,8 @@ struct mtk_vcodec_ctx { struct mutex lock; int hw_id; =20 + unsigned int max_width; + unsigned int max_height; struct vdec_msg_queue msg_queue; }; =20 --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C88AC433FE for ; Tue, 4 Jan 2022 08:02:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233862AbiADIB7 (ORCPT ); Tue, 4 Jan 2022 03:01:59 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:33662 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233807AbiADIBw (ORCPT ); Tue, 4 Jan 2022 03:01:52 -0500 X-UUID: c42673fed8134013959fc379e03e12d7-20220104 X-UUID: c42673fed8134013959fc379e03e12d7-20220104 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 197124608; Tue, 04 Jan 2022 16:01:49 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 4 Jan 2022 16:01:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:47 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:46 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 05/13] media: mtk-vcodec: Call v4l2_m2m_set_dst_buffered() set capture buffer buffered Date: Tue, 4 Jan 2022 16:01:30 +0800 Message-ID: <20220104080138.7472-6-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" lat thread: output queue \ -> lat hardware -> lat trans buffer lat trans buffer / core thread: capture queue \ ->core hardware -> capture queue lat trans buffer / Lat and core work in different thread, setting capture buffer buffered. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c b= /drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c index 5aebf88f997b..23a154c4e321 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c @@ -314,6 +314,9 @@ static void mtk_init_vdec_params(struct mtk_vcodec_ctx = *ctx) src_vq =3D v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); =20 + if (ctx->dev->vdec_pdata->hw_arch !=3D MTK_VDEC_PURE_SINGLE_CORE) + v4l2_m2m_set_dst_buffered(ctx->m2m_ctx, 1); + /* Support request api for output plane */ src_vq->supports_requests =3D true; src_vq->requires_requests =3D true; --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8466BC433F5 for ; Tue, 4 Jan 2022 08:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234001AbiADICR (ORCPT ); Tue, 4 Jan 2022 03:02:17 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52938 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233822AbiADIBy (ORCPT ); Tue, 4 Jan 2022 03:01:54 -0500 X-UUID: fe4e382ba4154ce989aea92e54c29c28-20220104 X-UUID: fe4e382ba4154ce989aea92e54c29c28-20220104 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 513615615; Tue, 04 Jan 2022 16:01:51 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:49 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:47 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , Steve Cho , , , , , , , Subject: [PATCH v3, 06/13] media: mtk-vcodec: Refactor get and put capture buffer flow Date: Tue, 4 Jan 2022 16:01:31 +0800 Message-ID: <20220104080138.7472-7-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For lat and core decode in parallel, need to get capture buffer when core start to decode and put put capture buffer to display list when core decode done. Signed-off-by: Yunfei Dong --- .../mtk-vcodec/mtk_vcodec_dec_stateless.c | 123 ++++++++++++------ .../platform/mtk-vcodec/mtk_vcodec_drv.h | 5 +- .../mtk-vcodec/vdec/vdec_h264_req_if.c | 16 ++- 3 files changed, 104 insertions(+), 40 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c b= /drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c index 23a154c4e321..f3036c3f223b 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c @@ -108,37 +108,89 @@ static const struct mtk_codec_framesizes mtk_vdec_fra= mesizes[] =3D { =20 #define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) =20 -static void mtk_vdec_stateless_set_dst_payload(struct mtk_vcodec_ctx *ctx, - struct vdec_fb *fb) +static void mtk_vdec_stateless_out_to_done(struct mtk_vcodec_ctx *ctx, + struct mtk_vcodec_mem *bs, int error) { - struct mtk_video_dec_buf *vdec_frame_buf =3D - container_of(fb, struct mtk_video_dec_buf, frame_buffer); - struct vb2_v4l2_buffer *vb =3D &vdec_frame_buf->m2m_buf.vb; - unsigned int cap_y_size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; + struct mtk_video_dec_buf *out_buf; + struct vb2_v4l2_buffer *vb; =20 - vb2_set_plane_payload(&vb->vb2_buf, 0, cap_y_size); - if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) { - unsigned int cap_c_size =3D - ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; + if (!bs) { + mtk_v4l2_err("Free bitstream buffer fail."); + return; + } + out_buf =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + vb =3D &out_buf->m2m_buf.vb; + + mtk_v4l2_debug(2, + "Free bitsteam buffer id =3D %d to done_list", + vb->vb2_buf.index); + + v4l2_m2m_src_buf_remove(ctx->m2m_ctx); + if (error) { + v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR); + if (error =3D=3D -EIO) + out_buf->error =3D true; + } else { + v4l2_m2m_buf_done(vb, VB2_BUF_STATE_DONE); + } +} =20 - vb2_set_plane_payload(&vb->vb2_buf, 1, cap_c_size); +static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_ctx *ctx, + struct vdec_fb *fb, int error) +{ + struct mtk_video_dec_buf *vdec_frame_buf; + struct vb2_v4l2_buffer *vb; + unsigned int cap_y_size, cap_c_size; + + if (!fb) { + mtk_v4l2_err("Free frame buffer fail."); + return; } + vdec_frame_buf =3D container_of(fb, struct mtk_video_dec_buf, + frame_buffer); + vb =3D &vdec_frame_buf->m2m_buf.vb; + + cap_y_size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; + cap_c_size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; + + v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); + + vb2_set_plane_payload(&vb->vb2_buf, 0, cap_y_size); + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) + vb2_set_plane_payload(&vb->vb2_buf, 1, cap_c_size); + + mtk_v4l2_debug(2, + "Free frame buffer id =3D %d to done_list", + vb->vb2_buf.index); + if (error) + v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR); + else + v4l2_m2m_buf_done(vb, VB2_BUF_STATE_DONE); } =20 -static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx, - struct vb2_v4l2_buffer *vb2_v4l2) +static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx) { - struct mtk_video_dec_buf *framebuf =3D - container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); - struct vdec_fb *pfb =3D &framebuf->frame_buffer; - struct vb2_buffer *dst_buf =3D &vb2_v4l2->vb2_buf; + struct mtk_video_dec_buf *framebuf; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vb2_buffer *dst_buf; + struct vdec_fb *pfb; + + vb2_v4l2 =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + if (!vb2_v4l2) { + mtk_v4l2_debug(1, "[%d] dst_buf empty!!", ctx->id); + return NULL; + } =20 - pfb->base_y.va =3D NULL; + dst_buf =3D &vb2_v4l2->vb2_buf; + framebuf =3D container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); + + pfb =3D &framebuf->frame_buffer; + pfb->base_y.va =3D vb2_plane_vaddr(dst_buf, 0); pfb->base_y.dma_addr =3D vb2_dma_contig_plane_dma_addr(dst_buf, 0); pfb->base_y.size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; =20 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) { - pfb->base_c.va =3D NULL; + pfb->base_c.va =3D vb2_plane_vaddr(dst_buf, 1); pfb->base_c.dma_addr =3D vb2_dma_contig_plane_dma_addr(dst_buf, 1); pfb->base_c.size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; @@ -162,12 +214,11 @@ static void mtk_vdec_worker(struct work_struct *work) struct mtk_vcodec_ctx *ctx =3D container_of(work, struct mtk_vcodec_ctx, decode_work); struct mtk_vcodec_dev *dev =3D ctx->dev; - struct vb2_v4l2_buffer *vb2_v4l2_src, *vb2_v4l2_dst; + struct vb2_v4l2_buffer *vb2_v4l2_src; struct vb2_buffer *vb2_src; struct mtk_vcodec_mem *bs_src; struct mtk_video_dec_buf *dec_buf_src; struct media_request *src_buf_req; - struct vdec_fb *dst_buf; bool res_chg =3D false; int ret; =20 @@ -178,13 +229,6 @@ static void mtk_vdec_worker(struct work_struct *work) return; } =20 - vb2_v4l2_dst =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); - if (!vb2_v4l2_dst) { - v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); - mtk_v4l2_debug(1, "[%d] no available destination buffer", ctx->id); - return; - } - vb2_src =3D &vb2_v4l2_src->vb2_buf; dec_buf_src =3D container_of(vb2_v4l2_src, struct mtk_video_dec_buf, m2m_buf.vb); @@ -193,9 +237,15 @@ static void mtk_vdec_worker(struct work_struct *work) mtk_v4l2_debug(3, "[%d] (%d) id=3D%d, vb=3D%p", ctx->id, vb2_src->vb2_queue->type, vb2_src->index, vb2_src); =20 - bs_src->va =3D NULL; + bs_src->va =3D vb2_plane_vaddr(vb2_src, 0); bs_src->dma_addr =3D vb2_dma_contig_plane_dma_addr(vb2_src, 0); bs_src->size =3D (size_t)vb2_src->planes[0].bytesused; + if (!bs_src->va) { + v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); + mtk_v4l2_err("[%d] id=3D%d source buffer is NULL", ctx->id, + vb2_src->index); + return; + } =20 mtk_v4l2_debug(3, "[%d] Bitstream VA=3D%p DMA=3D%pad Size=3D%zx vb=3D%p", ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src); @@ -206,9 +256,7 @@ static void mtk_vdec_worker(struct work_struct *work) else mtk_v4l2_err("vb2 buffer media request is NULL"); =20 - dst_buf =3D vdec_get_cap_buffer(ctx, vb2_v4l2_dst); - v4l2_m2m_buf_copy_metadata(vb2_v4l2_src, vb2_v4l2_dst, true); - ret =3D vdec_if_decode(ctx, bs_src, dst_buf, &res_chg); + ret =3D vdec_if_decode(ctx, bs_src, NULL, &res_chg); if (ret) { mtk_v4l2_err(" <=3D=3D=3D[%d], src_buf[%d] sz=3D0x%zx pts=3D%llu vdec_if= _decode() ret=3D%d res_chg=3D%d=3D=3D=3D>", ctx->id, vb2_src->index, bs_src->size, @@ -220,12 +268,9 @@ static void mtk_vdec_worker(struct work_struct *work) } } =20 - mtk_vdec_stateless_set_dst_payload(ctx, dst_buf); - - v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, - ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); - + mtk_vdec_stateless_out_to_done(ctx, bs_src, ret); v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); + v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); } =20 static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb) @@ -358,6 +403,8 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, }; @@ -376,6 +423,8 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdat= a =3D { .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, }; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_drv.h index 2d7ec1e16423..5347d77300fa 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -360,7 +360,8 @@ enum mtk_vdec_hw_arch { * @ctrls_setup: init vcodec dec ctrls * @worker: worker to start a decode job * @flush_decoder: function that flushes the decoder - * + * @get_cap_buffer: get capture buffer from capture queue + * @cap_to_disp: put capture buffer to disp list * @vdec_vb2_ops: struct vb2_ops * * @vdec_formats: supported video decoder formats @@ -382,6 +383,8 @@ struct mtk_vcodec_dec_pdata { int (*ctrls_setup)(struct mtk_vcodec_ctx *ctx); void (*worker)(struct work_struct *work); int (*flush_decoder)(struct mtk_vcodec_ctx *ctx); + struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_ctx *ctx); + void (*cap_to_disp)(struct mtk_vcodec_ctx *ctx, struct vdec_fb *fb, int e= rror); =20 struct vb2_ops *vdec_vb2_ops; =20 diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c b/dr= ivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c index 43542de11e9c..d00219a7587c 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c @@ -670,32 +670,42 @@ static void vdec_h264_slice_deinit(void *h_vdec) } =20 static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, - struct vdec_fb *fb, bool *res_chg) + struct vdec_fb *unused, bool *res_chg) { struct vdec_h264_slice_inst *inst =3D h_vdec; const struct v4l2_ctrl_h264_decode_params *dec_params =3D get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info; + struct mtk_video_dec_buf *dst_buf_info; + struct vdec_fb *fb; u32 data[2]; u64 y_fb_dma; u64 c_fb_dma; int err; =20 + inst->num_nalu++; /* bs NULL means flush decoder */ if (!bs) return vpu_dec_reset(vpu); =20 + fb =3D inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + dst_buf_info =3D container_of(fb, struct mtk_video_dec_buf, frame_buffer); + y_fb_dma =3D fb ? (u64)fb->base_y.dma_addr : 0; c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; =20 mtk_vcodec_debug(inst, "+ [%d] FB y_dma=3D%llx c_dma=3D%llx va=3D%p", - ++inst->num_nalu, y_fb_dma, c_fb_dma, fb); + inst->num_nalu, y_fb_dma, c_fb_dma, fb); =20 inst->vsi_ctx.dec.bs_dma =3D (uint64_t)bs->dma_addr; inst->vsi_ctx.dec.y_fb_dma =3D y_fb_dma; inst->vsi_ctx.dec.c_fb_dma =3D c_fb_dma; inst->vsi_ctx.dec.vdec_fb_va =3D (u64)(uintptr_t)fb; =20 + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, + &dst_buf_info->m2m_buf.vb, true); get_vdec_decode_parameters(inst); data[0] =3D bs->size; /* @@ -734,6 +744,8 @@ static int vdec_h264_slice_decode(void *h_vdec, struct = mtk_vcodec_mem *bs, =20 memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx)); mtk_vcodec_debug(inst, "\n - NALU[%d]", inst->num_nalu); + + inst->ctx->dev->vdec_pdata->cap_to_disp(inst->ctx, fb, 0); return 0; =20 err_free_fb_out: --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9495BC433EF for ; Tue, 4 Jan 2022 08:02:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233814AbiADICH (ORCPT ); Tue, 4 Jan 2022 03:02:07 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:53048 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233845AbiADIB4 (ORCPT ); Tue, 4 Jan 2022 03:01:56 -0500 X-UUID: 577920fab278475fa90654ddb133fd4a-20220104 X-UUID: 577920fab278475fa90654ddb133fd4a-20220104 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1246187477; Tue, 04 Jan 2022 16:01:52 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 4 Jan 2022 16:01:51 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:49 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 07/13] media: mtk-vcodec: Refactor supported vdec formats and framesizes Date: Tue, 4 Jan 2022 16:01:32 +0800 Message-ID: <20220104080138.7472-8-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Supported output and capture format types for mt8192 are different with mt8183. Needs to get format types according to decoder capability. Signed-off-by: Yunfei Dong --- .../platform/mtk-vcodec/mtk_vcodec_dec.c | 8 +- .../mtk-vcodec/mtk_vcodec_dec_stateful.c | 13 +- .../mtk-vcodec/mtk_vcodec_dec_stateless.c | 117 +++++++++++++----- .../platform/mtk-vcodec/mtk_vcodec_drv.h | 13 +- 4 files changed, 107 insertions(+), 44 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_dec.c index 65a224d788bf..519f2b9d9b5b 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -26,7 +26,7 @@ mtk_vdec_find_format(struct v4l2_format *f, const struct mtk_video_fmt *fmt; unsigned int k; =20 - for (k =3D 0; k < dec_pdata->num_formats; k++) { + for (k =3D 0; k < *dec_pdata->num_formats; k++) { fmt =3D &dec_pdata->vdec_formats[k]; if (fmt->fourcc =3D=3D f->fmt.pix_mp.pixelformat) return fmt; @@ -525,7 +525,7 @@ static int vidioc_enum_framesizes(struct file *file, vo= id *priv, if (fsize->index !=3D 0) return -EINVAL; =20 - for (i =3D 0; i < dec_pdata->num_framesizes; ++i) { + for (i =3D 0; i < *dec_pdata->num_framesizes; ++i) { if (fsize->pixel_format !=3D dec_pdata->vdec_framesizes[i].fourcc) continue; =20 @@ -564,7 +564,7 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, void= *priv, const struct mtk_video_fmt *fmt; int i, j =3D 0; =20 - for (i =3D 0; i < dec_pdata->num_formats; i++) { + for (i =3D 0; i < *dec_pdata->num_formats; i++) { if (output_queue && dec_pdata->vdec_formats[i].type !=3D MTK_FMT_DEC) continue; @@ -577,7 +577,7 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, void= *priv, ++j; } =20 - if (i =3D=3D dec_pdata->num_formats) + if (i =3D=3D *dec_pdata->num_formats) return -EINVAL; =20 fmt =3D &dec_pdata->vdec_formats[i]; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c b/= drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c index 7966c132be8f..3f33beb9c551 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateful.c @@ -37,7 +37,9 @@ static const struct mtk_video_fmt mtk_video_formats[] =3D= { }, }; =20 -#define NUM_FORMATS ARRAY_SIZE(mtk_video_formats) +static const unsigned int num_supported_formats =3D + ARRAY_SIZE(mtk_video_formats); + #define DEFAULT_OUT_FMT_IDX 0 #define DEFAULT_CAP_FMT_IDX 3 =20 @@ -59,7 +61,8 @@ static const struct mtk_codec_framesizes mtk_vdec_framesi= zes[] =3D { }, }; =20 -#define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) +static const unsigned int num_supported_framesize =3D + ARRAY_SIZE(mtk_vdec_framesizes); =20 /* * This function tries to clean all display buffers, the buffers will retu= rn @@ -235,7 +238,7 @@ static void mtk_vdec_update_fmt(struct mtk_vcodec_ctx *= ctx, unsigned int k; =20 dst_q_data =3D &ctx->q_data[MTK_Q_DATA_DST]; - for (k =3D 0; k < NUM_FORMATS; k++) { + for (k =3D 0; k < num_supported_formats; k++) { fmt =3D &mtk_video_formats[k]; if (fmt->fourcc =3D=3D pixelformat) { mtk_v4l2_debug(1, "Update cap fourcc(%d -> %d)", @@ -617,11 +620,11 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata= =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_frame_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D NUM_FORMATS, + .num_formats =3D &num_supported_formats, .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D NUM_SUPPORTED_FRAMESIZE, + .num_framesizes =3D &num_supported_framesize, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, .is_subdev_supported =3D false, diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c b= /drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c index f3036c3f223b..01bb96f3b30e 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c @@ -81,33 +81,23 @@ static const struct mtk_stateless_control mtk_stateless= _controls[] =3D { =20 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) =20 -static const struct mtk_video_fmt mtk_video_formats[] =3D { - { - .fourcc =3D V4L2_PIX_FMT_H264_SLICE, - .type =3D MTK_FMT_DEC, - .num_planes =3D 1, - }, - { - .fourcc =3D V4L2_PIX_FMT_MM21, - .type =3D MTK_FMT_FRAME, - .num_planes =3D 2, - }, +static struct mtk_video_fmt mtk_video_formats[2]; +static struct mtk_codec_framesizes mtk_vdec_framesizes[1]; + +static struct mtk_video_fmt default_out_format; +static struct mtk_video_fmt default_cap_format; +static unsigned int num_formats =3D 0; +static unsigned int num_framesizes =3D 0; + +static struct v4l2_frmsize_stepwise stepwise_fhd =3D { + .min_width =3D MTK_VDEC_MIN_W, + .max_width =3D MTK_VDEC_MAX_W, + .step_width =3D 16, + .min_height =3D MTK_VDEC_MIN_H, + .max_height =3D MTK_VDEC_MAX_H, + .step_height =3D 16 }; =20 -#define NUM_FORMATS ARRAY_SIZE(mtk_video_formats) -#define DEFAULT_OUT_FMT_IDX 0 -#define DEFAULT_CAP_FMT_IDX 1 - -static const struct mtk_codec_framesizes mtk_vdec_framesizes[] =3D { - { - .fourcc =3D V4L2_PIX_FMT_H264_SLICE, - .stepwise =3D { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16, - MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 }, - }, -}; - -#define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) - static void mtk_vdec_stateless_out_to_done(struct mtk_vcodec_ctx *ctx, struct mtk_vcodec_mem *bs, int error) { @@ -352,6 +342,63 @@ const struct media_device_ops mtk_vcodec_media_ops =3D= { .req_queue =3D v4l2_m2m_request_queue, }; =20 +static void mtk_vcodec_add_formats(unsigned int fourcc, + struct mtk_vcodec_ctx *ctx) +{ + struct mtk_vcodec_dev *dev =3D ctx->dev; + const struct mtk_vcodec_dec_pdata *pdata =3D dev->vdec_pdata; + int count_formats =3D *pdata->num_formats; + int count_framesizes =3D *pdata->num_framesizes; + + switch (fourcc) { + case V4L2_PIX_FMT_H264_SLICE: + mtk_video_formats[count_formats].fourcc =3D fourcc; + mtk_video_formats[count_formats].type =3D MTK_FMT_DEC; + mtk_video_formats[count_formats].num_planes =3D 1; + + mtk_vdec_framesizes[count_framesizes].fourcc =3D fourcc; + mtk_vdec_framesizes[count_framesizes].stepwise =3D stepwise_fhd; + num_framesizes++; + break; + case V4L2_PIX_FMT_MM21: + mtk_video_formats[count_formats].fourcc =3D fourcc; + mtk_video_formats[count_formats].type =3D MTK_FMT_FRAME; + mtk_video_formats[count_formats].num_planes =3D 2; + break; + default: + mtk_v4l2_err("Can not add unsupported format type"); + return; + } + + num_formats++; + mtk_v4l2_debug(3, "num_formats: %d num_frames:%d dec_capability: 0x%x", + *(pdata->num_formats), *(pdata->num_framesizes), + ctx->dev->dec_capability); +} + +static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_ctx *ctx) +{ + int cap_format_count =3D 0, out_format_count =3D 0; + + if (num_formats && num_framesizes) + return; + + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); + cap_format_count++; + } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); + out_format_count++; + } + + if (cap_format_count) + default_cap_format =3D mtk_video_formats[cap_format_count - 1]; + if (out_format_count) + default_out_format =3D + mtk_video_formats[cap_format_count + out_format_count - 1]; +} + static void mtk_init_vdec_params(struct mtk_vcodec_ctx *ctx) { struct vb2_queue *src_vq; @@ -361,6 +408,10 @@ static void mtk_init_vdec_params(struct mtk_vcodec_ctx= *ctx) =20 if (ctx->dev->vdec_pdata->hw_arch !=3D MTK_VDEC_PURE_SINGLE_CORE) v4l2_m2m_set_dst_buffered(ctx->m2m_ctx, 1); + else + ctx->dev->dec_capability |=3D + MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21; + mtk_vcodec_get_supported_formats(ctx); =20 /* Support request api for output plane */ src_vq->supports_requests =3D true; @@ -395,11 +446,11 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata= =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D NUM_FORMATS, - .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], - .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D NUM_SUPPORTED_FRAMESIZE, + .num_framesizes =3D &num_framesizes, .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, @@ -415,11 +466,11 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pd= ata =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D NUM_FORMATS, - .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], - .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D NUM_SUPPORTED_FRAMESIZE, + .num_framesizes =3D &num_framesizes, .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_drv.h index 5347d77300fa..4ae80d2e77d2 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -354,6 +354,15 @@ enum mtk_vdec_hw_arch { MTK_VDEC_LAT_SINGLE_CORE, }; =20 +/** + * struct mtk_vdec_format_types - Structure used to get supported + * format types according to decoder capability + */ +enum mtk_vdec_format_types { + MTK_VDEC_FORMAT_MM21 =3D 0x20, + MTK_VDEC_FORMAT_H264_SLICE =3D 0x100, +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -389,12 +398,12 @@ struct mtk_vcodec_dec_pdata { struct vb2_ops *vdec_vb2_ops; =20 const struct mtk_video_fmt *vdec_formats; - const int num_formats; + const int *num_formats; const struct mtk_video_fmt *default_out_fmt; const struct mtk_video_fmt *default_cap_fmt; =20 const struct mtk_codec_framesizes *vdec_framesizes; - const int num_framesizes; + const int *num_framesizes; =20 enum mtk_vdec_hw_arch hw_arch; =20 --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9502C433FE for ; Tue, 4 Jan 2022 08:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233962AbiADICM (ORCPT ); Tue, 4 Jan 2022 03:02:12 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:53124 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233856AbiADIB5 (ORCPT ); Tue, 4 Jan 2022 03:01:57 -0500 X-UUID: c73f664dd74249f282d030534e65821b-20220104 X-UUID: c73f664dd74249f282d030534e65821b-20220104 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 150738554; Tue, 04 Jan 2022 16:01:54 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 4 Jan 2022 16:01:53 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:52 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:51 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 08/13] media: mtk-vcodec: Add format to support MT21C Date: Tue, 4 Jan 2022 16:01:33 +0800 Message-ID: <20220104080138.7472-9-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Needs to use mediatek compressed mode for mt8192 decoder. Signed-off-by: Yunfei Dong --- .../media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c | 7 ++++++- drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c b= /drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c index 01bb96f3b30e..21895fbed4c5 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_stateless.c @@ -81,7 +81,7 @@ static const struct mtk_stateless_control mtk_stateless_c= ontrols[] =3D { =20 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) =20 -static struct mtk_video_fmt mtk_video_formats[2]; +static struct mtk_video_fmt mtk_video_formats[3]; static struct mtk_codec_framesizes mtk_vdec_framesizes[1]; =20 static struct mtk_video_fmt default_out_format; @@ -361,6 +361,7 @@ static void mtk_vcodec_add_formats(unsigned int fourcc, num_framesizes++; break; case V4L2_PIX_FMT_MM21: + case V4L2_PIX_FMT_MT21C: mtk_video_formats[count_formats].fourcc =3D fourcc; mtk_video_formats[count_formats].type =3D MTK_FMT_FRAME; mtk_video_formats[count_formats].num_planes =3D 2; @@ -387,6 +388,10 @@ static void mtk_vcodec_get_supported_formats(struct mt= k_vcodec_ctx *ctx) mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); cap_format_count++; } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx); + cap_format_count++; + } if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) { mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); out_format_count++; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_drv.h index 4ae80d2e77d2..6c084a172e4b 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -360,6 +360,7 @@ enum mtk_vdec_hw_arch { */ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_MM21 =3D 0x20, + MTK_VDEC_FORMAT_MT21C =3D 0x40, MTK_VDEC_FORMAT_H264_SLICE =3D 0x100, }; =20 --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD38CC433F5 for ; Tue, 4 Jan 2022 08:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233937AbiADICK (ORCPT ); Tue, 4 Jan 2022 03:02:10 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:33934 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233801AbiADIB6 (ORCPT ); Tue, 4 Jan 2022 03:01:58 -0500 X-UUID: 39170258b0f0489597b3211ec16722c0-20220104 X-UUID: 39170258b0f0489597b3211ec16722c0-20220104 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2092364369; Tue, 04 Jan 2022 16:01:56 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:54 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:52 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , Steve Cho , , , , , , , Subject: [PATCH v3, 09/13] media: mtk-vcodec: disable vp8 4K capability Date: Tue, 4 Jan 2022 16:01:34 +0800 Message-ID: <20220104080138.7472-10-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For vp8 not support 4K, need to disable it. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_dec.c index 519f2b9d9b5b..34ee4a0092ff 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -532,7 +532,8 @@ static int vidioc_enum_framesizes(struct file *file, vo= id *priv, fsize->type =3D V4L2_FRMSIZE_TYPE_STEPWISE; fsize->stepwise =3D dec_pdata->vdec_framesizes[i].stepwise; if (!(ctx->dev->dec_capability & - VCODEC_CAPABILITY_4K_DISABLED)) { + VCODEC_CAPABILITY_4K_DISABLED) && + fsize->pixel_format !=3D V4L2_PIX_FMT_VP8_FRAME) { mtk_v4l2_debug(3, "4K is enabled"); fsize->stepwise.max_width =3D VCODEC_DEC_4K_CODED_WIDTH; --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEE66C433FE for ; Tue, 4 Jan 2022 08:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233972AbiADICd (ORCPT ); Tue, 4 Jan 2022 03:02:33 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:34066 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233871AbiADICB (ORCPT ); Tue, 4 Jan 2022 03:02:01 -0500 X-UUID: 11d2cfbb5824468eaf7426bfe7ab199f-20220104 X-UUID: 11d2cfbb5824468eaf7426bfe7ab199f-20220104 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 473442449; Tue, 04 Jan 2022 16:01:57 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 4 Jan 2022 16:01:55 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:54 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 10/13] media: mtk-vcodec: Fix v4l2-compliance fail Date: Tue, 4 Jan 2022 16:01:35 +0800 Message-ID: <20220104080138.7472-11-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Need to use default pic info when get pic info fail. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_dec.c index 34ee4a0092ff..75210eb829d0 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -478,11 +478,14 @@ static int vidioc_vdec_s_fmt(struct file *file, void = *priv, ctx->picinfo.pic_w =3D pix_mp->width; ctx->picinfo.pic_h =3D pix_mp->height; =20 + /* + * If get pic info fail, need to use the default pic info params, or + * v4l2-compliance will fail + */ ret =3D vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo); if (ret) { mtk_v4l2_err("[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id); - return -EINVAL; } =20 ctx->last_decoded_picinfo =3D ctx->picinfo; --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E6C1C433FE for ; Tue, 4 Jan 2022 08:02:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231340AbiADICb (ORCPT ); Tue, 4 Jan 2022 03:02:31 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:53312 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233885AbiADICC (ORCPT ); Tue, 4 Jan 2022 03:02:02 -0500 X-UUID: 10960c3cd39c42b8bc85ea32ead3203f-20220104 X-UUID: 10960c3cd39c42b8bc85ea32ead3203f-20220104 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2019372065; Tue, 04 Jan 2022 16:01:59 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 4 Jan 2022 16:01:57 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:55 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v3, 11/13] media: mtk-vcodec: record capture queue format type Date: Tue, 4 Jan 2022 16:01:36 +0800 Message-ID: <20220104080138.7472-12-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Capture queue format type is difference for different platform, need to calculate capture buffer size according to capture queue format type in scp. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 2 ++ drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_dec.c index 75210eb829d0..4533cb44551d 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -468,6 +468,8 @@ static int vidioc_vdec_s_fmt(struct file *file, void *p= riv, } ctx->state =3D MTK_STATE_INIT; } + } else { + ctx->capture_fourcc =3D fmt->fourcc; } =20 /* diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/m= edia/platform/mtk-vcodec/mtk_vcodec_drv.h index 6c084a172e4b..364d2d794af4 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -277,6 +277,7 @@ struct vdec_pic_info { * to be used with encoder and stateful decoder. * @is_flushing: set to true if flushing is in progress. * @current_codec: current set input codec, in V4L2 pixel format + * @capture_fourcc: capture queue type in V4L2 pixel format * * @colorspace: enum v4l2_colorspace; supplemental to pixelformat * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding @@ -324,6 +325,7 @@ struct mtk_vcodec_ctx { bool is_flushing; =20 u32 current_codec; + u32 capture_fourcc; =20 enum v4l2_colorspace colorspace; enum v4l2_ycbcr_encoding ycbcr_enc; --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAA27C433EF for ; Tue, 4 Jan 2022 08:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234052AbiADICY (ORCPT ); Tue, 4 Jan 2022 03:02:24 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:34180 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233843AbiADICF (ORCPT ); Tue, 4 Jan 2022 03:02:05 -0500 X-UUID: 2ca944a9df1140318b4ed7fc1686c783-20220104 X-UUID: 2ca944a9df1140318b4ed7fc1686c783-20220104 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 264750960; Tue, 04 Jan 2022 16:02:00 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:01:58 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:57 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , Steve Cho , , , , , , , Subject: [PATCH v3, 12/13] media: mtk-vcodec: Extract H264 common code Date: Tue, 4 Jan 2022 16:01:37 +0800 Message-ID: <20220104080138.7472-13-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mt8192 can use some of common code with mt8183. Moves them to a new file in order to reuse. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/Makefile | 1 + .../mtk-vcodec/vdec/vdec_h264_req_common.c | 303 ++++++++++++++ .../mtk-vcodec/vdec/vdec_h264_req_common.h | 247 +++++++++++ .../mtk-vcodec/vdec/vdec_h264_req_if.c | 386 +----------------- 4 files changed, 571 insertions(+), 366 deletions(-) create mode 100644 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_co= mmon.c create mode 100644 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_co= mmon.h diff --git a/drivers/media/platform/mtk-vcodec/Makefile b/drivers/media/pla= tform/mtk-vcodec/Makefile index 359619653a0e..3f41d748eee5 100644 --- a/drivers/media/platform/mtk-vcodec/Makefile +++ b/drivers/media/platform/mtk-vcodec/Makefile @@ -9,6 +9,7 @@ mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp8_if.o \ vdec/vdec_vp9_if.o \ vdec/vdec_h264_req_if.o \ + vdec/vdec_h264_req_common.o \ mtk_vcodec_dec_drv.o \ vdec_drv_if.o \ vdec_vpu_if.o \ diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_common.c = b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_common.c new file mode 100644 index 000000000000..7e248e247628 --- /dev/null +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_common.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Yunfei Dong + */ + +#include "vdec_h264_req_common.h" + +/* get used parameters for sps/pps */ +#define GET_MTK_VDEC_FLAG(cond, flag) \ + { dst_param->cond =3D ((src_param->flags & flag) ? (1) : (0)); } +#define GET_MTK_VDEC_PARAM(param) \ + { dst_param->param =3D src_param->param; } + +void *mtk_vdec_h264_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) +{ + struct v4l2_ctrl *ctrl =3D v4l2_ctrl_find(&ctx->ctrl_hdl, id); + + return ctrl->p_cur.p; +} + +void mtk_vdec_h264_fill_dpb_info(struct mtk_vcodec_ctx *ctx, + struct slice_api_h264_decode_param *decode_params, + struct mtk_h264_dpb_info *h264_dpb_info) +{ + struct vb2_queue *vq; + struct vb2_buffer *vb; + struct vb2_v4l2_buffer *vb2_v4l2; + int index; + + vq =3D v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + + for (index =3D 0; index < V4L2_H264_NUM_DPB_ENTRIES; index++) { + const struct slice_h264_dpb_entry *dpb; + int vb2_index; + + dpb =3D &decode_params->dpb[index]; + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) { + h264_dpb_info[index].reference_flag =3D 0; + continue; + } + + vb2_index =3D vb2_find_timestamp(vq, dpb->reference_ts, 0); + if (vb2_index < 0) { + dev_err(&ctx->dev->plat_dev->dev, + "Reference invalid: dpb_index(%d) reference_ts(%lld)", + index, dpb->reference_ts); + continue; + } + + /* 1 for short term reference, 2 for long term reference */ + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) + h264_dpb_info[index].reference_flag =3D 1; + else + h264_dpb_info[index].reference_flag =3D 2; + + vb =3D vq->bufs[vb2_index]; + vb2_v4l2 =3D container_of(vb, struct vb2_v4l2_buffer, vb2_buf); + h264_dpb_info[index].field =3D vb2_v4l2->field; + + h264_dpb_info[index].y_dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 0); + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) + h264_dpb_info[index].c_dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 1); + else + h264_dpb_info[index].c_dma_addr =3D + h264_dpb_info[index].y_dma_addr + + ctx->picinfo.fb_sz[0]; + } +} + +void mtk_vdec_h264_copy_sps_params(struct mtk_h264_sps_param *dst_param, + const struct v4l2_ctrl_h264_sps *src_param) +{ + GET_MTK_VDEC_PARAM(chroma_format_idc); + GET_MTK_VDEC_PARAM(bit_depth_luma_minus8); + GET_MTK_VDEC_PARAM(bit_depth_chroma_minus8); + GET_MTK_VDEC_PARAM(log2_max_frame_num_minus4); + GET_MTK_VDEC_PARAM(pic_order_cnt_type); + GET_MTK_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); + GET_MTK_VDEC_PARAM(max_num_ref_frames); + GET_MTK_VDEC_PARAM(pic_width_in_mbs_minus1); + GET_MTK_VDEC_PARAM(pic_height_in_map_units_minus1); + + GET_MTK_VDEC_FLAG(separate_colour_plane_flag, + V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE); + GET_MTK_VDEC_FLAG(qpprime_y_zero_transform_bypass_flag, + V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); + GET_MTK_VDEC_FLAG(delta_pic_order_always_zero_flag, + V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); + GET_MTK_VDEC_FLAG(frame_mbs_only_flag, + V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); + GET_MTK_VDEC_FLAG(mb_adaptive_frame_field_flag, + V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); + GET_MTK_VDEC_FLAG(direct_8x8_inference_flag, + V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); +} + +void mtk_vdec_h264_copy_pps_params(struct mtk_h264_pps_param *dst_param, + const struct v4l2_ctrl_h264_pps *src_param) +{ + GET_MTK_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); + GET_MTK_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); + GET_MTK_VDEC_PARAM(weighted_bipred_idc); + GET_MTK_VDEC_PARAM(pic_init_qp_minus26); + GET_MTK_VDEC_PARAM(chroma_qp_index_offset); + GET_MTK_VDEC_PARAM(second_chroma_qp_index_offset); + + GET_MTK_VDEC_FLAG(entropy_coding_mode_flag, + V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); + GET_MTK_VDEC_FLAG(pic_order_present_flag, + V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); + GET_MTK_VDEC_FLAG(weighted_pred_flag, + V4L2_H264_PPS_FLAG_WEIGHTED_PRED); + GET_MTK_VDEC_FLAG(deblocking_filter_control_present_flag, + V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); + GET_MTK_VDEC_FLAG(constrained_intra_pred_flag, + V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); + GET_MTK_VDEC_FLAG(redundant_pic_cnt_present_flag, + V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); + GET_MTK_VDEC_FLAG(transform_8x8_mode_flag, + V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); + GET_MTK_VDEC_FLAG(scaling_matrix_present_flag, + V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); +} + +void mtk_vdec_h264_copy_slice_hd_params( + struct mtk_h264_slice_hd_param *dst_param, + const struct v4l2_ctrl_h264_slice_params *src_param, + const struct v4l2_ctrl_h264_decode_params *dec_param) +{ + int temp; + + GET_MTK_VDEC_PARAM(first_mb_in_slice); + GET_MTK_VDEC_PARAM(slice_type); + GET_MTK_VDEC_PARAM(cabac_init_idc); + GET_MTK_VDEC_PARAM(slice_qp_delta); + GET_MTK_VDEC_PARAM(disable_deblocking_filter_idc); + GET_MTK_VDEC_PARAM(slice_alpha_c0_offset_div2); + GET_MTK_VDEC_PARAM(slice_beta_offset_div2); + GET_MTK_VDEC_PARAM(num_ref_idx_l0_active_minus1); + GET_MTK_VDEC_PARAM(num_ref_idx_l1_active_minus1); + + dst_param->frame_num =3D dec_param->frame_num; + dst_param->pic_order_cnt_lsb =3D dec_param->pic_order_cnt_lsb; + + dst_param->delta_pic_order_cnt_bottom =3D + dec_param->delta_pic_order_cnt_bottom; + dst_param->delta_pic_order_cnt0 =3D + dec_param->delta_pic_order_cnt0; + dst_param->delta_pic_order_cnt1 =3D + dec_param->delta_pic_order_cnt1; + + temp =3D dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC; + dst_param->field_pic_flag =3D temp ? 1 : 0; + + temp =3D dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD; + dst_param->bottom_field_flag =3D temp ? 1 : 0; + + GET_MTK_VDEC_FLAG(direct_spatial_mv_pred_flag, + V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED); +} + +void mtk_vdec_h264_copy_scaling_matrix( + struct slice_api_h264_scaling_matrix *dst_matrix, + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix) +{ + memcpy(dst_matrix->scaling_list_4x4, src_matrix->scaling_list_4x4, + sizeof(dst_matrix->scaling_list_4x4)); + + memcpy(dst_matrix->scaling_list_8x8, src_matrix->scaling_list_8x8, + sizeof(dst_matrix->scaling_list_8x8)); +} + +void mtk_vdec_h264_copy_decode_params( + struct slice_api_h264_decode_param *dst_params, + const struct v4l2_ctrl_h264_decode_params *src_params, + const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(dst_params->dpb); i++) { + struct slice_h264_dpb_entry *dst_entry =3D &dst_params->dpb[i]; + const struct v4l2_h264_dpb_entry *src_entry =3D &dpb[i]; + + dst_entry->reference_ts =3D src_entry->reference_ts; + dst_entry->frame_num =3D src_entry->frame_num; + dst_entry->pic_num =3D src_entry->pic_num; + dst_entry->top_field_order_cnt =3D src_entry->top_field_order_cnt; + dst_entry->bottom_field_order_cnt =3D + src_entry->bottom_field_order_cnt; + dst_entry->flags =3D src_entry->flags; + } + + /* num_slices is a leftover from the old H.264 support and is ignored + * by the firmware. + */ + dst_params->num_slices =3D 0; + dst_params->nal_ref_idc =3D src_params->nal_ref_idc; + dst_params->top_field_order_cnt =3D src_params->top_field_order_cnt; + dst_params->bottom_field_order_cnt =3D src_params->bottom_field_order_cnt; + dst_params->flags =3D src_params->flags; +} + +static bool mtk_vdec_h264_dpb_entry_match( + const struct v4l2_h264_dpb_entry *a, + const struct v4l2_h264_dpb_entry *b) +{ + return a->top_field_order_cnt =3D=3D b->top_field_order_cnt && + a->bottom_field_order_cnt =3D=3D b->bottom_field_order_cnt; +} + +/* + * Move DPB entries of dec_param that refer to a frame already existing in= dpb + * into the already existing slot in dpb, and move other entries into new = slots. + * + * This function is an adaptation of the similarly-named function in + * hantro_h264.c. + */ +void mtk_vdec_h264_update_dpb(const struct v4l2_ctrl_h264_decode_params *d= ec_param, + struct v4l2_h264_dpb_entry *dpb) +{ + DECLARE_BITMAP(new, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; + DECLARE_BITMAP(in_use, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; + DECLARE_BITMAP(used, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; + unsigned int i, j; + + /* Disable all entries by default, and mark the ones in use. */ + for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) + set_bit(i, in_use); + dpb[i].flags &=3D ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; + } + + /* Try to match new DPB entries with existing ones by their POCs. */ + for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { + const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; + + if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + continue; + + /* + * To cut off some comparisons, iterate only on target DPB + * entries were already used. + */ + for_each_set_bit(j, in_use, ARRAY_SIZE(dec_param->dpb)) { + struct v4l2_h264_dpb_entry *cdpb; + + cdpb =3D &dpb[j]; + if (!mtk_vdec_h264_dpb_entry_match(cdpb, ndpb)) + continue; + + *cdpb =3D *ndpb; + set_bit(j, used); + /* Don't reiterate on this one. */ + clear_bit(j, in_use); + break; + } + + if (j =3D=3D ARRAY_SIZE(dec_param->dpb)) + set_bit(i, new); + } + + /* For entries that could not be matched, use remaining free slots. */ + for_each_set_bit(i, new, ARRAY_SIZE(dec_param->dpb)) { + const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; + struct v4l2_h264_dpb_entry *cdpb; + + /* + * Both arrays are of the same sizes, so there is no way + * we can end up with no space in target array, unless + * something is buggy. + */ + j =3D find_first_zero_bit(used, ARRAY_SIZE(dec_param->dpb)); + if (WARN_ON(j >=3D ARRAY_SIZE(dec_param->dpb))) + return; + + cdpb =3D &dpb[j]; + *cdpb =3D *ndpb; + set_bit(j, used); + } +} + +unsigned int mtk_vdec_h264_get_mv_buf_size( + unsigned int width, unsigned int height) +{ + int unit_size =3D (width / MB_UNIT_LEN) * (height / MB_UNIT_LEN) + 8; + + return HW_MB_STORE_SZ * unit_size; +} + +int mtk_vdec_h264_find_start_code(unsigned char *data, unsigned int data_s= z) +{ + if (data_sz > 3 && data[0] =3D=3D 0 && data[1] =3D=3D 0 && data[2] =3D=3D= 1) + return 3; + + if (data_sz > 4 && data[0] =3D=3D 0 && data[1] =3D=3D 0 && data[2] =3D=3D= 0 && + data[3] =3D=3D 1) + return 4; + + return -1; +} diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_common.h = b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_common.h new file mode 100644 index 000000000000..71372fcae168 --- /dev/null +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_common.h @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Yunfei Dong + */ + +#ifndef _VDEC_H264_REQ_COMMON_H_ +#define _VDEC_H264_REQ_COMMON_H_ + +#include +#include +#include +#include +#include + +#include "../mtk_vcodec_drv.h" + +#define NAL_NON_IDR_SLICE 0x01 +#define NAL_IDR_SLICE 0x05 +#define NAL_TYPE(value) ((value) & 0x1F) + +#define BUF_PREDICTION_SZ (64 * 4096) +#define MB_UNIT_LEN 16 + +/* motion vector size (bytes) for every macro block */ +#define HW_MB_STORE_SZ 64 + +#define H264_MAX_MV_NUM 32 + +/** + * struct mtk_h264_dpb_info - h264 dpb information + * @y_dma_addr: Y bitstream physical address + * @c_dma_addr: CbCr bitstream physical address + * @reference_flag: reference picture flag (short/long term reference pict= ure) + * @field: field picture flag + */ +struct mtk_h264_dpb_info { + dma_addr_t y_dma_addr; + dma_addr_t c_dma_addr; + int reference_flag; + int field; +}; + +/** + * struct mtk_h264_sps_param - parameters for sps + */ +struct mtk_h264_sps_param { + unsigned char chroma_format_idc; + unsigned char bit_depth_luma_minus8; + unsigned char bit_depth_chroma_minus8; + unsigned char log2_max_frame_num_minus4; + unsigned char pic_order_cnt_type; + unsigned char log2_max_pic_order_cnt_lsb_minus4; + unsigned char max_num_ref_frames; + unsigned char separate_colour_plane_flag; + unsigned short pic_width_in_mbs_minus1; + unsigned short pic_height_in_map_units_minus1; + unsigned int max_frame_nums; + unsigned char qpprime_y_zero_transform_bypass_flag; + unsigned char delta_pic_order_always_zero_flag; + unsigned char frame_mbs_only_flag; + unsigned char mb_adaptive_frame_field_flag; + unsigned char direct_8x8_inference_flag; + unsigned char reserved[3]; +}; + +/** + * struct mtk_h264_pps_param - parameters for pps + */ +struct mtk_h264_pps_param { + unsigned char num_ref_idx_l0_default_active_minus1; + unsigned char num_ref_idx_l1_default_active_minus1; + unsigned char weighted_bipred_idc; + char pic_init_qp_minus26; + char chroma_qp_index_offset; + char second_chroma_qp_index_offset; + unsigned char entropy_coding_mode_flag; + unsigned char pic_order_present_flag; + unsigned char deblocking_filter_control_present_flag; + unsigned char constrained_intra_pred_flag; + unsigned char weighted_pred_flag; + unsigned char redundant_pic_cnt_present_flag; + unsigned char transform_8x8_mode_flag; + unsigned char scaling_matrix_present_flag; + unsigned char reserved[2]; +}; + +/** + * struct mtk_h264_slice_hd_param - parameters for slice header + */ +struct mtk_h264_slice_hd_param { + unsigned int first_mb_in_slice; + unsigned int field_pic_flag; + unsigned int slice_type; + unsigned int frame_num; + int pic_order_cnt_lsb; + int delta_pic_order_cnt_bottom; + unsigned int bottom_field_flag; + unsigned int direct_spatial_mv_pred_flag; + int delta_pic_order_cnt0; + int delta_pic_order_cnt1; + unsigned int cabac_init_idc; + int slice_qp_delta; + unsigned int disable_deblocking_filter_idc; + int slice_alpha_c0_offset_div2; + int slice_beta_offset_div2; + unsigned int num_ref_idx_l0_active_minus1; + unsigned int num_ref_idx_l1_active_minus1; + unsigned int reserved; +}; + +struct slice_api_h264_scaling_matrix { + unsigned char scaling_list_4x4[6][16]; + unsigned char scaling_list_8x8[6][64]; +}; + +struct slice_h264_dpb_entry { + unsigned long long reference_ts; + unsigned short frame_num; + unsigned short pic_num; + /* Note that field is indicated by v4l2_buffer.field */ + int top_field_order_cnt; + int bottom_field_order_cnt; + unsigned int flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ +}; + +/** + * struct slice_api_h264_decode_param - parameters for decode. + */ +struct slice_api_h264_decode_param { + struct slice_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]; + unsigned short num_slices; + unsigned short nal_ref_idc; + unsigned char ref_pic_list_p0[32]; + unsigned char ref_pic_list_b0[32]; + unsigned char ref_pic_list_b1[32]; + int top_field_order_cnt; + int bottom_field_order_cnt; + unsigned int flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ +}; + +/** + * struct h264_fb - h264 decode frame buffer information + * @vdec_fb_va : virtual address of struct vdec_fb + * @y_fb_dma : dma address of Y frame buffer (luma) + * @c_fb_dma : dma address of C frame buffer (chroma) + * @poc : picture order count of frame buffer + * @reserved : for 8 bytes alignment + */ +struct h264_fb { + uint64_t vdec_fb_va; + uint64_t y_fb_dma; + uint64_t c_fb_dma; + int32_t poc; + uint32_t reserved; +}; + +/** + * mtk_vdec_h264_get_ctrl_ptr - get each CID contrl address. + * @ctx: v4l2 ctx + * @id: CID control ID + */ +void *mtk_vdec_h264_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id); + +/** + * mtk_vdec_h264_fill_dpb_info - get each CID contrl address. + * @ctx: v4l2 ctx + * @decode_params: slice decode params + * @h264_dpb_info: dpb buffer information + */ +void mtk_vdec_h264_fill_dpb_info(struct mtk_vcodec_ctx *ctx, + struct slice_api_h264_decode_param *decode_params, + struct mtk_h264_dpb_info *h264_dpb_info); + +/** + * mtk_vdec_h264_copy_sps_params - get sps params. + * @dst_params: sps params for hw decoder + * @src_params: sps params from user driver + */ +void mtk_vdec_h264_copy_sps_params(struct mtk_h264_sps_param *dst_param, + const struct v4l2_ctrl_h264_sps *src_param); + +/** + * mtk_vdec_h264_copy_pps_params - get pps params. + * @dst_params: pps params for hw decoder + * @src_params: pps params from user driver + */ +void mtk_vdec_h264_copy_pps_params(struct mtk_h264_pps_param *dst_param, + const struct v4l2_ctrl_h264_pps *src_param); + +/** + * mtk_vdec_h264_copy_slice_hd_params - get slice header params. + * @dst_params: slice params for hw decoder + * @src_params: slice params from user driver + * @dec_param: decode params from user driver + */ +void mtk_vdec_h264_copy_slice_hd_params( + struct mtk_h264_slice_hd_param *dst_param, + const struct v4l2_ctrl_h264_slice_params *src_param, + const struct v4l2_ctrl_h264_decode_params *dec_param); + +/** + * mtk_vdec_h264_copy_scaling_matrix - get each CID contrl address. + * @dst_matrix: scaling list params for hw decoder + * @src_matrix: scaling list params from user driver + */ +void mtk_vdec_h264_copy_scaling_matrix( + struct slice_api_h264_scaling_matrix *dst_matrix, + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix); + +/** + * mtk_vdec_h264_copy_decode_params - get decode params. + * @dst_params: dst params for hw decoder + * @src_params: decode params from user driver + * @dpb: dpb information + */ +void mtk_vdec_h264_copy_decode_params( + struct slice_api_h264_decode_param *dst_params, + const struct v4l2_ctrl_h264_decode_params *src_params, + const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]); + + +/** + * mtk_vdec_h264_update_dpb - updata dpb list. + * @dec_param: v4l2 control decode params + * @dpb: dpb entry informaton + */ +void mtk_vdec_h264_update_dpb( + const struct v4l2_ctrl_h264_decode_params *dec_param, + struct v4l2_h264_dpb_entry *dpb); + +/** + * mtk_vdec_h264_find_start_code - find h264 start code using sofeware. + * @data: input buffer address + * @data_sz: input buffer size + */ +int mtk_vdec_h264_find_start_code(unsigned char *data, unsigned int data_s= z); + +/** + * mtk_vdec_h264_get_mv_buf_size - get mv buffer size. + * @width: picture width + * @height: picture height + */ +unsigned int mtk_vdec_h264_get_mv_buf_size( + unsigned int width, unsigned int height); + +#endif diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c b/dr= ivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c index d00219a7587c..1c92e71e7fa0 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_if.c @@ -12,109 +12,7 @@ #include "../vdec_drv_base.h" #include "../vdec_drv_if.h" #include "../vdec_vpu_if.h" - -#define BUF_PREDICTION_SZ (64 * 4096) -#define MB_UNIT_LEN 16 - -/* get used parameters for sps/pps */ -#define GET_MTK_VDEC_FLAG(cond, flag) \ - { dst_param->cond =3D ((src_param->flags & (flag)) ? (1) : (0)); } -#define GET_MTK_VDEC_PARAM(param) \ - { dst_param->param =3D src_param->param; } -/* motion vector size (bytes) for every macro block */ -#define HW_MB_STORE_SZ 64 - -#define H264_MAX_FB_NUM 17 -#define H264_MAX_MV_NUM 32 -#define HDR_PARSING_BUF_SZ 1024 - -/** - * struct mtk_h264_dpb_info - h264 dpb information - * @y_dma_addr: Y bitstream physical address - * @c_dma_addr: CbCr bitstream physical address - * @reference_flag: reference picture flag (short/long term reference pict= ure) - * @field: field picture flag - */ -struct mtk_h264_dpb_info { - dma_addr_t y_dma_addr; - dma_addr_t c_dma_addr; - int reference_flag; - int field; -}; - -/* - * struct mtk_h264_sps_param - parameters for sps - */ -struct mtk_h264_sps_param { - unsigned char chroma_format_idc; - unsigned char bit_depth_luma_minus8; - unsigned char bit_depth_chroma_minus8; - unsigned char log2_max_frame_num_minus4; - unsigned char pic_order_cnt_type; - unsigned char log2_max_pic_order_cnt_lsb_minus4; - unsigned char max_num_ref_frames; - unsigned char separate_colour_plane_flag; - unsigned short pic_width_in_mbs_minus1; - unsigned short pic_height_in_map_units_minus1; - unsigned int max_frame_nums; - unsigned char qpprime_y_zero_transform_bypass_flag; - unsigned char delta_pic_order_always_zero_flag; - unsigned char frame_mbs_only_flag; - unsigned char mb_adaptive_frame_field_flag; - unsigned char direct_8x8_inference_flag; - unsigned char reserved[3]; -}; - -/* - * struct mtk_h264_pps_param - parameters for pps - */ -struct mtk_h264_pps_param { - unsigned char num_ref_idx_l0_default_active_minus1; - unsigned char num_ref_idx_l1_default_active_minus1; - unsigned char weighted_bipred_idc; - char pic_init_qp_minus26; - char chroma_qp_index_offset; - char second_chroma_qp_index_offset; - unsigned char entropy_coding_mode_flag; - unsigned char pic_order_present_flag; - unsigned char deblocking_filter_control_present_flag; - unsigned char constrained_intra_pred_flag; - unsigned char weighted_pred_flag; - unsigned char redundant_pic_cnt_present_flag; - unsigned char transform_8x8_mode_flag; - unsigned char scaling_matrix_present_flag; - unsigned char reserved[2]; -}; - -struct slice_api_h264_scaling_matrix { - unsigned char scaling_list_4x4[6][16]; - unsigned char scaling_list_8x8[6][64]; -}; - -struct slice_h264_dpb_entry { - unsigned long long reference_ts; - unsigned short frame_num; - unsigned short pic_num; - /* Note that field is indicated by v4l2_buffer.field */ - int top_field_order_cnt; - int bottom_field_order_cnt; - unsigned int flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ -}; - -/* - * struct slice_api_h264_decode_param - parameters for decode. - */ -struct slice_api_h264_decode_param { - struct slice_h264_dpb_entry dpb[16]; - unsigned short num_slices; - unsigned short nal_ref_idc; - unsigned char ref_pic_list_p0[32]; - unsigned char ref_pic_list_b0[32]; - unsigned char ref_pic_list_b1[32]; - int top_field_order_cnt; - int bottom_field_order_cnt; - unsigned int flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ -}; +#include "vdec_h264_req_common.h" =20 /* * struct mtk_h264_dec_slice_param - parameters for decode current frame @@ -127,22 +25,6 @@ struct mtk_h264_dec_slice_param { struct mtk_h264_dpb_info h264_dpb_info[16]; }; =20 -/** - * struct h264_fb - h264 decode frame buffer information - * @vdec_fb_va : virtual address of struct vdec_fb - * @y_fb_dma : dma address of Y frame buffer (luma) - * @c_fb_dma : dma address of C frame buffer (chroma) - * @poc : picture order count of frame buffer - * @reserved : for 8 bytes alignment - */ -struct h264_fb { - u64 vdec_fb_va; - u64 y_fb_dma; - u64 c_fb_dma; - s32 poc; - u32 reserved; -}; - /** * struct vdec_h264_dec_info - decode information * @dpb_sz : decoding picture buffer size @@ -212,233 +94,6 @@ struct vdec_h264_slice_inst { struct v4l2_h264_dpb_entry dpb[16]; }; =20 -static void *get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) -{ - struct v4l2_ctrl *ctrl =3D v4l2_ctrl_find(&ctx->ctrl_hdl, id); - - return ctrl->p_cur.p; -} - -static void get_h264_dpb_list(struct vdec_h264_slice_inst *inst, - struct mtk_h264_dec_slice_param *slice_param) -{ - struct vb2_queue *vq; - struct vb2_buffer *vb; - struct vb2_v4l2_buffer *vb2_v4l2; - u64 index; - - vq =3D v4l2_m2m_get_vq(inst->ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MP= LANE); - - for (index =3D 0; index < ARRAY_SIZE(slice_param->decode_params.dpb); ind= ex++) { - const struct slice_h264_dpb_entry *dpb; - int vb2_index; - - dpb =3D &slice_param->decode_params.dpb[index]; - if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) { - slice_param->h264_dpb_info[index].reference_flag =3D 0; - continue; - } - - vb2_index =3D vb2_find_timestamp(vq, dpb->reference_ts, 0); - if (vb2_index < 0) { - mtk_vcodec_err(inst, "Reference invalid: dpb_index(%lld) reference_ts(%= lld)", - index, dpb->reference_ts); - continue; - } - /* 1 for short term reference, 2 for long term reference */ - if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) - slice_param->h264_dpb_info[index].reference_flag =3D 1; - else - slice_param->h264_dpb_info[index].reference_flag =3D 2; - - vb =3D vq->bufs[vb2_index]; - vb2_v4l2 =3D container_of(vb, struct vb2_v4l2_buffer, vb2_buf); - slice_param->h264_dpb_info[index].field =3D vb2_v4l2->field; - - slice_param->h264_dpb_info[index].y_dma_addr =3D - vb2_dma_contig_plane_dma_addr(vb, 0); - if (inst->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) { - slice_param->h264_dpb_info[index].c_dma_addr =3D - vb2_dma_contig_plane_dma_addr(vb, 1); - } - } -} - -static void get_h264_sps_parameters(struct mtk_h264_sps_param *dst_param, - const struct v4l2_ctrl_h264_sps *src_param) -{ - GET_MTK_VDEC_PARAM(chroma_format_idc); - GET_MTK_VDEC_PARAM(bit_depth_luma_minus8); - GET_MTK_VDEC_PARAM(bit_depth_chroma_minus8); - GET_MTK_VDEC_PARAM(log2_max_frame_num_minus4); - GET_MTK_VDEC_PARAM(pic_order_cnt_type); - GET_MTK_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); - GET_MTK_VDEC_PARAM(max_num_ref_frames); - GET_MTK_VDEC_PARAM(pic_width_in_mbs_minus1); - GET_MTK_VDEC_PARAM(pic_height_in_map_units_minus1); - - GET_MTK_VDEC_FLAG(separate_colour_plane_flag, - V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE); - GET_MTK_VDEC_FLAG(qpprime_y_zero_transform_bypass_flag, - V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); - GET_MTK_VDEC_FLAG(delta_pic_order_always_zero_flag, - V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); - GET_MTK_VDEC_FLAG(frame_mbs_only_flag, - V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); - GET_MTK_VDEC_FLAG(mb_adaptive_frame_field_flag, - V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); - GET_MTK_VDEC_FLAG(direct_8x8_inference_flag, - V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); -} - -static void get_h264_pps_parameters(struct mtk_h264_pps_param *dst_param, - const struct v4l2_ctrl_h264_pps *src_param) -{ - GET_MTK_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); - GET_MTK_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); - GET_MTK_VDEC_PARAM(weighted_bipred_idc); - GET_MTK_VDEC_PARAM(pic_init_qp_minus26); - GET_MTK_VDEC_PARAM(chroma_qp_index_offset); - GET_MTK_VDEC_PARAM(second_chroma_qp_index_offset); - - GET_MTK_VDEC_FLAG(entropy_coding_mode_flag, - V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); - GET_MTK_VDEC_FLAG(pic_order_present_flag, - V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); - GET_MTK_VDEC_FLAG(weighted_pred_flag, - V4L2_H264_PPS_FLAG_WEIGHTED_PRED); - GET_MTK_VDEC_FLAG(deblocking_filter_control_present_flag, - V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); - GET_MTK_VDEC_FLAG(constrained_intra_pred_flag, - V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); - GET_MTK_VDEC_FLAG(redundant_pic_cnt_present_flag, - V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); - GET_MTK_VDEC_FLAG(transform_8x8_mode_flag, - V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); - GET_MTK_VDEC_FLAG(scaling_matrix_present_flag, - V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); -} - -static void -get_h264_scaling_matrix(struct slice_api_h264_scaling_matrix *dst_matrix, - const struct v4l2_ctrl_h264_scaling_matrix *src_matrix) -{ - memcpy(dst_matrix->scaling_list_4x4, src_matrix->scaling_list_4x4, - sizeof(dst_matrix->scaling_list_4x4)); - - memcpy(dst_matrix->scaling_list_8x8, src_matrix->scaling_list_8x8, - sizeof(dst_matrix->scaling_list_8x8)); -} - -static void -get_h264_decode_parameters(struct slice_api_h264_decode_param *dst_params, - const struct v4l2_ctrl_h264_decode_params *src_params, - const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(dst_params->dpb); i++) { - struct slice_h264_dpb_entry *dst_entry =3D &dst_params->dpb[i]; - const struct v4l2_h264_dpb_entry *src_entry =3D &dpb[i]; - - dst_entry->reference_ts =3D src_entry->reference_ts; - dst_entry->frame_num =3D src_entry->frame_num; - dst_entry->pic_num =3D src_entry->pic_num; - dst_entry->top_field_order_cnt =3D src_entry->top_field_order_cnt; - dst_entry->bottom_field_order_cnt =3D - src_entry->bottom_field_order_cnt; - dst_entry->flags =3D src_entry->flags; - } - - /* - * num_slices is a leftover from the old H.264 support and is ignored - * by the firmware. - */ - dst_params->num_slices =3D 0; - dst_params->nal_ref_idc =3D src_params->nal_ref_idc; - dst_params->top_field_order_cnt =3D src_params->top_field_order_cnt; - dst_params->bottom_field_order_cnt =3D src_params->bottom_field_order_cnt; - dst_params->flags =3D src_params->flags; -} - -static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, - const struct v4l2_h264_dpb_entry *b) -{ - return a->top_field_order_cnt =3D=3D b->top_field_order_cnt && - a->bottom_field_order_cnt =3D=3D b->bottom_field_order_cnt; -} - -/* - * Move DPB entries of dec_param that refer to a frame already existing in= dpb - * into the already existing slot in dpb, and move other entries into new = slots. - * - * This function is an adaptation of the similarly-named function in - * hantro_h264.c. - */ -static void update_dpb(const struct v4l2_ctrl_h264_decode_params *dec_para= m, - struct v4l2_h264_dpb_entry *dpb) -{ - DECLARE_BITMAP(new, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; - DECLARE_BITMAP(in_use, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; - DECLARE_BITMAP(used, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; - unsigned int i, j; - - /* Disable all entries by default, and mark the ones in use. */ - for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) - set_bit(i, in_use); - dpb[i].flags &=3D ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; - } - - /* Try to match new DPB entries with existing ones by their POCs. */ - for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { - const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; - - if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) - continue; - - /* - * To cut off some comparisons, iterate only on target DPB - * entries were already used. - */ - for_each_set_bit(j, in_use, ARRAY_SIZE(dec_param->dpb)) { - struct v4l2_h264_dpb_entry *cdpb; - - cdpb =3D &dpb[j]; - if (!dpb_entry_match(cdpb, ndpb)) - continue; - - *cdpb =3D *ndpb; - set_bit(j, used); - /* Don't reiterate on this one. */ - clear_bit(j, in_use); - break; - } - - if (j =3D=3D ARRAY_SIZE(dec_param->dpb)) - set_bit(i, new); - } - - /* For entries that could not be matched, use remaining free slots. */ - for_each_set_bit(i, new, ARRAY_SIZE(dec_param->dpb)) { - const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; - struct v4l2_h264_dpb_entry *cdpb; - - /* - * Both arrays are of the same sizes, so there is no way - * we can end up with no space in target array, unless - * something is buggy. - */ - j =3D find_first_zero_bit(used, ARRAY_SIZE(dec_param->dpb)); - if (WARN_ON(j >=3D ARRAY_SIZE(dec_param->dpb))) - return; - - cdpb =3D &dpb[j]; - *cdpb =3D *ndpb; - set_bit(j, used); - } -} - /* * The firmware expects unused reflist entries to have the value 0x20. */ @@ -450,27 +105,32 @@ static void fixup_ref_list(u8 *ref_list, size_t num_v= alid) static void get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst) { const struct v4l2_ctrl_h264_decode_params *dec_params =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_DECODE_PARAMS); const struct v4l2_ctrl_h264_sps *sps =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS); + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_SPS); const struct v4l2_ctrl_h264_pps *pps =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX); + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_SCALING_MATRIX); struct mtk_h264_dec_slice_param *slice_param =3D &inst->h264_slice_param; struct v4l2_h264_reflist_builder reflist_builder; u8 *p0_reflist =3D slice_param->decode_params.ref_pic_list_p0; u8 *b0_reflist =3D slice_param->decode_params.ref_pic_list_b0; u8 *b1_reflist =3D slice_param->decode_params.ref_pic_list_b1; =20 - update_dpb(dec_params, inst->dpb); + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); =20 - get_h264_sps_parameters(&slice_param->sps, sps); - get_h264_pps_parameters(&slice_param->pps, pps); - get_h264_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix); - get_h264_decode_parameters(&slice_param->decode_params, dec_params, - inst->dpb); - get_h264_dpb_list(inst, slice_param); + mtk_vdec_h264_copy_sps_params(&slice_param->sps, sps); + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); + mtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, + scaling_matrix); + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, + dec_params, inst->dpb); + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, + slice_param->h264_dpb_info); =20 /* Build the reference lists */ v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, @@ -486,13 +146,6 @@ static void get_vdec_decode_parameters(struct vdec_h26= 4_slice_inst *inst) sizeof(inst->vsi_ctx.h264_slice_params)); } =20 -static unsigned int get_mv_buf_size(unsigned int width, unsigned int heigh= t) -{ - int unit_size =3D (width / MB_UNIT_LEN) * (height / MB_UNIT_LEN) + 8; - - return HW_MB_STORE_SZ * unit_size; -} - static int allocate_predication_buf(struct vdec_h264_slice_inst *inst) { int err; @@ -525,7 +178,7 @@ static int alloc_mv_buf(struct vdec_h264_slice_inst *in= st, int i; int err; struct mtk_vcodec_mem *mem =3D NULL; - unsigned int buf_sz =3D get_mv_buf_size(pic->buf_w, pic->buf_h); + unsigned int buf_sz =3D mtk_vdec_h264_get_mv_buf_size(pic->buf_w, pic->bu= f_h); =20 mtk_v4l2_debug(3, "size =3D 0x%x", buf_sz); for (i =3D 0; i < H264_MAX_MV_NUM; i++) { @@ -674,7 +327,8 @@ static int vdec_h264_slice_decode(void *h_vdec, struct = mtk_vcodec_mem *bs, { struct vdec_h264_slice_inst *inst =3D h_vdec; const struct v4l2_ctrl_h264_decode_params *dec_params =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_DECODE_PARAMS); struct vdec_vpu_inst *vpu =3D &inst->vpu; struct mtk_video_dec_buf *src_buf_info; struct mtk_video_dec_buf *dst_buf_info; --=20 2.25.1 From nobody Sun Sep 22 11:46:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72EE2C43217 for ; Tue, 4 Jan 2022 08:02:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233857AbiADICU (ORCPT ); Tue, 4 Jan 2022 03:02:20 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:53498 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231294AbiADICF (ORCPT ); Tue, 4 Jan 2022 03:02:05 -0500 X-UUID: 749f77bc4bac4966842cf59d2d89e995-20220104 X-UUID: 749f77bc4bac4966842cf59d2d89e995-20220104 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1655764792; Tue, 04 Jan 2022 16:02:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jan 2022 16:02:00 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 4 Jan 2022 16:01:59 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , Steve Cho , , , , , , , Subject: [PATCH 13/13] media: mtk-vcodec: Add h264 decoder driver for mt8192 Date: Tue, 4 Jan 2022 16:01:38 +0800 Message-ID: <20220104080138.7472-14-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104080138.7472-1-yunfei.dong@mediatek.com> References: <20220104080138.7472-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds h264 lat and core driver for mt8192, and the decode mode is frame based for stateless decoder. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/Makefile | 1 + .../mtk-vcodec/vdec/vdec_h264_req_lat_if.c | 620 ++++++++++++++++++ .../media/platform/mtk-vcodec/vdec_drv_if.c | 8 +- .../media/platform/mtk-vcodec/vdec_drv_if.h | 1 + include/linux/remoteproc/mtk_scp.h | 2 + 5 files changed, 631 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_la= t_if.c diff --git a/drivers/media/platform/mtk-vcodec/Makefile b/drivers/media/pla= tform/mtk-vcodec/Makefile index 3f41d748eee5..1777d7606f0d 100644 --- a/drivers/media/platform/mtk-vcodec/Makefile +++ b/drivers/media/platform/mtk-vcodec/Makefile @@ -10,6 +10,7 @@ mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp9_if.o \ vdec/vdec_h264_req_if.o \ vdec/vdec_h264_req_common.o \ + vdec/vdec_h264_req_lat_if.o \ mtk_vcodec_dec_drv.o \ vdec_drv_if.o \ vdec_vpu_if.o \ diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_lat_if.c = b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_lat_if.c new file mode 100644 index 000000000000..403d7df00e1d --- /dev/null +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_lat_if.c @@ -0,0 +1,620 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Yunfei Dong + */ + +#include +#include +#include +#include +#include + +#include "../mtk_vcodec_util.h" +#include "../mtk_vcodec_dec.h" +#include "../mtk_vcodec_intr.h" +#include "../vdec_drv_base.h" +#include "../vdec_drv_if.h" +#include "../vdec_vpu_if.h" +#include "vdec_h264_req_common.h" + +/** + * enum vdec_h264_core_dec_err_type - core decode error type + */ +enum vdec_h264_core_dec_err_type { + TRANS_BUFFER_FULL =3D 1, + SLICE_HEADER_FULL, +}; + +/** + * struct vdec_h264_slice_lat_dec_param - parameters for decode current f= rame + * @sps : h264 sps syntax parameters + * @pps : h264 pps syntax parameters + * @slice_header: h264 slice header syntax parameters + * @scaling_matrix : h264 scaling list parameters + * @decode_params : decoder parameters of each frame used for hardware dec= ode + * @h264_dpb_info : dpb reference list + */ +struct vdec_h264_slice_lat_dec_param { + struct mtk_h264_sps_param sps; + struct mtk_h264_pps_param pps; + struct mtk_h264_slice_hd_param slice_header; + struct slice_api_h264_scaling_matrix scaling_matrix; + struct slice_api_h264_decode_param decode_params; + struct mtk_h264_dpb_info h264_dpb_info[V4L2_H264_NUM_DPB_ENTRIES]; +}; + +/** + * struct vdec_h264_slice_info - decode information + * @nal_info : nal info of current picture + * @timeout : Decode timeout: 1 timeout, 0 no timeount + * @bs_buf_size : bitstream size + * @bs_buf_addr : bitstream buffer dma address + * @y_fb_dma : Y frame buffer dma address + * @c_fb_dma : C frame buffer dma address + * @vdec_fb_va : VDEC frame buffer struct virtual address + * @crc : Used to check whether hardware's status is right + */ +struct vdec_h264_slice_info { + uint16_t nal_info; + uint16_t timeout; + uint32_t bs_buf_size; + uint64_t bs_buf_addr; + uint64_t y_fb_dma; + uint64_t c_fb_dma; + uint64_t vdec_fb_va; + uint32_t crc[8]; +}; + +/** + * struct vdec_h264_slice_vsi - shared memory for decode information excha= nge + * between VPU and Host. The memory is allocated by VPU then mappin= g to + * Host in vdec_h264_slice_init() and freed in vdec_h264_slice_dein= it() + * by VPU. AP-W/R : AP is writer/reader on this item. VPU-W/R: VPU = is + * write/reader on this item. + * @wdma_err_addr : wdma error dma address + * @wdma_start_addr : wdma start dma address + * @wdma_end_addr : wdma end dma address + * @slice_bc_start_addr : slice bc start dma address + * @slice_bc_end_addr : slice bc end dma address + * @row_info_start_addr : row info start dma address + * @row_info_end_addr : row info end dma address + * @trans_start : trans start dma address + * @trans_end : trans end dma address + * @wdma_end_addr_offset: wdma end address offset + * @mv_buf_dma : HW working motion vector buffer + * dma address (AP-W, VPU-R) + * @dec : decode information (AP-R, VPU-W) + * @h264_slice_params : decode parameters for hw used + */ +struct vdec_h264_slice_vsi { + /* LAT dec addr */ + uint64_t wdma_err_addr; + uint64_t wdma_start_addr; + uint64_t wdma_end_addr; + uint64_t slice_bc_start_addr; + uint64_t slice_bc_end_addr; + uint64_t row_info_start_addr; + uint64_t row_info_end_addr; + uint64_t trans_start; + uint64_t trans_end; + uint64_t wdma_end_addr_offset; + + uint64_t mv_buf_dma[H264_MAX_MV_NUM]; + struct vdec_h264_slice_info dec; + struct vdec_h264_slice_lat_dec_param h264_slice_params; +}; + +/** + * struct vdec_h264_slice_share_info - shared information used to exchange + * message between lat and core + * @sps : sequence header information from user space + * @dec_params : decoder params from user space + * @h264_slice_params : decoder params used for hardware + * @trans_start : trans start dma address + * @trans_end : trans end dma address + * @nal_info : nal info of current picture + */ +struct vdec_h264_slice_share_info { + struct v4l2_ctrl_h264_sps sps; + struct v4l2_ctrl_h264_decode_params dec_params; + struct vdec_h264_slice_lat_dec_param h264_slice_params; + uint64_t trans_start; + uint64_t trans_end; + uint16_t nal_info; +}; + +/** + * struct vdec_h264_slice_inst - h264 decoder instance + * @num_nalu : how many nalus be decoded + * @ctx : point to mtk_vcodec_ctx + * @pred_buf : HW working predication buffer + * @mv_buf : HW working motion vector buffer + * @vpu : VPU instance + * @vsi : vsi used for lat + * @vsi_core : vsi used for core + * @resolution_changed : resolution changed + * @realloc_mv_buf : reallocate mv buffer + * @cap_num_planes : number of capture queue plane + */ +struct vdec_h264_slice_inst { + unsigned int num_nalu; + struct mtk_vcodec_ctx *ctx; + struct mtk_vcodec_mem pred_buf; + struct mtk_vcodec_mem mv_buf[H264_MAX_MV_NUM]; + struct vdec_vpu_inst vpu; + struct vdec_h264_slice_vsi *vsi; + struct vdec_h264_slice_vsi *vsi_core; + + unsigned int resolution_changed; + unsigned int realloc_mv_buf; + unsigned int cap_num_planes; + + struct v4l2_h264_dpb_entry dpb[16]; +}; + +static void vdec_h264_slice_fill_decode_parameters( + struct vdec_h264_slice_inst *inst, + struct vdec_h264_slice_share_info *share_info) +{ + struct vdec_h264_slice_lat_dec_param *slice_param =3D + &inst->vsi->h264_slice_params; + const struct v4l2_ctrl_h264_decode_params *dec_params =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_DECODE_PARAMS); + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_SCALING_MATRIX); + const struct v4l2_ctrl_h264_sps *sps =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_SPS); + const struct v4l2_ctrl_h264_pps *pps =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, + V4L2_CID_STATELESS_H264_PPS); + + mtk_vdec_h264_copy_sps_params(&slice_param->sps,sps); + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); + mtk_vdec_h264_copy_scaling_matrix( + &slice_param->scaling_matrix, src_matrix); + + memcpy(&share_info->sps, sps, sizeof(*sps)); + memcpy(&share_info->dec_params, dec_params, sizeof(*dec_params)); +} + +/* + * The firmware expects unused reflist entries to have the value 0x20. + */ +static void fixup_ref_list(u8 *ref_list, size_t num_valid) +{ + memset(&ref_list[num_valid], 0x20, 32 - num_valid); +} + +static void vdec_h264_slice_fill_decode_reflist( + struct vdec_h264_slice_inst *inst, + struct vdec_h264_slice_lat_dec_param *slice_param, + struct vdec_h264_slice_share_info *share_info) +{ + struct v4l2_ctrl_h264_decode_params *dec_params =3D &share_info->dec_para= ms; + struct v4l2_ctrl_h264_sps *sps =3D &share_info->sps; + struct v4l2_h264_reflist_builder reflist_builder; + u8 *p0_reflist =3D slice_param->decode_params.ref_pic_list_p0; + u8 *b0_reflist =3D slice_param->decode_params.ref_pic_list_b0; + u8 *b1_reflist =3D slice_param->decode_params.ref_pic_list_b1; + + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); + + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, dec_params, + inst->dpb); + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, + slice_param->h264_dpb_info); + + mtk_v4l2_debug(3, "cur poc =3D %d\n", dec_params->bottom_field_order_cnt); + /* Build the reference lists */ + v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, + inst->dpb); + v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); + v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); + + /* Adapt the built lists to the firmware's expectations */ + fixup_ref_list(p0_reflist, reflist_builder.num_valid); + fixup_ref_list(b0_reflist, reflist_builder.num_valid); + fixup_ref_list(b1_reflist, reflist_builder.num_valid); +} + +static int vdec_h264_slice_alloc_mv_buf(struct vdec_h264_slice_inst *inst, + struct vdec_pic_info *pic) +{ + int i; + int err; + struct mtk_vcodec_mem *mem; + unsigned int buf_sz =3D mtk_vdec_h264_get_mv_buf_size( + pic->buf_w, pic->buf_h); + + mtk_v4l2_debug(3, "size =3D 0x%x", buf_sz); + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + mem->size =3D buf_sz; + err =3D mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "failed to allocate mv buf"); + return err; + } + } + + return 0; +} + +static void vdec_h264_slice_free_mv_buf(struct vdec_h264_slice_inst *inst) +{ + int i; + struct mtk_vcodec_mem *mem; + + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + } +} + +static void vdec_h264_slice_get_pic_info(struct vdec_h264_slice_inst *inst) +{ + struct mtk_vcodec_ctx *ctx =3D inst->ctx; + unsigned int data[3]; + + data[0] =3D ctx->picinfo.pic_w; + data[1] =3D ctx->picinfo.pic_h; + data[2] =3D ctx->capture_fourcc; + vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); + + ctx->picinfo.buf_w =3D ALIGN(ctx->picinfo.pic_w, 64); + ctx->picinfo.buf_h =3D ALIGN(ctx->picinfo.pic_h, 64); + ctx->picinfo.fb_sz[0] =3D inst->vpu.fb_sz[0]; + ctx->picinfo.fb_sz[1] =3D inst->vpu.fb_sz[1]; + inst->cap_num_planes =3D + ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; + + mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", + ctx->picinfo.pic_w, ctx->picinfo.pic_h, + ctx->picinfo.buf_w, ctx->picinfo.buf_h); + mtk_vcodec_debug(inst, "Y/C(%d, %d)", ctx->picinfo.fb_sz[0], + ctx->picinfo.fb_sz[1]); + + if ((ctx->last_decoded_picinfo.pic_w !=3D ctx->picinfo.pic_w) || + (ctx->last_decoded_picinfo.pic_h !=3D ctx->picinfo.pic_h)) { + inst->resolution_changed =3D true; + if ((ctx->last_decoded_picinfo.buf_w !=3D ctx->picinfo.buf_w) || + (ctx->last_decoded_picinfo.buf_h !=3D ctx->picinfo.buf_h)) + inst->realloc_mv_buf =3D true; + + mtk_v4l2_debug(1, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)", + inst->resolution_changed, + inst->realloc_mv_buf, + ctx->last_decoded_picinfo.pic_w, + ctx->last_decoded_picinfo.pic_h, + ctx->picinfo.pic_w, ctx->picinfo.pic_h); + } +} + +static void vdec_h264_slice_get_crop_info(struct vdec_h264_slice_inst *ins= t, + struct v4l2_rect *cr) +{ + cr->left =3D 0; + cr->top =3D 0; + cr->width =3D inst->ctx->picinfo.pic_w; + cr->height =3D inst->ctx->picinfo.pic_h; + + mtk_vcodec_debug(inst, "l=3D%d, t=3D%d, w=3D%d, h=3D%d", + cr->left, cr->top, cr->width, cr->height); +} + +static int vdec_h264_slice_init(struct mtk_vcodec_ctx *ctx) +{ + struct vdec_h264_slice_inst *inst; + int err, vsi_size; + + inst =3D kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx =3D ctx; + + inst->vpu.id =3D SCP_IPI_VDEC_LAT; + inst->vpu.core_id =3D SCP_IPI_VDEC_CORE; + inst->vpu.ctx =3D ctx; + inst->vpu.codec_type =3D ctx->current_codec; + inst->vpu.capture_type =3D ctx->capture_fourcc; + + err =3D vpu_dec_init(&inst->vpu); + if (err) { + mtk_vcodec_err(inst, "vdec_h264 init err=3D%d", err); + goto error_free_inst; + } + + vsi_size =3D round_up(sizeof(struct vdec_h264_slice_vsi), 64); + inst->vsi =3D inst->vpu.vsi; + inst->vsi_core =3D + (struct vdec_h264_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size); + inst->resolution_changed =3D true; + inst->realloc_mv_buf =3D true; + + mtk_vcodec_debug(inst, "lat struct size =3D %d,%d,%d,%d vsi: %d\n", + (int)sizeof(struct mtk_h264_sps_param), + (int)sizeof(struct mtk_h264_pps_param), + (int)sizeof(struct vdec_h264_slice_lat_dec_param), + (int)sizeof(struct mtk_h264_dpb_info), + vsi_size); + mtk_vcodec_debug(inst, "lat H264 instance >> %p, codec_type =3D 0x%x", + inst, inst->vpu.codec_type); + + ctx->drv_handle =3D inst; + return 0; + +error_free_inst: + kfree(inst); + return err; +} + +static void vdec_h264_slice_deinit(void *h_vdec) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + + mtk_vcodec_debug_enter(inst); + + vpu_dec_deinit(&inst->vpu); + vdec_h264_slice_free_mv_buf(inst); + vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + + kfree(inst); +} + +static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) +{ + struct vdec_fb *fb; + uint64_t vdec_fb_va; + uint64_t y_fb_dma, c_fb_dma; + int err, timeout, i, dec_err; + struct vdec_vpu_inst *vpu; + struct mtk_vcodec_ctx *ctx =3D lat_buf->ctx; + struct vdec_h264_slice_inst *inst =3D ctx->drv_handle; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vdec_h264_slice_share_info *share_info =3D lat_buf->private_data; + struct mtk_vcodec_mem *mem; + + mtk_vcodec_debug(inst, "[h264-core] vdec_h264 core decode"); + memcpy(&inst->vsi_core->h264_slice_params, &share_info->h264_slice_params, + sizeof(share_info->h264_slice_params)); + fb =3D ctx->dev->vdec_pdata->get_cap_buffer(ctx); + vpu =3D &inst->vpu; + vdec_fb_va =3D (unsigned long)fb; + y_fb_dma =3D fb ? (u64)fb->base_y.dma_addr : 0; + + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 1) + c_fb_dma =3D + y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; + else + c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; + + mtk_vcodec_debug(inst, "[h264-core] y/c addr =3D 0x%llx 0x%llx", y_fb_dma, + c_fb_dma); + + inst->vsi_core->dec.y_fb_dma =3D y_fb_dma; + inst->vsi_core->dec.c_fb_dma =3D c_fb_dma; + inst->vsi_core->dec.vdec_fb_va =3D vdec_fb_va; + inst->vsi_core->dec.nal_info =3D share_info->nal_info; + inst->vsi_core->wdma_start_addr =3D + lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi_core->wdma_end_addr =3D + lat_buf->ctx->msg_queue.wdma_addr.dma_addr + + lat_buf->ctx->msg_queue.wdma_addr.size; + inst->vsi_core->wdma_err_addr =3D lat_buf->wdma_err_addr.dma_addr; + inst->vsi_core->slice_bc_start_addr =3D lat_buf->slice_bc_addr.dma_addr; + inst->vsi_core->slice_bc_end_addr =3D lat_buf->slice_bc_addr.dma_addr + + lat_buf->slice_bc_addr.size; + inst->vsi_core->trans_start =3D share_info->trans_start; + inst->vsi_core->trans_end =3D share_info->trans_end; + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi_core->mv_buf_dma[i] =3D mem->dma_addr; + } + + vb2_v4l2 =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + vb2_v4l2->vb2_buf.timestamp =3D lat_buf->ts_info.vb2_buf.timestamp; + vb2_v4l2->timecode =3D lat_buf->ts_info.timecode; + vb2_v4l2->field =3D lat_buf->ts_info.field; + vb2_v4l2->flags =3D lat_buf->ts_info.flags; + vb2_v4l2->vb2_buf.copied_timestamp =3D + lat_buf->ts_info.vb2_buf.copied_timestamp; + + vdec_h264_slice_fill_decode_reflist(inst, + &inst->vsi_core->h264_slice_params, share_info); + + err =3D vpu_dec_core(vpu); + if (err) { + dec_err =3D 1; + mtk_vcodec_err(inst, "core decode err=3D%d", err); + goto vdec_dec_end; + } else { + dec_err =3D 0; + } + + /* wait decoder done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx( + inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (timeout) + mtk_vcodec_err(inst, "core decode timeout: pic_%d", + ctx->decoded_frame_cnt); + inst->vsi_core->dec.timeout =3D !!timeout; + + vpu_dec_core_end(vpu); + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0= x%x", + ctx->decoded_frame_cnt, + inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1], + inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3], + inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5], + inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]); +vdec_dec_end: + vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, + inst->vsi_core->trans_end); + ctx->dev->vdec_pdata->cap_to_disp(ctx, fb, dec_err); + mtk_vcodec_debug(inst, "core decode done err=3D%d", err); + ctx->decoded_frame_cnt++; + + return 0; +} + +static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info; + int nal_start_idx, err, timeout =3D 0, i; + unsigned int nal_type, data[2]; + struct vdec_lat_buf *lat_buf; + struct vdec_h264_slice_share_info *share_info; + unsigned char *buf; + struct mtk_vcodec_mem *mem; + + mtk_vcodec_debug(inst, "+ [%d] ", ++inst->num_nalu); + + if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx, + vdec_h264_slice_core_decode, sizeof(*share_info))) + return -ENOMEM; + + /* bs NULL means flush decoder */ + if (!bs) { + vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue); + return vpu_dec_reset(vpu); + } + + lat_buf =3D vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vcodec_err(inst, "failed to get lat buffer"); + return -EINVAL; + } + share_info =3D lat_buf->private_data; + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + + buf =3D (unsigned char *)bs->va; + nal_start_idx =3D mtk_vdec_h264_find_start_code(buf, bs->size); + if (nal_start_idx < 0) { + err =3D -EINVAL; + goto err_free_fb_out; + } + + inst->vsi->dec.nal_info =3D buf[nal_start_idx]; + nal_type =3D NAL_TYPE(buf[nal_start_idx]); + mtk_vcodec_debug(inst, "\n + NALU[%d] type %d +\n", inst->num_nalu, + nal_type); + + inst->vsi->dec.bs_buf_addr =3D (uint64_t)bs->dma_addr; + inst->vsi->dec.bs_buf_size =3D bs->size; + + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, + &lat_buf->ts_info, true); + + vdec_h264_slice_fill_decode_parameters(inst, share_info); + *res_chg =3D inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vcodec_debug(inst, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err =3D vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf =3D false; + if (err) + goto err_free_fb_out; + } + inst->resolution_changed =3D false; + } + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi->mv_buf_dma[i] =3D mem->dma_addr; + } + inst->vsi->wdma_start_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi->wdma_end_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma_addr + + lat_buf->ctx->msg_queue.wdma_addr.size; + inst->vsi->wdma_err_addr =3D lat_buf->wdma_err_addr.dma_addr; + inst->vsi->slice_bc_start_addr =3D lat_buf->slice_bc_addr.dma_addr; + inst->vsi->slice_bc_end_addr =3D lat_buf->slice_bc_addr.dma_addr + + lat_buf->slice_bc_addr.size; + + inst->vsi->trans_end =3D inst->ctx->msg_queue.wdma_rptr_addr; + inst->vsi->trans_start =3D inst->ctx->msg_queue.wdma_wptr_addr; + mtk_vcodec_debug(inst, "lat:trans(0x%llx 0x%llx)err:0x%llx", + inst->vsi->wdma_start_addr, + inst->vsi->wdma_end_addr, + inst->vsi->wdma_err_addr); + + mtk_vcodec_debug(inst, "slice(0x%llx 0x%llx) rprt((0x%llx 0x%llx))", + inst->vsi->slice_bc_start_addr, + inst->vsi->slice_bc_end_addr, + inst->vsi->trans_start, + inst->vsi->trans_end); + err =3D vpu_dec_start(vpu, data, 2); + if (err) { + mtk_vcodec_debug(inst, "lat decode err: %d", err); + goto err_free_fb_out; + } + + if (nal_type =3D=3D NAL_NON_IDR_SLICE || nal_type =3D=3D NAL_IDR_SLICE) { + /* wait decoder done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx( + inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); + inst->vsi->dec.timeout =3D !!timeout; + } + err =3D vpu_dec_end(vpu); + if (err =3D=3D SLICE_HEADER_FULL || timeout || err =3D=3D TRANS_BUFFER_FU= LL) { + err =3D -EINVAL; + goto err_free_fb_out; + } + + share_info->trans_end =3D inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi->wdma_end_addr_offset; + share_info->trans_start =3D inst->ctx->msg_queue.wdma_wptr_addr; + share_info->nal_info =3D inst->vsi->dec.nal_info; + vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, + share_info->trans_end); + + memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params, + sizeof(share_info->h264_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf); + mtk_vcodec_debug(inst, "- NALU[%d] type=3D%d -\n", inst->num_nalu, + nal_type); + return 0; + +err_free_fb_out: + mtk_vcodec_err(inst, "- NALU[%d] err=3D%d -\n", inst->num_nalu, err); + return err; +} + +static int vdec_h264_slice_get_param(void *h_vdec, + enum vdec_get_param_type type, void *out) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + + switch (type) { + case GET_PARAM_PIC_INFO: + vdec_h264_slice_get_pic_info(inst); + break; + case GET_PARAM_DPB_SIZE: + *(unsigned int *)out =3D 6; + break; + case GET_PARAM_CROP_INFO: + vdec_h264_slice_get_crop_info(inst, out); + break; + default: + mtk_vcodec_err(inst, "invalid get parameter type=3D%d", type); + return -EINVAL; + } + return 0; +} + +const struct vdec_common_if vdec_h264_slice_lat_if =3D { + .init =3D vdec_h264_slice_init, + .decode =3D vdec_h264_slice_decode, + .get_param =3D vdec_h264_slice_get_param, + .deinit =3D vdec_h264_slice_deinit, +}; diff --git a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c b/drivers/medi= a/platform/mtk-vcodec/vdec_drv_if.c index c93dd0ea3537..c17a7815e1bb 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec_drv_if.c @@ -20,7 +20,13 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned in= t fourcc) =20 switch (fourcc) { case V4L2_PIX_FMT_H264_SLICE: - ctx->dec_if =3D &vdec_h264_slice_if; + if (ctx->dev->vdec_pdata->hw_arch =3D=3D MTK_VDEC_PURE_SINGLE_CORE) { + ctx->dec_if =3D &vdec_h264_slice_if; + ctx->hw_id =3D MTK_VDEC_CORE; + } else { + ctx->dec_if =3D &vdec_h264_slice_lat_if; + ctx->hw_id =3D MTK_VDEC_LAT0; + } break; case V4L2_PIX_FMT_H264: ctx->dec_if =3D &vdec_h264_if; diff --git a/drivers/media/platform/mtk-vcodec/vdec_drv_if.h b/drivers/medi= a/platform/mtk-vcodec/vdec_drv_if.h index d467e8af4a84..6ce848e74167 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_drv_if.h +++ b/drivers/media/platform/mtk-vcodec/vdec_drv_if.h @@ -56,6 +56,7 @@ struct vdec_fb_node { =20 extern const struct vdec_common_if vdec_h264_if; extern const struct vdec_common_if vdec_h264_slice_if; +extern const struct vdec_common_if vdec_h264_slice_lat_if; extern const struct vdec_common_if vdec_vp8_if; extern const struct vdec_common_if vdec_vp9_if; =20 diff --git a/include/linux/remoteproc/mtk_scp.h b/include/linux/remoteproc/= mtk_scp.h index b47416f7aeb8..a32ffd736e7b 100644 --- a/include/linux/remoteproc/mtk_scp.h +++ b/include/linux/remoteproc/mtk_scp.h @@ -41,6 +41,8 @@ enum scp_ipi_id { SCP_IPI_ISP_FRAME, SCP_IPI_FD_CMD, SCP_IPI_CROS_HOST_CMD, + SCP_IPI_VDEC_LAT, + SPC_IPI_VDEC_CORE, SCP_IPI_NS_SERVICE =3D 0xFF, SCP_IPI_MAX =3D 0x100, }; --=20 2.25.1