From nobody Wed Jul 1 03:08:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4307CC433FE for ; Mon, 3 Jan 2022 07:48:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232040AbiACHsA (ORCPT ); Mon, 3 Jan 2022 02:48:00 -0500 Received: from st43p00im-zteg10073501.me.com ([17.58.63.180]:57874 "EHLO st43p00im-zteg10073501.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232027AbiACHr7 (ORCPT ); Mon, 3 Jan 2022 02:47:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1641196079; bh=2YbMTcQIr5y6YcT0ka7hcRvxxoTx5VI1wckXwfdlRH4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZzbLVWOEkbV/v/cLEdaCSPRjm3gYHrvRi/zZT2y+2iAyBOz+KWPPubAAFIaejRUNL PPtLiydzh671kqw3W2Pp2/NJQXlrXi2x1N4DHbnC7nO+ire09pcI02Tcvlebnb5Y8G 8KSEq+OFLBAvjE3Bm/Cg4M68LhB0LHfYfwJYyM0CICXk4+5H5ZNnkjxU/RG0V0ADho X5n72nvhB0ApO2sTSRHGaXZbjHmHuSsd/ByGMAtW/TTe1dKL0xmr8jDwc9M3bvpPXh UU3RQLD0SgSY1aWE1V+Y88KETrFVA44VvELkYbPMFlKlsJxi0LcsYU8ItKKi5v1Elu gLExFAx93K72Q== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-zteg10073501.me.com (Postfix) with ESMTPSA id 62A4736078A; Mon, 3 Jan 2022 07:47:58 +0000 (UTC) From: Alain Volmat To: Rob Herring , linux-pci@vger.kernel.org Cc: Patrice Chotard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabrice Gasnier , avolmat@me.com Subject: [PATCH RESEND v2 1/5] dt-bindings: pci: st-pcie: PCIe controller found on STi platforms Date: Mon, 3 Jan 2022 08:47:27 +0100 Message-Id: <20220103074731.3651-2-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220103074731.3651-1-avolmat@me.com> References: <20220103074731.3651-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425,18.0.790 definitions=2022-01-03_02:2022-01-01,2022-01-03 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2201030052 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Addition of the bindings for the Designware based PCIe controller that can be found on STi platforms such as STiH407, STiH410 or STiH418. Signed-off-by: Alain Volmat --- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- .../devicetree/bindings/pci/st,st-pcie.yaml | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/st,st-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Docu= mentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 9ed0dfba7f89..3a92078128f7 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -35,7 +35,7 @@ properties: maxItems: 5 items: enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, li= nk, - ulreg, smu, mpu, apb, phy ] + ulreg, smu, mpu, apb, phy, mem-window ] =20 num-lanes: description: | diff --git a/Documentation/devicetree/bindings/pci/st,st-pcie.yaml b/Docume= ntation/devicetree/bindings/pci/st,st-pcie.yaml new file mode 100644 index 000000000000..2fa686d573c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,st-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on ST STi platform + +maintainers: + - Alain Volmat + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: st,stih407-pcie + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Memory made available to the controller + + reg-names: + items: + - const: dbi + - const: config + - const: mem-window + + interrupts: + maxItems: 1 + + resets: + items: + - description: Controller reset + - description: Powerdown reset (optional) + minItems: 1 + + reset-names: + items: + - const: softreset + - const: powerdown + minItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: true + + st,syscfg: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: syscfg node phandle and offsets of the 2 registers + controlling root complex and ltssm. + +required: + - interrupts + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + - resets + - reset-names + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + pcie1: pcie@9b10000 { + compatible =3D "st,stih407-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x09b10000 0x1000>, + <0x3fff0000 0x10000>, + <0x40000000 0xc0000000>; + reg-names =3D "dbi", "config", "mem-window"; + + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-names =3D "msi"; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + st,syscfg =3D <&syscfg_core 0xdc 0xe4>; + + ranges =3D <0x82000000 0 0x30000000 0x30000000 0 0x05550000>, /* non= -prefetchable memory */ + <0xc2000000 0 0x35550000 0x35550000 0 0x0AAA0000>; /* prefe= tchable memory */ + bus-range =3D <0x00 0xff>; + + resets =3D <&softreset STIH407_PCIE1_SOFTRESET>, + <&powerdown STIH407_PCIE1_POWERDOWN>; + + reset-names =3D "softreset", "powerdown"; + + phys =3D <&phy_port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie"; + + reset-gpios =3D <&pio34 5 GPIO_ACTIVE_LOW>; + }; --=20 2.25.1 From nobody Wed Jul 1 03:08:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48633C433F5 for ; Mon, 3 Jan 2022 07:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232045AbiACHsG (ORCPT ); Mon, 3 Jan 2022 02:48:06 -0500 Received: from st43p00im-ztdg10071801.me.com ([17.58.63.171]:43430 "EHLO st43p00im-ztdg10071801.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232027AbiACHsE (ORCPT ); Mon, 3 Jan 2022 02:48:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1641196084; bh=zFaYY1g+/NPb8ajEgqtLXK2DXFsX6UH0DHg0WqFZZ6M=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Ypco8NgLBB9JnIh3Uy00RvpPl9h1z173YBKfD77upsuNQvQLHRK8q0Mq+ZjYduS+8 9uILh4OI+oszDFgKcJH/bj2GTedc6DLAUfv9gTLtOXpGy7WV8IW6A/VpN6iYmnq/36 i4O+P8QK6QAys/KzXXKM+BmYectT915w3GNCQFfsKT2VV4oEvKevXuRmxM75W1xSGG qe0RV5SJPG+uhVoLiTXTzT2Y+XRy1Z0QTJAM+GsX3ITRNFVj2ID5KaubLPH2UWHH4c Ye8ghKZH2wkJESw1XvH9Rredv49RnTYieNwATLe8k2nEy+bk3nP4VaijbIDXvGxtLr RjSTpOxHXBRkA== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-ztdg10071801.me.com (Postfix) with ESMTPSA id 48DD53C095F; Mon, 3 Jan 2022 07:48:03 +0000 (UTC) From: Alain Volmat To: Rob Herring , linux-pci@vger.kernel.org Cc: Patrice Chotard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabrice Gasnier , avolmat@me.com Subject: [PATCH RESEND v2 2/5] pci: dwc: pcie-st: Add PCIe driver for STi platforms Date: Mon, 3 Jan 2022 08:47:28 +0100 Message-Id: <20220103074731.3651-3-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220103074731.3651-1-avolmat@me.com> References: <20220103074731.3651-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.425,18.0.790,17.11.62.513.0000000_definitions?= =?UTF-8?Q?=3D2022-01-03=5F02:2022-01-01=5F01,2022-01-03=5F02,2021-12-02?= =?UTF-8?Q?=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2201030052 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Addition of the PCIe driver (supporting RC) for controllers found on some STi platforms such as STiH407, STiH410 or STiH418. The controller is based on the designware PCIe controller. Signed-off-by: Alain Volmat --- v2: update of the pcie-st driver to add possibility to build as module and remove the __init of the probe drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-sti.c | 386 ++++++++++++++++++++++++++ 3 files changed, 398 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-sti.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index 62ce3abf0f19..232b8ffd54af 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -384,4 +384,15 @@ config PCIE_FU740 Say Y here if you want PCIe controller support for the SiFive FU740. =20 +config PCIE_STI + tristate "STMicroelectronics PCIe Controller for STi SoCs" + depends on ARCH_STI || COMPILE_TEST + depends on OF && PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Enable PCIe controller support on STMicroelectronics STi SoCs. + This controller is based on Designware hardware and therefore + the driver re-uses the Designware core functions to implement + the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 8ba7b67f5e50..c98fa18714ce 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_KEEMBAY) +=3D pcie-keembay.o obj-$(CONFIG_PCIE_KIRIN) +=3D pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) +=3D pcie-histb.o obj-$(CONFIG_PCI_MESON) +=3D pci-meson.o +obj-$(CONFIG_PCIE_STI) +=3D pcie-sti.o obj-$(CONFIG_PCIE_TEGRA194) +=3D pcie-tegra194.o obj-$(CONFIG_PCIE_UNIPHIER) +=3D pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) +=3D pcie-uniphier-ep.o diff --git a/drivers/pci/controller/dwc/pcie-sti.c b/drivers/pci/controller= /dwc/pcie-sti.c new file mode 100644 index 000000000000..61da00a079ac --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-sti.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 STMicroelectronics + * + * STMicroelectronics PCI express Driver for STi SoCs. + * ST PCIe IPs are built around a Synopsys IP Core. + * + * Authors: Fabrice Gasnier + * Alain Volmat + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +/* RC_ADDRESS_TRANSLATION Registers */ +#define TRANSLATION_CONTROL 0x900 +/* Controls if area is inclusive or exclusive */ +#define RC_PASS_ADDR_RANGE BIT(1) + +/* Base of area reserved for config accesses. Fixed size of 64K. */ +#define CFG_BASE_ADDRESS 0x92c +#define CFG_REGION_SIZE 65536 +#define CFG_SPACE1_OFFSET 0x1000 + +/* First 4K of config space has this BDF (bus,device,function) */ +#define FUNC0_BDF_NUM 0x930 + +/* Mem regions */ +#define IN0_MEM_ADDR_START 0x964 +#define IN0_MEM_ADDR_LIMIT 0x968 +#define IN1_MEM_ADDR_START 0x974 +#define IN1_MEM_ADDR_LIMIT 0x978 + +/* syscfg1 bits */ +#define PCIE_APP_LTSSM_ENABLE BIT(2) +/* syscfg0 bits */ +#define PCIE_TYPE_ROOT_COMPLEX BIT(0) + +/* st,syscfg offsets */ +#define SYSCFG0_REG 1 +#define SYSCFG1_REG 2 + +#define to_st_pcie(x) dev_get_drvdata((x)->dev) + +/** + * struct st_pcie - private data of the controller + * @dw: designware pcie + * @syscfg0: PCIe conf register setting root complex, regmap offset + * @syscfg1: PCIe conf register for PCIE_APP_LTSSM_ENABLE, regmap offset + * @phy: associated pcie phy + * @lmi: memory made available to the controller + * @regmap: Syscfg registers bank in which PCIe port is configured + * @pwr: power control + * @rst: reset control + * @reset_gpio: optional reset gpio + * @config_window_start: start address of 64K config space area + */ +struct st_pcie { + struct dw_pcie *dw; + int syscfg0; + int syscfg1; + struct phy *phy; + struct resource *lmi; + struct regmap *regmap; + struct reset_control *pwr; + struct reset_control *rst; + struct gpio_desc *reset_gpio; + phys_addr_t config_window_start; +}; + +/* + * The PCI express core IP expects the following arrangement on it's addre= ss + * bus (slv_haddr) when driving config cycles. + * bus_number [31:24] + * dev_number [23:19] + * func_number [18:16] + * unused [15:12] + * ext_reg_number [11:8] + * reg_number [7:2] + * + * Bits [15:12] are unused. + * + * In the glue logic there is a 64K region of address space that can be + * written/read to generate config cycles. The base address of this is + * controlled by CFG_BASE_ADDRESS. There are 8 16 bit registers called + * FUNC0_BDF_NUM to FUNC8_BDF_NUM. These split the bottom half of the 64K + * window into 8 regions at 4K boundaries. These control the bus, device a= nd + * function number you are trying to talk to. + * + * The decision on whether to generate a type 0 or type 1 access is contro= lled + * by bits 15:12 of the address you write to. If they are zero, then a ty= pe 0 + * is generated, if anything else it will be a type 1. Thus the bottom 4K + * region controlled by FUNC0_BDF_NUM can only generate type 0, all the ot= hers + * can only generate type 1. + * + * We only use FUNC0_BDF_NUM and FUNC1_BDF_NUM. Which one you use is selec= ted + * by bit 12 of the address you write to. The selected register is then us= ed + * for the top 16 bits of the slv_haddr to form the bus/dev/func, bit 15:1= 2 are + * wired to zero, and bits 11:2 form the address of the register you want = to + * read in config space. + * + * We always write FUNC0_BDF_NUM as a 32 bit write. So if we want type 1 + * accesses we have to shift by 16 so in effect we are writing to FUNC1_BD= F_NUM + */ +static inline u32 bdf_num(int bus, int devfn, int is_root_bus) +{ + return ((bus << 8) | devfn) << (is_root_bus ? 0 : 16); +} + +static void __iomem *st_pcie_other_map_bus(struct pci_bus *bus, unsigned i= nt devfn, int where) +{ + struct pcie_port *pp =3D bus->sysdata; + struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); + u32 bdf; + + bdf =3D bdf_num(bus->number, devfn, pci_is_root_bus(bus)); + + /* Set the config packet devfn */ + dw_pcie_writel_dbi(dw, FUNC0_BDF_NUM, bdf); + dw_pcie_readl_dbi(dw, FUNC0_BDF_NUM); + + return pp->va_cfg0_base + where + (pci_is_root_bus(bus->parent) ? 0 : CFG= _SPACE1_OFFSET); +} + +static struct pci_ops st_child_pcie_ops =3D { + .map_bus =3D st_pcie_other_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, +}; + +static void st_pcie_hw_setup(struct dw_pcie *dw) +{ + struct st_pcie *pcie =3D to_st_pcie(dw); + + /* Set up the config window to the top of the PCI address space */ + dw_pcie_writel_dbi(dw, CFG_BASE_ADDRESS, pcie->config_window_start); + + /* + * Open up memory to the PCI controller. We could do slightly + * better than this and exclude the kernel text segment and bss etc. + * They are base/limit registers so can be of arbitrary alignment + * presumably + */ + dw_pcie_writel_dbi(dw, IN0_MEM_ADDR_START, pcie->lmi->start); + dw_pcie_writel_dbi(dw, IN0_MEM_ADDR_LIMIT, pcie->lmi->end); + + /* Disable the 2nd region */ + dw_pcie_writel_dbi(dw, IN1_MEM_ADDR_START, ~0); + dw_pcie_writel_dbi(dw, IN1_MEM_ADDR_LIMIT, 0); + + dw_pcie_writel_dbi(dw, TRANSLATION_CONTROL, RC_PASS_ADDR_RANGE); +} + +static int st_pcie_init(struct pcie_port *pp) +{ + struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); + struct st_pcie *pcie =3D to_st_pcie(dw); + int ret; + + /* Set device type : Root Complex */ + ret =3D regmap_write(pcie->regmap, pcie->syscfg0, PCIE_TYPE_ROOT_COMPLEX); + if (ret < 0) { + dev_err(dw->dev, "unable to set device type\n"); + return ret; + } + + ret =3D reset_control_deassert(pcie->pwr); + if (ret) { + dev_err(dw->dev, "unable to bring out of powerdown\n"); + return ret; + } + + ret =3D reset_control_deassert(pcie->rst); + if (ret) { + dev_err(dw->dev, "unable to bring out of softreset\n"); + return ret; + } + + /* let the controller initialize in the proper mode (RC) after reset */ + usleep_range(1000, 2000); + + return ret; +} + +static int st_pcie_control_ltssm(struct dw_pcie *dw, bool enable) +{ + struct st_pcie *pcie =3D to_st_pcie(dw); + + return regmap_update_bits(pcie->regmap, pcie->syscfg1, PCIE_APP_LTSSM_ENA= BLE, + FIELD_PREP(PCIE_APP_LTSSM_ENABLE, enable)); +} + +static int st_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); + struct st_pcie *pcie =3D to_st_pcie(dw); + int err; + + pcie->config_window_start =3D pp->cfg0_base; + + /* + * "Override" default ops provided by designware driver as STI + * PCIe uses its own translation unit rather than iATU + */ + pp->bridge->child_ops =3D &st_child_pcie_ops; + + /* + * We have to initialise the PCIe cell on some hardware before we can + * talk to the phy + */ + err =3D st_pcie_init(pp); + if (err) + return err; + + err =3D st_pcie_control_ltssm(dw, false); + if (err) { + dev_err(dw->dev, "disable ltssm failed, %d\n", err); + return err; + } + + /* Init the associated miphy */ + err =3D phy_init(pcie->phy); + if (err < 0) { + dev_err(dw->dev, "Cannot init PHY: %d\n", err); + return err; + } + + return 0; +} + +static int st_pcie_start_link(struct dw_pcie *dw) +{ + struct st_pcie *pcie =3D to_st_pcie(dw); + int err; + + /* Do all the register poking */ + st_pcie_hw_setup(dw); + + if (pcie->reset_gpio) { + /* Assert the PERST# signal */ + gpiod_set_value(pcie->reset_gpio, 1); + + /* PERST# signal must stay asserted for at least 100us (Tperst-clk) */ + usleep_range(100, 200); + + /* Release PERST# signal */ + gpiod_set_value(pcie->reset_gpio, 0); + } + + /* Re-enable the link, link training must begin shortly after reset */ + err =3D st_pcie_control_ltssm(dw, true); + if (err) { + dev_err(dw->dev, "enable ltssm failed, %d\n", err); + return err; + } + + err =3D dw_pcie_wait_for_link(dw); + if (err) { + dev_err(dw->dev, "wait for link failed, %d\n", err); + return err; + } + + /* + * PCIe specification states that you should not issue any config + * requests until 100ms after asserting reset, so we enforce that here + */ + if (pcie->reset_gpio) + msleep(100); + + return 0; +} + +static struct dw_pcie_host_ops st_pcie_host_ops =3D { + .host_init =3D st_pcie_host_init, +}; + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D st_pcie_start_link, +}; + +static int st_pcie_probe(struct platform_device *pdev) +{ + struct st_pcie *pcie; + struct dw_pcie *dw; + struct device_node *np =3D pdev->dev.of_node; + struct pcie_port *pp; + int ret; + + pcie =3D devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + dw =3D devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); + if (!dw) + return -ENOMEM; + pcie->dw =3D dw; + dw->dev =3D &pdev->dev; + dw->ops =3D &dw_pcie_ops; + + pp =3D &dw->pp; + pp->ops =3D &st_pcie_host_ops; + + /* mem regions */ + pcie->lmi =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem-win= dow"); + if (!pcie->lmi) + return -ENXIO; + + /* regmap registers for PCIe IP configuration */ + pcie->regmap =3D syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(pcie->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(pcie->regmap), + "No syscfg phandle specified\n"); + + ret =3D of_property_read_u32_index(np, "st,syscfg", SYSCFG0_REG, &pcie->s= yscfg0); + if (ret) { + dev_err(&pdev->dev, "can't get syscfg0 offset (%d)\n", ret); + return ret; + } + + ret =3D of_property_read_u32_index(np, "st,syscfg", SYSCFG1_REG, &pcie->s= yscfg1); + if (ret) { + dev_err(&pdev->dev, "can't get syscfg1 offset (%d)\n", ret); + return ret; + } + + /* powerdown / resets */ + pcie->pwr =3D devm_reset_control_get_optional(&pdev->dev, "powerdown"); + if (IS_ERR(pcie->pwr)) + return dev_err_probe(&pdev->dev, PTR_ERR(pcie->pwr), + "Error getting powerdown reset control\n"); + + pcie->rst =3D devm_reset_control_get(&pdev->dev, "softreset"); + if (IS_ERR(pcie->rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(pcie->rst), + "Error getting softreset control\n"); + + /* phy */ + pcie->phy =3D devm_phy_get(&pdev->dev, "pcie"); + if (IS_ERR(pcie->phy)) + return dev_err_probe(&pdev->dev, PTR_ERR(pcie->phy), "no PHY configured\= n"); + + /* Claim the GPIO for PRST# if available, keep it de-asserted */ + pcie->reset_gpio =3D devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_O= UT_LOW); + if (IS_ERR(pcie->reset_gpio)) + return dev_err_probe(&pdev->dev, PTR_ERR(pcie->reset_gpio), + "Cannot request reset-gpios\n"); + + platform_set_drvdata(pdev, pcie); + + ret =3D dw_pcie_host_init(pp); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to initialize host\n"); + + return 0; +} + +static const struct of_device_id st_pcie_of_match[] =3D { + { .compatible =3D "st,stih407-pcie", }, + { }, +}; +MODULE_DEVICE_TABLE(of, st_pcie_of_match); + +static struct platform_driver st_pcie_driver __refdata =3D { + .probe =3D st_pcie_probe, + .driver =3D { + .name =3D "st-pcie", + .of_match_table =3D st_pcie_of_match, + }, +}; +module_platform_driver(st_pcie_driver); + +MODULE_AUTHOR("Fabrice Gasnier "); +MODULE_AUTHOR("Alain Volmat "); +MODULE_DESCRIPTION("STi PCIe Controller driver"); +MODULE_LICENSE("GPL v2"); --=20 2.25.1 From nobody Wed Jul 1 03:08:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D48F6C433EF for ; Mon, 3 Jan 2022 07:48:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232046AbiACHsK (ORCPT ); Mon, 3 Jan 2022 02:48:10 -0500 Received: from st43p00im-ztdg10071801.me.com ([17.58.63.171]:44362 "EHLO st43p00im-ztdg10071801.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232059AbiACHsJ (ORCPT ); Mon, 3 Jan 2022 02:48:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1641196088; bh=+49ITMZhhvsylnROVwCGbQZMaN2WBTCcdJwitqIziGo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=iuEYyea0WuykOXRneeoWnaAg2GXJwqbrpsKpHseXugB63JtfzBjKQkHMAGJro2OL8 kfuDkRu+zviE9pGSum5kb0p2tGvHHT9nxtY4PXyKEg4FEzL2PcFjRjG1I+/MrbwCef QwfTIqBcrLI8j7/9F63PCklVezvZvtBHyaG1tT7u/UDtQ7wVmwoTi3BJOzkR/slKhP UhcrMDYMNxKiolSISMvXv0Zi/u8Jy62N68gw9LxEOBrb45tlCDZgGmia+3dM68KQ40 mJin584xEX8kpHTyQEJfhOtpAnzgNqomF2bNrvwbl8xTxMqY0rYR2raFOSF8hUXd+C 4t/2Y4oN4loMA== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-ztdg10071801.me.com (Postfix) with ESMTPSA id 65C2F3C02BD; Mon, 3 Jan 2022 07:48:07 +0000 (UTC) From: Alain Volmat To: Rob Herring , linux-pci@vger.kernel.org Cc: Patrice Chotard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabrice Gasnier , avolmat@me.com Subject: [PATCH RESEND v2 3/5] MAINTAINERS: add entry for ST STI PCIE driver Date: Mon, 3 Jan 2022 08:47:29 +0100 Message-Id: <20220103074731.3651-4-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220103074731.3651-1-avolmat@me.com> References: <20220103074731.3651-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425,18.0.790 definitions=2022-01-03_02:2022-01-01,2022-01-03 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2201030052 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCIE Driver entry for STI family from ST Microelectronics. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 360e9aa0205d..081ccdfbd89c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14666,6 +14666,12 @@ L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/pci-exynos.c =20 +PCI DRIVER FOR ST STI PLATFORM +M: Alain Volmat +L: linux-pci@vger.kernel.org +S: Maintained +F: drivers/pci/controller/dwc/pcie-sti.c + PCI DRIVER FOR SYNOPSYS DESIGNWARE M: Jingoo Han M: Gustavo Pimentel --=20 2.25.1 From nobody Wed Jul 1 03:08:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9B1AC433FE for ; Mon, 3 Jan 2022 07:48:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232085AbiACHsO (ORCPT ); Mon, 3 Jan 2022 02:48:14 -0500 Received: from st43p00im-ztdg10073201.me.com ([17.58.63.177]:45198 "EHLO st43p00im-ztdg10073201.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232070AbiACHsN (ORCPT ); Mon, 3 Jan 2022 02:48:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1641196092; bh=A2jhYOomsuOm4V0BEb9bdP5dTvI8ffnV0G50ioBK2m4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=jp1En/9A4+AlIU2j5cn+hooGGzKZNVOfDvrihi8x2e00Mkm7MIRUpRLthD6e0h9IR yj1CjnQuHhopaJOWHPOlrTJbje1/010jor0IQQLqs0M9gmaKjgMH9bQDd6c2qC9rO8 Jk8rW+Cwbjc7WL2j4Rk+WMTDMPXUuT7axGE21lvgzNAE6XrgJnc+o2Zb3OTgb+z1RF dUVwsHAHovTToor9GETYBXr+Qrfhz8Ty6FJfPngl6xizHhJmivvRUZsQlLwTmEZ681 cXpDqizKHiwQmvbO1Eh4CCh5opPQPaJRdcJ9tygR0qtsJdZYqbDtbLAQUTSSzG6SyX DpH1DpE011f6w== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-ztdg10073201.me.com (Postfix) with ESMTPSA id 486F49A009E; Mon, 3 Jan 2022 07:48:11 +0000 (UTC) From: Alain Volmat To: Rob Herring , linux-pci@vger.kernel.org Cc: Patrice Chotard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabrice Gasnier , avolmat@me.com Subject: [PATCH RESEND v2 4/5] ARM: dts: sti: add the PCIe controller node within stih407-family Date: Mon, 3 Jan 2022 08:47:30 +0100 Message-Id: <20220103074731.3651-5-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220103074731.3651-1-avolmat@me.com> References: <20220103074731.3651-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.425,18.0.790,17.11.62.513.0000000_definitions?= =?UTF-8?Q?=3D2022-01-03=5F01:2021-12-30=5F02,2022-01-03=5F01,2021-12-02?= =?UTF-8?Q?=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2201030052 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the pcie1 entry within stih407-family dtsi. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih407-family.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih= 407-family.dtsi index 21f3347a91d6..fe4ea2d5b583 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -631,6 +631,46 @@ spifsm: spifsm@9022000{ status =3D "disabled"; }; =20 + pcie1: pcie@9b10000 { + compatible =3D "st,stih407-pcie"; + device_type =3D "pci"; + reg =3D <0x09b10000 0x00001000>, /* cntrl registers */ + <0x3fff0000 0x00010000>, /* config space */ + <0x40000000 0xc0000000>; /* lmi mem window */ + + reg-names =3D "dbi", + "config", + "mem-window"; + + st,syscfg =3D <&syscfg_core 0xdc 0xe4>; + + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-names =3D "msi"; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + /* non-prefetchable and prefetchable */ + ranges =3D <0x82000000 0 0x30000000 0x30000000 0 0x05550000>, + <0xc2000000 0 0x35550000 0x35550000 0 0x0AAA0000>; + bus-range =3D <0x00 0xff>; + + resets =3D <&softreset STIH407_PCIE1_SOFTRESET>, + <&powerdown STIH407_PCIE1_POWERDOWN>; + + reset-names =3D "softreset", "powerdown"; + + phys =3D <&phy_port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie"; + + status =3D "disabled"; + }; + sata0: sata@9b20000 { compatible =3D "st,ahci"; reg =3D <0x9b20000 0x1000>; --=20 2.25.1 From nobody Wed Jul 1 03:08:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 258B2C433EF for ; Mon, 3 Jan 2022 07:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232059AbiACHsY (ORCPT ); Mon, 3 Jan 2022 02:48:24 -0500 Received: from st43p00im-zteg10072001.me.com ([17.58.63.167]:49124 "EHLO st43p00im-zteg10072001.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232084AbiACHsT (ORCPT ); Mon, 3 Jan 2022 02:48:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1641196098; bh=lSevOr7BAHftq5gxm26fGEC7mH3hZcAia+JHROve4Ww=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=iW/dvf83BPVpMA1Omhu3AylQPoL9dyQZp853xrBYySrkj8u/S4WinpaTsWkWEYzkK DaFrRRN0yjDfwVNkUZ8Lm2MSTwZhH8hCI6dmkiX/+e6WAQpL7Z9msS1fatsFNSU3SW BGO+j2O3uMiUUMDQi8+Mfo27mbqIC+PLBKMFUvaOBimLs98vb2Dyi9+QMGmdS/yHiS l5JiuuOy5Ic59657qwWdncji4p1SAR2QRy+uZYbn7NSW0TizdX5W5w2cP9IOqjo+ZF kI+mDJwdgnx1dFRGzgrU8fYK8bhoH8k52V9SzMe0yHpkqMUxyi2Dt+eUaJddUCScOQ 5aeqLG11JVHnA== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-zteg10072001.me.com (Postfix) with ESMTPSA id 3A503B40605; Mon, 3 Jan 2022 07:48:17 +0000 (UTC) From: Alain Volmat To: Rob Herring , linux-pci@vger.kernel.org Cc: Patrice Chotard , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabrice Gasnier , avolmat@me.com Subject: [PATCH RESEND v2 5/5] ARM: dts: sti: enable PCIe on the stih418-b2264 board Date: Mon, 3 Jan 2022 08:47:31 +0100 Message-Id: <20220103074731.3651-6-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220103074731.3651-1-avolmat@me.com> References: <20220103074731.3651-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425,18.0.790 definitions=2022-01-03_02:2022-01-01,2022-01-03 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=748 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2201030052 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the PCIe controller with proper reset gpio pin for this board. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih418-b2264.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/stih41= 8-b2264.dts index a99604bebf8c..ed183292a669 100644 --- a/arch/arm/boot/dts/stih418-b2264.dts +++ b/arch/arm/boot/dts/stih418-b2264.dts @@ -130,6 +130,11 @@ &ohci1 { status =3D "okay"; }; =20 +&pcie1 { + reset-gpios =3D <&pio34 5 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + &pwm1 { status =3D "okay"; }; --=20 2.25.1