From nobody Wed Jul 1 04:14:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72B94C433EF for ; Sun, 2 Jan 2022 16:57:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229627AbiABQ5k (ORCPT ); Sun, 2 Jan 2022 11:57:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229584AbiABQ5i (ORCPT ); Sun, 2 Jan 2022 11:57:38 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA8DDC061761; Sun, 2 Jan 2022 08:57:37 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id v6so3959017wra.8; Sun, 02 Jan 2022 08:57:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xY5sdN/MjZvpkzIVHRkalM0h2jmAhubj3ucgmZy/xLE=; b=i8OYmVcfHjMRcYo9XYExn4e2LNHOqCu1kTC+mLNyb1O47gYyzhvVI3sN2L7M8JFbvL qr5ahmw45IF7mWqD/M12tFe3IfZDoor+Jry72WbiuC1IzkXFrA2SS1uP1IygNh6NwInG cKzxx3gu0Any4MqLizbuaAL7Q7DlWh7mdjrQYsXpLEE7F5XXbKvEyndvSIZsir4xFqqk JuMD1OPQFzRbNiIqqbEvWGscH1wDS+sdXf2snHWc/It7j0+RplOnCyTVftHHhC90cEa4 bdP2Sh+pUK6cuSFcyrdeubEUH6mwkq8K3BmTKxEbvP0Xh6uFPpE0pc7QRFCZ5mZ0gXBJ cNfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xY5sdN/MjZvpkzIVHRkalM0h2jmAhubj3ucgmZy/xLE=; b=7/H2XtdSEeZnTpKN0/VLXfB40LGtVsJV8YM+pU1sNNGa/MC3+yDatNs5r3yF3fLEaJ GE4y/x+aOM8gCiEpa9/zojJShSO8uDcQryGT4TryS4aSU5U9AuQ+LJRW4fvCXScHkxJA cewVQrDcDhl1yQG4xlLd8ypWm6+IL106puFTf8x9foIwEZEXmuZTojRKlCMM6RzUtymr 3ruD7JG0G3qKfKqzfB+88z8eH/PS9zipWCFM8rqVnG0BPd+J1FTyxEfBloaph83m+/JD iMnMIphyqiyx0uzXVngs8aRkSZf+FDd1N65nOV6sWLPUbTOK3E4uzdPgl+NSeHoTghIL eRWA== X-Gm-Message-State: AOAM533JGgw9XYZ82BfSYFLRXUh9vfU65U2gvdEnqLnmJ/nDdRJijCgr 2MSFJmmlezw2wQCwW+0wonmP9DeYJVTCdw== X-Google-Smtp-Source: ABdhPJzdOuDFcSB38KIyoLrnqkve6qQFfKNS1W+N8l0uI2s/gbI4hx/9N/M6aAIWfb3msaI4TUvdGg== X-Received: by 2002:a05:6000:188c:: with SMTP id a12mr38138519wri.45.1641142655727; Sun, 02 Jan 2022 08:57:35 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id bg12sm40620846wmb.5.2022.01.02.08.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:35 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/9] dt-bindings: clk: mstar msc313 cpupll binding description Date: Sun, 2 Jan 2022 17:57:22 +0100 Message-Id: <20220102165730.50190-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring --- .../bindings/clock/mstar,msc313-cpupll.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cp= upll.yaml diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.ya= ml b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file mode 100644 index 000000000000..a9ad7ab5230c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 CPU PLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable + PLL that can be used as the clock source for the CPU(s). + +properties: + compatible: + const: mstar,msc313-cpupll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + cpupll: cpupll@206400 { + compatible =3D "mstar,msc313-cpupll"; + reg =3D <0x206400 0x200>; + #clock-cells =3D <1>; + clocks =3D <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; --=20 2.34.1 From nobody Wed Jul 1 04:14:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F5EAC433EF for ; Sun, 2 Jan 2022 16:57:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229584AbiABQ5m (ORCPT ); Sun, 2 Jan 2022 11:57:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229590AbiABQ5i (ORCPT ); Sun, 2 Jan 2022 11:57:38 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49670C061784; Sun, 2 Jan 2022 08:57:38 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id w20so56682671wra.9; Sun, 02 Jan 2022 08:57:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=99BhoIF0QsN7W+XiT4N4CxnrOHTqsGHcxK8UH/KZtro=; b=KOCIaEpm6tDeeo+B3T5cmjoKL3Bp9mqtD8XEwbpDj3cEgII7DlQyr+k8jQU7P2Y5eP dntEqXwFmilgB7IXS1YkgFUzx6mm//HWpjqvxezqhs+N90CZ6+Iz44rhfiiZNNtw9umC uHhMdiy0lKf1VNuHKQ93MPpu6XL/0LngHEUO8qPP6qRgph6vj3GTlL7P0jC8se7UnyTW aPY5fehD1PDiVwXUAfJkixhwqZcFwyHbJrEDAGp5Z4TeA3G48oT8dWrVzN3YlGxgMN1w 1Mx7CaRYCw2+5C2ToTju5E062yYGTDuXPuhQrF2ZvhTi+PjOaqt58QBVDk1Lw+Z5AhVI 1OnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=99BhoIF0QsN7W+XiT4N4CxnrOHTqsGHcxK8UH/KZtro=; b=0rlMr3PAaXMF3+ldGs4h8E4EzGd0M0SVexDCG7OQX/VB+/xvB0xcF3YupNDZNz4UAW Qbf74D48lZaxbGE0NUp0fJF6C6yJiK30geGKfSyR7glnIDCBd09rUB+c2ElmyxmvHFuP bLrrEuged5j8BrbqTAJz7BcI7do8Kzr15ppXT/ptS/ruNJ8PW76qe1EeC9VTQYs3n0R8 rr13eqVq5B7mfcBXJu5dGY0hzJLMSoo5bX07+cpUTmIAI/+mN8WgMgw5wKYgyWc9xXDR 0HIEPIzBGuNVf/m+3V8p+6nfkJGimz2Qo7CQORyC84+6i7qo6e3fAFc2QOlcaEdqJGvt L1Aw== X-Gm-Message-State: AOAM531e1tDo+QnRJmY3JlO3uhRh71FEIFhdQnjMpBwoE3AXVj5yRofO wNSQ+bP0iv/m9OJvZg49fqg= X-Google-Smtp-Source: ABdhPJxZrIuZ8nYgJgBvNM3coNHMtx4YqOjsLdm514ouixXAU2jO9pHfR9M5MCRnmUy3TqGbnW0UFg== X-Received: by 2002:a5d:588f:: with SMTP id n15mr36520972wrf.159.1641142656878; Sun, 02 Jan 2022 08:57:36 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id w6sm32567801wrs.52.2022.01.02.08.57.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:36 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v2 2/9] clk: mstar: msc313 cpupll clk driver Date: Sun, 2 Jan 2022 17:57:23 +0100 Message-Id: <20220102165730.50190-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer Add a driver for the CPU pll/ARM pll/MIPS pll that is present in MStar SoCs. Currently there is no documentation for this block so it's possible this driver isn't entirely correct. Only tested on the version of this IP in the MStar/SigmaStar ARMv7 SoCs. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- drivers/clk/mstar/Kconfig | 7 + drivers/clk/mstar/Makefile | 1 + drivers/clk/mstar/clk-msc313-cpupll.c | 227 ++++++++++++++++++++++++++ 3 files changed, 235 insertions(+) create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig index de37e1bce2d2..a44ca2b180ff 100644 --- a/drivers/clk/mstar/Kconfig +++ b/drivers/clk/mstar/Kconfig @@ -7,3 +7,10 @@ config MSTAR_MSC313_MPLL help Support for the MPLL PLL and dividers block present on MStar/Sigmastar SoCs. + +config MSTAR_MSC313_CPUPLL + bool "MStar CPUPLL driver" + depends on ARCH_MSTARV7 || COMPILE_TEST + default ARCH_MSTARV7 + help + Support for the CPU PLL present on MStar/Sigmastar SoCs. diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile index f8dcd25ede1d..9f05b73a0619 100644 --- a/drivers/clk/mstar/Makefile +++ b/drivers/clk/mstar/Makefile @@ -4,3 +4,4 @@ # =20 obj-$(CONFIG_MSTAR_MSC313_MPLL) +=3D clk-msc313-mpll.o +obj-$(CONFIG_MSTAR_MSC313_CPUPLL) +=3D clk-msc313-cpupll.o diff --git a/drivers/clk/mstar/clk-msc313-cpupll.c b/drivers/clk/mstar/clk-= msc313-cpupll.c new file mode 100644 index 000000000000..2229b16475eb --- /dev/null +++ b/drivers/clk/mstar/clk-msc313-cpupll.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Daniel Palmer + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * This IP is not documented outside of the messy vendor driver. + * Below is what we think the registers look like based on looking at + * the vendor code and poking at the hardware: + * + * 0x140 -- LPF low. Seems to store one half of the clock transition + * 0x144 / + * 0x148 -- LPF high. Seems to store one half of the clock transition + * 0x14c / + * 0x150 -- vendor code says "toggle lpf enable" + * 0x154 -- mu? + * 0x15c -- lpf_update_count? + * 0x160 -- vendor code says "switch to LPF". Clock source config? Registe= r bank? + * 0x164 -- vendor code says "from low to high" which seems to mean transi= tion from LPF low to + * LPF high. + * 0x174 -- Seems to be the PLL lock status bit + * 0x180 -- Seems to be the current frequency, this might need to be popul= ated by software? + * 0x184 / The vendor driver uses these to set the initial value of LPF l= ow + * + * Frequency seems to be calculated like this: + * (parent clock (432mhz) / register_magic_value) * 16 * 524288 + * Only the lower 24 bits of the resulting value will be used. In addition= , the + * PLL doesn't seem to be able to lock on frequencies lower than 220 MHz, = as + * divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up. + * + * Vendor values: + * frequency - register value + * + * 400000000 - 0x0067AE14 + * 600000000 - 0x00451EB8, + * 800000000 - 0x0033D70A, + * 1000000000 - 0x002978d4, + */ + +#define REG_LPF_LOW_L 0x140 +#define REG_LPF_LOW_H 0x144 +#define REG_LPF_HIGH_BOTTOM 0x148 +#define REG_LPF_HIGH_TOP 0x14c +#define REG_LPF_TOGGLE 0x150 +#define REG_LPF_MYSTERYTWO 0x154 +#define REG_LPF_UPDATE_COUNT 0x15c +#define REG_LPF_MYSTERYONE 0x160 +#define REG_LPF_TRANSITIONCTRL 0x164 +#define REG_LPF_LOCK 0x174 +#define REG_CURRENT 0x180 + +#define MULTIPLIER_1 16 +#define MULTIPLIER_2 524288 +#define MULTIPLIER (MULTIPLIER_1 * MULTIPLIER_2) + +struct msc313_cpupll { + void __iomem *base; + struct clk_hw clk_hw; +}; + +#define to_cpupll(_hw) container_of(_hw, struct msc313_cpupll, clk_hw) + +static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned= int reg) +{ + u32 value; + + value =3D ioread16(cpupll->base + reg + 4) << 16; + value |=3D ioread16(cpupll->base + reg); + + return value; +} + +static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsign= ed int reg, u32 value) +{ + u16 l =3D value & 0xffff, h =3D (value >> 16) & 0xffff; + + iowrite16(l, cpupll->base + reg); + iowrite16(h, cpupll->base + reg + 4); +} + +static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regval= ue) +{ + msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue); + + iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE); + iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO); + iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT); + iowrite16(BIT(12), cpupll->base + REG_LPF_TRANSITIONCTRL); + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + iowrite16(1, cpupll->base + REG_LPF_TOGGLE); + + while (!(ioread16(cpupll->base + REG_LPF_LOCK))) + cpu_relax(); + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue); +} + +static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long = parent_rate) +{ + unsigned long long prescaled =3D ((unsigned long long)parent_rate) * MULT= IPLIER; + unsigned long long scaled; + + if (prescaled =3D=3D 0 || reg =3D=3D 0) + return 0; + scaled =3D DIV_ROUND_DOWN_ULL(prescaled, reg); + + return scaled; +} + +static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long = parent_rate) +{ + unsigned long long prescaled =3D ((unsigned long long)parent_rate) * MULT= IPLIER; + unsigned long long scaled; + u32 reg; + + if (prescaled =3D=3D 0 || rate =3D=3D 0) + return 0; + + scaled =3D DIV_ROUND_UP_ULL(prescaled, rate); + reg =3D scaled; + + return reg; +} + +static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned= long parent_rate) +{ + struct msc313_cpupll *cpupll =3D to_cpupll(hw); + + return msc313_cpupll_frequencyforreg(msc313_cpupll_reg_read32(cpupll, REG= _LPF_LOW_L), + parent_rate); +} + +static long msc313_cpupll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 reg =3D msc313_cpupll_regforfrequecy(rate, *parent_rate); + long rounded =3D msc313_cpupll_frequencyforreg(reg, *parent_rate); + + /* + * This is my poor attempt at making sure the resulting + * rate doesn't overshoot the requested rate. + */ + for (; rounded >=3D rate && reg > 0; reg--) + rounded =3D msc313_cpupll_frequencyforreg(reg, *parent_rate); + + return rounded; +} + +static int msc313_cpupll_set_rate(struct clk_hw *hw, unsigned long rate, u= nsigned long parent_rate) +{ + struct msc313_cpupll *cpupll =3D to_cpupll(hw); + u32 reg =3D msc313_cpupll_regforfrequecy(rate, parent_rate); + + msc313_cpupll_setfreq(cpupll, reg); + + return 0; +} + +static const struct clk_ops msc313_cpupll_ops =3D { + .recalc_rate =3D msc313_cpupll_recalc_rate, + .round_rate =3D msc313_cpupll_round_rate, + .set_rate =3D msc313_cpupll_set_rate, +}; + +static const struct of_device_id msc313_cpupll_of_match[] =3D { + { + .compatible =3D "mstar,msc313-cpupll", + }, + {} +}; + +static const struct clk_parent_data cpupll_parent =3D { + .index =3D 0, +}; + +static int msc313_cpupll_probe(struct platform_device *pdev) +{ + struct clk_init_data clk_init =3D {}; + struct device *dev =3D &pdev->dev; + struct msc313_cpupll *cpupll; + int ret; + + cpupll =3D devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL); + if (!cpupll) + return -ENOMEM; + + cpupll->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cpupll->base)) + return PTR_ERR(cpupll->base); + + /* LPF might not contain the current frequency so fix that up */ + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, + msc313_cpupll_reg_read32(cpupll, REG_CURRENT)); + + clk_init.name =3D dev_name(dev); + clk_init.ops =3D &msc313_cpupll_ops; + clk_init.flags =3D CLK_IS_CRITICAL; + clk_init.parent_data =3D &cpupll_parent; + clk_init.num_parents =3D 1; + cpupll->clk_hw.init =3D &clk_init; + + ret =3D devm_clk_hw_register(dev, &cpupll->clk_hw); + if (ret) + return ret; + + return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get, &c= pupll->clk_hw); +} + +static struct platform_driver msc313_cpupll_driver =3D { + .driver =3D { + .name =3D "mstar-msc313-cpupll", + .of_match_table =3D msc313_cpupll_of_match, + }, + .probe =3D msc313_cpupll_probe, +}; +builtin_platform_driver(msc313_cpupll_driver); --=20 2.34.1 From nobody Wed Jul 1 04:14:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D602C46467 for ; Sun, 2 Jan 2022 16:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229771AbiABQ5o (ORCPT ); Sun, 2 Jan 2022 11:57:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbiABQ5j (ORCPT ); Sun, 2 Jan 2022 11:57:39 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94305C061761; Sun, 2 Jan 2022 08:57:39 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id g191-20020a1c9dc8000000b0032fbf912885so17213963wme.4; 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Sun, 02 Jan 2022 08:57:37 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id y11sm32899848wrp.86.2022.01.02.08.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:37 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/9] ARM: mstar: Add cpupll to base dtsi Date: Sun, 2 Jan 2022 17:57:24 +0100 Message-Id: <20220102165730.50190-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.d= tsi index 89ebfe4f29da..2249faaa3aa7 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -155,6 +155,13 @@ mpll: mpll@206000 { clocks =3D <&xtal>; }; =20 + cpupll: cpupll@206400 { + compatible =3D "mstar,msc313-cpupll"; + reg =3D <0x206400 0x200>; + #clock-cells =3D <0>; + clocks =3D <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells =3D <2>; reg =3D <0x207800 0x200>; --=20 2.34.1 From nobody Wed Jul 1 04:14:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBCEC4167D for ; Sun, 2 Jan 2022 16:57:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229835AbiABQ5q (ORCPT ); Sun, 2 Jan 2022 11:57:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229630AbiABQ5l (ORCPT ); Sun, 2 Jan 2022 11:57:41 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9641BC061761; Sun, 2 Jan 2022 08:57:40 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id j18so65698495wrd.2; Sun, 02 Jan 2022 08:57:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PSLPG0MzXHr2sBAsU44qorgJ49GZ8FzI0+68Kp64Drs=; b=VOQd0Ow+1WrNgYoFwglIyEDD6eh0BYvqxp/o+V8B/ljFwgxQTOEv6OJej9Mm5R+oYR hkhJn924zrQiLQcJnGGw3JAdk3VOqMJwJkpkOvmlDEjNQ9hU+kQ52Ftz1a4TKcUJNrUa 7Ozk7l+nDnMIdRpuzunuEk28K5nHqv3kP+A1i5CiKF6V6WSNN848CrI8bs1omgDwEv4V ERNaMlDYKH8a4Jrd9vug/k4Fy7od9oHsSA9alNkU50hWXcUwFZRz4/96ke0ewxaIol8+ wVJt6r+O7Yh/X2+qAXheK37OiawrgLjj3R3NxZKPGn/xstgbIaeGGFecPDFaDkmdSrm4 0cRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PSLPG0MzXHr2sBAsU44qorgJ49GZ8FzI0+68Kp64Drs=; b=uGh4pE9r3ien+f2mVwMYTXFGnywHln3hUZacA9y2TeEcKT+Fo/ZFzdeP969ae7fMt7 EHk24ywif3nMTc4hbHpWNkfrgCdzTfXhCVUnLigX68Cv2xtAosKSxx/6hpyBFZysiGVm oN3LRweDbZHh8hYbN/LssiCV30Zpkv6p8jxYEh/Xcx4fxjYCFkPEcSlRuYy9ses07kPk oj7qyLT/1qk3rNWRMDZaSdw1vfaX2TGZ9yxBBmfiPyaBn7qcuv7fx+uNNsvaC4HkFcJx UM/WYzJexsBR+1M2C0x20WA/jIFxgMQGfjLdRQ8axVJU9WQ6dKKDqokghH5gJUh1o9ph BDRw== X-Gm-Message-State: AOAM533qQFoa+CZxahr/Fwa/Hqcz3sRC4WpuPxin7s/ptqKTaB/Kq1qQ kXQtX8UyDpxv9nKS85jorpUY7Qs5VfAe5w== X-Google-Smtp-Source: ABdhPJz7QrYuQYvDwF8GFlCqsOZUggIWRhwsYrBN7X2EcIR/k/YLBCU5wE1SdWo+1XMV6CkNH71Jkg== X-Received: by 2002:a5d:6d0e:: with SMTP id e14mr37348800wrq.407.1641142658912; Sun, 02 Jan 2022 08:57:38 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id p13sm25786857wrs.54.2022.01.02.08.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:38 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/9] ARM: mstar: Link cpupll to cpu Date: Sun, 2 Jan 2022 17:57:25 +0100 Message-Id: <20220102165730.50190-5-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer The CPU clock is sourced from the CPU PLL. Link cpupll to the cpu so that frequency scaling can happen. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.d= tsi index 2249faaa3aa7..c26ba9b7b6dd 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -21,6 +21,8 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; reg =3D <0x0>; + clocks =3D <&cpupll>; + clock-names =3D "cpuclk"; }; }; =20 --=20 2.34.1 From nobody Wed Jul 1 04:14:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C19F3C433EF for ; Sun, 2 Jan 2022 16:57:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbiABQ5t (ORCPT ); Sun, 2 Jan 2022 11:57:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbiABQ5m (ORCPT ); Sun, 2 Jan 2022 11:57:42 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C426DC061761; Sun, 2 Jan 2022 08:57:41 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id bg19-20020a05600c3c9300b0034565e837b6so9572128wmb.1; Sun, 02 Jan 2022 08:57:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XBkuRgwe6wjN8B0dWdq4qTtmz/vmICR+ObQMfngMweY=; b=LQBHp/l45t4z5YWuB+Sfk5u3i5X3BIZqx5z++W8Ku9PElU7/04F4dE/eehHuLMTzSb V8XyxS7Rj0+oj3XyE87KYyBfl2ajEuI/zRAdW+TD6IwWJIyC20iFGwQWc4ZWAo+6dNY8 ChqJv17YWllfBsa1Xjn9YeDDteYs1NDz7zVlym056KI8WNnNuBJ7JziJ/03ioUKemzC1 piVuGhP6gGolCqk6Ur562fdyOw4Ok6xCkTsQKWV8mxoygFmpkbUe+GHAwknk5e+aGV3o N9h0bW11D1nKyj/1M3JKqWhYWy5lvHvm3a5YUnwHeLRxbzqquT3nNv01WxFC+H9ILpW4 njUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XBkuRgwe6wjN8B0dWdq4qTtmz/vmICR+ObQMfngMweY=; b=XRtaT+L/OW89GTMib1VQGRAV/sU/ZL33b9TYiHXI7Y3RrfTHkRE0KqG2Bo5LphYvfX gKWi6zIsX6m4SWs2FH15331RYh1pOzyzNDqS9TuKPqgjfE/oxXaPHeioRKGD2vWEqa7J cIboVEm9O+qF8DAAockzvmvplK37uGk3tUO/clWAhQyM9Qw8kEvOPRooQh3JjW78kGad 6/QRWDM3yw69BZlYx7xvOJoPWpgyisl29zayY8ZLtpmzwbAhC5JyF/rw2Fqy2DA57ktM m+Km/fESTI+0DioL6u9hd9qQvn929VgsYjL8AvSrz03VZ768DzwMVMzm1dadItaiPLxA arXw== X-Gm-Message-State: AOAM5339oHaPmnQ1luBJBG3s7xw/v+B8W1eCieiTPLSqKwbVPHgOvLrW ETx7cBEm8b4Llc9RW2cVxOaJH2atXaCooQ== X-Google-Smtp-Source: ABdhPJzVe5xaHtg300FhtGj31yzAxDEi2z1lt44/jfQJTXEGYErXbNN3jAWTUoQFGm3g/hxzve5JoQ== X-Received: by 2002:a05:600c:510f:: with SMTP id o15mr35759659wms.104.1641142660072; Sun, 02 Jan 2022 08:57:40 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id l6sm42247234wry.18.2022.01.02.08.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:39 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/9] ARM: mstar: Link cpupll to second core Date: Sun, 2 Jan 2022 17:57:26 +0100 Message-Id: <20220102165730.50190-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer The second core also sources it's clock from the CPU PLL. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/ms= tar-infinity2m.dtsi index 6d4d1d224e96..dc339cd29778 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -11,6 +11,8 @@ cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; reg =3D <0x1>; + clocks =3D <&cpupll>; + clock-names =3D "cpuclk"; }; }; =20 --=20 2.34.1 From nobody Wed Jul 1 04:14:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECDE8C433EF for ; Sun, 2 Jan 2022 16:57:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229936AbiABQ5w (ORCPT ); Sun, 2 Jan 2022 11:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229692AbiABQ5m (ORCPT ); Sun, 2 Jan 2022 11:57:42 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B2F1C061792; Sun, 2 Jan 2022 08:57:42 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id l4so20212305wmq.3; Sun, 02 Jan 2022 08:57:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MwkPi3zTHNX/WgU468/COGljzbksLucVcX9Vresnwgs=; b=JA3YqBV0dBer5Kp4K4W0e1lBP6bSyY186oVs0gUMBG/kXP0OX78v3XYHCJ8PBQo8uB cWYW3Ib/cvCCIONWmyVw2+E+GgSZcxO2vGZb/TfXDSSBwbGOMG3jyFm5lSp6vPaHVZjZ UTwdWVwx3kmBJ1Pg0LaVcHw08IXN5jizUIdEpH9boncaqtN00PdeOm6rXJ8hHBdFY3m9 gat0WYf7GEIKTchc+6r6l82+dwKBz6Cg3lIGIw+ysX/c42L78vNXfh5YfnYIVdRVtH1D uFREgLOjlIlUNtIqIAi6MVwAAPFskIl2qINRBUvLxueBlWP7msm3PeSrIq0OmAsRb+yQ 8M9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MwkPi3zTHNX/WgU468/COGljzbksLucVcX9Vresnwgs=; b=FJ++KW9TNlLlu/OF/QyAm2VsbpfWfEefrgR2gel+kLrRD6lVweZ5kjeDOrdyKtkeYZ gT5HAjfjrrUb8UJvS4oig2SC/Q3pe6DtZ5TnW1pTZq3cu7bSTOjO/2WEL/TNclab3p6C TVLJzDYQePOazbQQPIRBW7stBRDWGwKU2Xz0QPW6QUK14cufpASFJVCAGUpGhPSvruqT tUqbkKcYJgEWNioJWfFFdrWqUZj3xscc4mmgSJAElDJdfOnA9zJg14iez8DXEsYwxOp8 Tr1BhYKNSANGg/ylWeR2mhl1YmmVaAePKRi+XyRWSzn6fjrpUi4pHyu6GzTiZ4ExsfEE t6HA== X-Gm-Message-State: AOAM531eNIMn7fH1Z2LfXsPXTB7KcFZRF63rdeGoccIohDMktGwTQLxL 9k5y8FMzhgEeumXvbm2YBD8= X-Google-Smtp-Source: ABdhPJw+T+7Kva7Grqslf4Ard+f+I0ns0p4qkTopFlTEorvQ7OO+iaZQtaZdCphuRJ7GAg2DLWSmcA== X-Received: by 2002:a7b:c745:: with SMTP id w5mr36644779wmk.96.1641142661060; Sun, 02 Jan 2022 08:57:41 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id o15sm26163717wri.106.2022.01.02.08.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:40 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v2 6/9] ARM: mstar: Add OPP table for infinity Date: Sun, 2 Jan 2022 17:57:27 +0100 Message-Id: <20220102165730.50190-7-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer Add an OPP table for the inifinity chips so that cpu frequency scaling can happen. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/msta= r-infinity.dtsi index 0bee517797f4..441a917b88ba 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -8,6 +8,40 @@ =20 #include =20 +/ { + cpu0_opp_table: opp_table0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu0_opp_table>; +}; + &imi { reg =3D <0xa0000000 0x16000>; }; --=20 2.34.1 From nobody Wed Jul 1 04:14:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F596C3525C for ; Sun, 2 Jan 2022 16:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229902AbiABQ5u (ORCPT ); Sun, 2 Jan 2022 11:57:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229719AbiABQ5o (ORCPT ); Sun, 2 Jan 2022 11:57:44 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5147FC06179C; Sun, 2 Jan 2022 08:57:43 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id v7so65574323wrv.12; Sun, 02 Jan 2022 08:57:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=21h9f/ui8ZIqSSrHzJ4KrN8YACvdlcc8m+OIu8z6NvM=; b=ElGGNSCD9QRK7+dw5nfGGhnn8BxEqs9+Jm/XI0ZtwxDwdeI7y6hp/nKKzi8OmmkTfd DfesxdRQQk9RqiyI/gy8nV7M1JGKw5EXwm1V8ZsxS4++cNwA9Y9cvcGFKl3yJ4TYDFJR PdQo3mBGXpTYUy6CjffI3IEKAMAs0z/QXgFssHDMe0orAfv10vB6jROWsQZ3td7PZ/Cd L9axkJZxSYMmyaxtnUMJ6UL9CFqC7S8Zsv4AXyzVbkF6LBpcxF/KA/W4R0WmoM6CWEYp Rd2Zt7f2YKdTAI+W8rAJkk5EKgtHHmQ2E9c8rt/nJgcbaTcrXFkVN5W0pZaqji6gTMJD E99w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=21h9f/ui8ZIqSSrHzJ4KrN8YACvdlcc8m+OIu8z6NvM=; b=FvjYyLLaNvp5KpnOLK6DHPUnpThtJM1sHELA54l/dh6ebyjmgF1N/QmxwsV8m1czzW gA3lDYy+XR9gg4yEguPXhsr7mp7krp1SX3EdB8RmyLDntAX7Z3CDdqQDNM0rQPNRqnLB 5mD9tOkHDVgH5q98vCmzxTmmn9Z/jvF+vh4+8y6ge+pbkMEEpMWy8388pmigWcHElGQ/ gHq5r+2SwCovzjogWtj5Yp+Bd0MCV6/9pA6DZwX07tmKMfY5SWikDj0fNqIof4HL55vP NTabJQCRAaE32DjYsDYRZX0swVc4/riVyORihZkpyFDMLqJHatggH+5MOImfUd+4no7V w98w== X-Gm-Message-State: AOAM530wbLwRVmT0hl6wX0EeVJIReNFgRWF1mwL1ouk7Ik4LR2YohyD5 k1XaYJ5QpsMWd++O03JAQdE= X-Google-Smtp-Source: ABdhPJwJOhTLzvSn3l0lO6PPzb+/Xo7IVWWa+kzDE8rxBggDHlIZdM774Ruhx9LE0tOuEbvyX2a6LA== X-Received: by 2002:a5d:440e:: with SMTP id z14mr14054757wrq.611.1641142661995; Sun, 02 Jan 2022 08:57:41 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id y1sm32261901wrm.3.2022.01.02.08.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:41 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v2 7/9] ARM: mstar: Add OPP table for infinity3 Date: Sun, 2 Jan 2022 17:57:28 +0100 Message-Id: <20220102165730.50190-8-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer The infinity3 has a slightly higher max frequency compared to the infinity so extend the OPP table. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity3.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mst= ar-infinity3.dtsi index 9857e2a9934d..a56cf29e5d82 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -6,6 +6,64 @@ =20 #include "mstar-infinity.dtsi" =20 +&cpu0_opp_table { + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; + + // overclock frequencies below, shown to work fine up to 1.3 GHz + opp-108000000 { + opp-hz =3D /bits/ 64 <1080000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; + + opp-1188000000 { + opp-hz =3D /bits/ 64 <1188000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; + + opp-1296000000 { + opp-hz =3D /bits/ 64 <1296000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; + + opp-1350000000 { + opp-hz =3D /bits/ 64 <1350000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; + + opp-1404000000 { + opp-hz =3D /bits/ 64 <1404000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; + + opp-1458000000 { + opp-hz =3D /bits/ 64 <1458000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; + + opp-1512000000 { + opp-hz =3D /bits/ 64 <1512000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + turbo-mode; + }; +}; + &imi { reg =3D <0xa0000000 0x20000>; }; --=20 2.34.1 From nobody Wed Jul 1 04:14:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D45B0C433F5 for ; Sun, 2 Jan 2022 16:57:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229735AbiABQ54 (ORCPT ); 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Sun, 02 Jan 2022 08:57:42 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/9] ARM: mstar: Add OPP table for mercury5 Date: Sun, 2 Jan 2022 17:57:29 +0100 Message-Id: <20220102165730.50190-9-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer Add an OPP table for mercury5 so that cpu frequency scaling can happen. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/msta= r-mercury5.dtsi index a7d0dd9d6132..80a19bd23c9c 100644 --- a/arch/arm/boot/dts/mstar-mercury5.dtsi +++ b/arch/arm/boot/dts/mstar-mercury5.dtsi @@ -6,6 +6,42 @@ =20 #include "mstar-v7.dtsi" =20 +/ { + cpu0_opp_table: opp_table0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-microvolt =3D <800000 800000 850000>; + clock-latency-ns =3D <300000>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-microvolt =3D <850000 850000 880000>; + clock-latency-ns =3D <300000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <880000 880000 890000>; + clock-latency-ns =3D <300000>; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <900000 900000 1000000>; + clock-latency-ns =3D <300000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <900000 900000 1000000>; + clock-latency-ns =3D <300000>; + }; + }; +}; + &imi { reg =3D <0xa0000000 0x20000>; }; --=20 2.34.1 From nobody Wed Jul 1 04:14:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B67CC433F5 for ; Sun, 2 Jan 2022 16:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229918AbiABQ6A (ORCPT ); Sun, 2 Jan 2022 11:58:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbiABQ5q (ORCPT ); Sun, 2 Jan 2022 11:57:46 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B09E5C061761; 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Sun, 02 Jan 2022 08:57:43 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id bk17sm2095664wrb.105.2022.01.02.08.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 08:57:43 -0800 (PST) From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Arnd Bergmann , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 9/9] ARM: mstar: Extend opp_table for infinity2m Date: Sun, 2 Jan 2022 17:57:30 +0100 Message-Id: <20220102165730.50190-10-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220102165730.50190-1-romain.perier@gmail.com> References: <20220102165730.50190-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" infinity2m are running up to 1.2Ghz, this extends opp_table with the corresponding frequencies and enable operating-points table for cpu1 Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/ms= tar-infinity2m.dtsi index dc339cd29778..1b485efd7156 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -6,10 +6,25 @@ =20 #include "mstar-infinity.dtsi" =20 +&cpu0_opp_table { + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <300000>; + }; +}; + &cpus { cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; + operating-points-v2 =3D <&cpu0_opp_table>; reg =3D <0x1>; clocks =3D <&cpupll>; clock-names =3D "cpuclk"; --=20 2.34.1