From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE7B1C433F5 for ; Thu, 23 Dec 2021 01:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345575AbhLWBLR (ORCPT ); Wed, 22 Dec 2021 20:11:17 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57468 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241087AbhLWBLP (ORCPT ); Wed, 22 Dec 2021 20:11:15 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id C6E4ACE1EFD; Thu, 23 Dec 2021 01:11:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CF62C36AEB; Thu, 23 Dec 2021 01:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221871; bh=hG00kWbWXHmSwWgo7vfy0tK/cDWcyfPAdzTXQsCGsWs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C+Vhgkel6nBIgd3Ta4wvAsw2WlgcLdYXD3cSEXHxLLiDWWxoGyEGmpqbeJgJzeDoo gJQ/BAkHieRO0ishtxWcvqeCqG6bU4kpHO08y0QHVPPlpOBttVn5uHJyW/dloPsx4t eIMi1BoWPoV9eRar3/BZlTxj6LZ6SoCukCKk/04UlRhdWw83SgCf/1p/yHSygSr6lZ tLwwCL7N5mg4s4bq6gLvPbNXEyAHWJb/3EfQdVS9wnr+IKOKh2DeO19GNDvoM2c3at joUqfXPw8GSvk7m892YHzlBvz2wbie6+VW6d2XipZjZtjNSxOfRIxilRuPivUduA5z qLjKBCPlhzk0Q== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Joyce Ooi Subject: [PATCH v2 01/23] PCI: altera: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:32 -0600 Message-Id: <20211223011054.1227810-2-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The altera driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Joyce Ooi --- drivers/pci/controller/pcie-altera.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/= pcie-altera.c index 2513e9363236..98ada2e20e02 100644 --- a/drivers/pci/controller/pcie-altera.c +++ b/drivers/pci/controller/pcie-altera.c @@ -767,7 +767,7 @@ static int altera_pcie_probe(struct platform_device *pd= ev) struct altera_pcie *pcie; struct pci_host_bridge *bridge; int ret; - const struct of_device_id *match; + const struct altera_pcie_data *data; =20 bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!bridge) @@ -777,11 +777,11 @@ static int altera_pcie_probe(struct platform_device *= pdev) pcie->pdev =3D pdev; platform_set_drvdata(pdev, pcie); =20 - match =3D of_match_device(altera_pcie_of_match, &pdev->dev); - if (!match) + data =3D of_device_get_match_data(&pdev->dev); + if (!data) return -ENODEV; =20 - pcie->pcie_data =3D match->data; + pcie->pcie_data =3D data; =20 ret =3D altera_pcie_parse_dt(pcie); if (ret) { --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0990C433F5 for ; Thu, 23 Dec 2021 01:11:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345532AbhLWBLQ (ORCPT ); Wed, 22 Dec 2021 20:11:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241236AbhLWBLO (ORCPT ); Wed, 22 Dec 2021 20:11:14 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4AC2C06173F; Wed, 22 Dec 2021 17:11:14 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3F49B61D92; Thu, 23 Dec 2021 01:11:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 619B6C36AE5; Thu, 23 Dec 2021 01:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221873; bh=yGisiihGA/0OfiY28lJ4w5wj7xm0xhnIxa3qRAa2Or0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nh7C33QdMOtYnnjcLl+Y2Lp4VQGd0KokjCLyM241tdCQV9G7v2jYT7viPYs82LtE4 5bUHLojVXLleeOG9QadcLshFK3EPoMa3/mVb2olLZxD+eMo/3izvtRQXfs9R9lI9Eb LX7bEEkmjFHm6TmJWXqyQgeIqa8KxmFd2S/bfCrkBdPLL5wSEXXYzLf3jnfWx9waV1 JLupjK4rhNymbkWWUZVQjkdie3e2bdApEfBJJI7VXZapqZjZlkCB1gnyZqgc9Ewbm+ OA+zwZw/TjPE/6p3TutKLCP039AZMub9wBt8W3WqNqQsAOhaFLqIH1tMEx1Rdqgmjx T/pHQw66mV1Vg== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Jesper Nilsson , linux-arm-kernel@axis.com Subject: [PATCH v2 02/23] PCI: artpec6: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:33 -0600 Message-Id: <20211223011054.1227810-3-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The artpec6 driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Jesper Nilsson Cc: linux-arm-kernel@axis.com Acked-by: Jesper Nilsson --- drivers/pci/controller/dwc/pcie-artpec6.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/contro= ller/dwc/pcie-artpec6.c index c91fc1954432..2f15441770e1 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -380,17 +380,15 @@ static int artpec6_pcie_probe(struct platform_device = *pdev) struct dw_pcie *pci; struct artpec6_pcie *artpec6_pcie; int ret; - const struct of_device_id *match; const struct artpec_pcie_of_data *data; enum artpec_pcie_variants variant; enum dw_pcie_device_mode mode; u32 val; =20 - match =3D of_match_device(artpec6_pcie_of_match, dev); - if (!match) + data =3D of_device_get_match_data(dev); + if (!data) return -EINVAL; =20 - data =3D (struct artpec_pcie_of_data *)match->data; variant =3D (enum artpec_pcie_variants)data->variant; mode =3D (enum dw_pcie_device_mode)data->mode; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BF6BC433EF for ; Thu, 23 Dec 2021 01:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345623AbhLWBLS (ORCPT ); Wed, 22 Dec 2021 20:11:18 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:49372 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345529AbhLWBLQ (ORCPT ); Wed, 22 Dec 2021 20:11:16 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DFBEF61C2C; Thu, 23 Dec 2021 01:11:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28D20C36AE5; Thu, 23 Dec 2021 01:11:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221875; bh=Ibnjc1Ag3vn7A29RC/T0gZzNpyuQKYqn+Ff07SRVx4Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZcfHxOmKbAHh1dur48h2G343diWQd0rLaQKK+YfADYBNoQA2tvOZSKISdBUNvGyH/ mgi+Yeq0GCAzdt8cqaZ26PJ0n/PjZnT2loDxzVws1dNNYCwaKjwudaxLmCLcqyLUtF ElJt7+6TAtmb+U6U1/m46/m0UiO/prtTQQxh0iPXWY5vXpPMKp2alyxdFBzansjmyX JB1QSS9u938+RS3a0OICI4q2lm2T6XjKGWpuvw2SwH8PhUO3N+juflm85M/JS/O9cP OBhwax0V+HAv4vnKjtKWyK3wsAOMtaLYI4uMBZYwyGQJMZHaR46bXJcHkERc006RCq thqnbKcuXwSxA== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Tom Joseph Subject: [PATCH v2 03/23] PCI: cadence: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:34 -0600 Message-Id: <20211223011054.1227810-4-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The cadence driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Tom Joseph --- drivers/pci/controller/cadence/pcie-cadence-plat.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index a224afadbcc0..bac0541317c1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -45,7 +45,6 @@ static int cdns_plat_pcie_probe(struct platform_device *p= dev) { const struct cdns_plat_pcie_of_data *data; struct cdns_plat_pcie *cdns_plat_pcie; - const struct of_device_id *match; struct device *dev =3D &pdev->dev; struct pci_host_bridge *bridge; struct cdns_pcie_ep *ep; @@ -54,11 +53,10 @@ static int cdns_plat_pcie_probe(struct platform_device = *pdev) bool is_rc; int ret; =20 - match =3D of_match_device(cdns_plat_pcie_of_match, dev); - if (!match) + data =3D of_device_get_match_data(dev); + if (!data) return -EINVAL; =20 - data =3D (struct cdns_plat_pcie_of_data *)match->data; is_rc =3D data->is_rc; =20 pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8BD0C433EF for ; Thu, 23 Dec 2021 01:11:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345649AbhLWBLX (ORCPT ); Wed, 22 Dec 2021 20:11:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345594AbhLWBLS (ORCPT ); Wed, 22 Dec 2021 20:11:18 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1473DC061574; Wed, 22 Dec 2021 17:11:18 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AB60561D47; Thu, 23 Dec 2021 01:11:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB616C36AE5; Thu, 23 Dec 2021 01:11:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221877; bh=iOkvvyDco++xwaeJXqOOlWMRlL/DkfMGvNa4DoNqUTQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q7E39IHl8weHJkVn1UAIb9+guzhHDgYPnNQzt9wSq/FHdc/97cDonVlM2/hQ/lIUH gAdKyWS8xDCLCKNsVflsNlRTbNUkJwrRe7zSgyjDGEm+P2S9D6ehwc/QBtNEnIy7q1 uMXH6dwvg4J7DacnAsgZosBP+kdDCocgwkWQlLSjgYRl6xtqVLqHC1B8jAY6K9/38L B2ShZqx9M15IxpoVcW6YmIyjsyL3wBJJDhud0sNBn+dSmadnnPcZTiUIu8+pMJ/QI8 kGJQ/ukDXaVFKNKQVRNgF9nKWlQmnS0GoqVfUJbFj65IE+khgHt13OEmVD001RWEAV b+DjnCLYnFlGQ== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel Subject: [PATCH v2 04/23] PCI: designware-plat: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:35 -0600 Message-Id: <20211223011054.1227810-5-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The designware-plat driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Jingoo Han Cc: Gustavo Pimentel --- drivers/pci/controller/dwc/pcie-designware-plat.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pc= i/controller/dwc/pcie-designware-plat.c index 8851eb161a0e..0c5de87d3cc6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -122,15 +122,13 @@ static int dw_plat_pcie_probe(struct platform_device = *pdev) struct dw_plat_pcie *dw_plat_pcie; struct dw_pcie *pci; int ret; - const struct of_device_id *match; const struct dw_plat_pcie_of_data *data; enum dw_pcie_device_mode mode; =20 - match =3D of_match_device(dw_plat_pcie_of_match, dev); - if (!match) + data =3D of_device_get_match_data(dev); + if (!data) return -EINVAL; =20 - data =3D (struct dw_plat_pcie_of_data *)match->data; mode =3D (enum dw_pcie_device_mode)data->mode; =20 dw_plat_pcie =3D devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FD7DC433EF for ; Thu, 23 Dec 2021 01:11:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345662AbhLWBL0 (ORCPT ); Wed, 22 Dec 2021 20:11:26 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:49458 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345633AbhLWBLT (ORCPT ); Wed, 22 Dec 2021 20:11:19 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7953C61D98; Thu, 23 Dec 2021 01:11:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99289C36AEA; Thu, 23 Dec 2021 01:11:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221878; bh=Vi54mz/4hxthWCKu01W9eiBvXWzlLPEqbkFMBL2+LVo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s8pS7WSXaJ0we2kX41QnNq/kpLw+seDJ3eV4B93lirSpLX5GpXn+Bbo0C3ZCOk4/8 5gFIVA7fGAsUgrZr0Z464BSzLnRCdORcsIpJALlPPF4356Jp6SlngEywHUK7lZEG10 DwfSW3skPCtAOHQzhq4aElCd92JQB3W5MzTmURuw2EHN+qU/2FGo0pelCtU/J9uDsZ x7qNWAPz+NqXfGuzYP7+zIGvItWvY0KwWKDENdmCdpHy9dpv8jyG4+mqvfmuQF0Ebn CDbbEVXrNmOqeoRbmP4iFSS0Y9zTTX+ue28n2wZ0y3QAduCZSheod9nnfoFgOLBP9w ZNOiV0Z2Emd+Q== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Kishon Vijay Abraham I , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/23] PCI: dra7xx: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:36 -0600 Message-Id: <20211223011054.1227810-6-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The dra7xx driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Kishon Vijay Abraham I Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/dwc/pci-dra7xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controll= er/dwc/pci-dra7xx.c index a4221f6f3629..12d19183e746 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -697,16 +697,14 @@ static int dra7xx_pcie_probe(struct platform_device *= pdev) struct device_node *np =3D dev->of_node; char name[10]; struct gpio_desc *reset; - const struct of_device_id *match; const struct dra7xx_pcie_of_data *data; enum dw_pcie_device_mode mode; u32 b1co_mode_sel_mask; =20 - match =3D of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); - if (!match) + data =3D of_device_get_match_data(dev); + if (!data) return -EINVAL; =20 - data =3D (struct dra7xx_pcie_of_data *)match->data; mode =3D (enum dw_pcie_device_mode)data->mode; b1co_mode_sel_mask =3D data->b1co_mode_sel_mask; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED314C43219 for ; Thu, 23 Dec 2021 01:11:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345651AbhLWBL2 (ORCPT ); Wed, 22 Dec 2021 20:11:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345652AbhLWBLY (ORCPT ); Wed, 22 Dec 2021 20:11:24 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA7DFC061746; Wed, 22 Dec 2021 17:11:23 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 4D0ADCE1EFD; Thu, 23 Dec 2021 01:11:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5862DC36AE5; Thu, 23 Dec 2021 01:11:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221880; bh=8ozT1NnqkwytB+gwY3dvSdAg57IGoiJh+NMjyrG5TXA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oyPoF7LNrBKwHu9Z0WIPQfpnPnPTcI66gGGVzgbjwpxYfd0RkuyNatl41Daem9rpI ymAh+c463R5vh8aIIUOIiUfxWwJ8Vufz5rCxY0DDa10PD3kBIWe5iO/De+TLCJQZkt 6KdZ+bRch8nw3vbJnPSG5n035962dXAXrf4HaNjn0YppPYX0M954ccHf4t+D9U1kMQ SM4Q2FLSCCxyVZ2xNUY9Axo9xfqt6EexjKOqx16uzP6QXSLCtBRPV7/tEorfJsSqly CAFQdiyDwUm/jFjNXi9c8zU4AwkQBFFuz/d+Nn4VWoAGz3ToITWpZDNob2DnylZ6b2 ZLQyuSOstvh9g== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Kishon Vijay Abraham I Subject: [PATCH v2 06/23] PCI: keystone: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:37 -0600 Message-Id: <20211223011054.1227810-7-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The keystone driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/contro= ller/dwc/pci-keystone.c index 865258d8c53c..bf4755cb6c50 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1087,7 +1087,6 @@ static int __init ks_pcie_probe(struct platform_devic= e *pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; const struct ks_pcie_of_data *data; - const struct of_device_id *match; enum dw_pcie_device_mode mode; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; @@ -1104,8 +1103,7 @@ static int __init ks_pcie_probe(struct platform_devic= e *pdev) int irq; int i; =20 - match =3D of_match_device(of_match_ptr(ks_pcie_of_match), dev); - data =3D (struct ks_pcie_of_data *)match->data; + data =3D of_device_get_match_data(dev); if (!data) return -EINVAL; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A874EC433FE for ; Thu, 23 Dec 2021 01:11:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345677AbhLWBLa (ORCPT ); Wed, 22 Dec 2021 20:11:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345594AbhLWBLY (ORCPT ); Wed, 22 Dec 2021 20:11:24 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 993A5C061401; Wed, 22 Dec 2021 17:11:23 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 35FF961C04; Thu, 23 Dec 2021 01:11:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4AF44C36AEE; Thu, 23 Dec 2021 01:11:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221882; bh=QDle4GEHP+VzIlHo0RChYIQ/WFmjI4YP/x4ESfOQkZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QpIe8nj+BHPIEcjhMuUSuo6A8TsW92oTiKFaqdg/AzCCbockFTElcFQfG6Sb2eMYk 4cqyiM+rMqFQ9JsAYIA240RQlVCq+vX1dTp/llDt7FNVubDTaJQi5En7KSqSiMIXng 7A8xA4Gn2u2U2GwO5vCRjs1JURLMteFoLhTzjkRUsEenFp2o7RK2+78CA3Rgx8IJHE JAD0+9GToxQbWszsRZvbbjPW836ltgwMzcnP1LCFdYSozJZbn7svtJt4eKH5VcaB/I 7hrdmU9yY0nRTYfBGGReyyaI+42+rjVJJKoPqkAg7gdUZegD4NVQR2xk6EQIATxcYy cFt0qrk/fsTEw== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Xiaowei Song , Binghui Wang Subject: [PATCH v2 07/23] PCI: kirin: Prefer of_device_get_match_data() Date: Wed, 22 Dec 2021 19:10:38 -0600 Message-Id: <20211223011054.1227810-8-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei The kirin driver only needs the device data, not the whole struct of_device_id. Use of_device_get_match_data() instead of of_match_device(). No functional change intended. [bhelgaas: commit log] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Xiaowei Song Cc: Binghui Wang --- drivers/pci/controller/dwc/pcie-kirin.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controll= er/dwc/pcie-kirin.c index 095afbccf9c1..8d6e241bd171 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -773,7 +773,6 @@ static const struct of_device_id kirin_pcie_match[] =3D= { static int kirin_pcie_probe(struct platform_device *pdev) { enum pcie_kirin_phy_type phy_type; - const struct of_device_id *of_id; struct device *dev =3D &pdev->dev; struct kirin_pcie *kirin_pcie; struct dw_pcie *pci; @@ -784,13 +783,12 @@ static int kirin_pcie_probe(struct platform_device *p= dev) return -EINVAL; } =20 - of_id =3D of_match_device(kirin_pcie_match, dev); - if (!of_id) { + phy_type =3D (long)of_device_get_match_data(dev); + if (!phy_type) { dev_err(dev, "OF data missing\n"); return -EINVAL; } =20 - phy_type =3D (long)of_id->data; =20 kirin_pcie =3D devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); if (!kirin_pcie) --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B250AC433EF for ; Thu, 23 Dec 2021 01:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345684AbhLWBLe (ORCPT ); Wed, 22 Dec 2021 20:11:34 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:49548 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345634AbhLWBLZ (ORCPT ); Wed, 22 Dec 2021 20:11:25 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 403BB61C1E; Thu, 23 Dec 2021 01:11:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 713A5C36AE5; Thu, 23 Dec 2021 01:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221884; bh=WOUkdh1NbhxbQ1Gq4rElA7a5wF5ya9shQ6vgwd/J/8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XcYlS6fRfQS5o3OiQzeKUPl9PX6YTj2xTyv9ColCT1RtYUuHzUKFtXz6deCitMebs ujbGSOpKfSzSVneNicgpv2ntPkZycMsm160HY1uY4aNM8POK6nYtHEXA0UD00BVw+K lirrCj5b/2h0WqSUS01XHiO6pKGWvRc9n+BZ5p+F3lVjn2D+TYhUeTG6n326zd6gtI Mmu5U9oWU4y1CiZXRB/d4fyCPIr/Ij6WSMxYZKsO/TjnVOQrqYthIlpF0JbvJe2rYj 8q68Be8X2r86adz+5jA3TtNouIAfdgu20nxQZM+vBRWh5NEtIE5JIOFn1r7cj/dxc6 kquiE7eh9B8Vw== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Kishon Vijay Abraham I , Tom Joseph , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/23] PCI: j721e: Drop pointless of_device_get_match_data() cast Date: Wed, 22 Dec 2021 19:10:39 -0600 Message-Id: <20211223011054.1227810-9-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas of_device_get_match_data() returns "void *", so no cast is needed when assigning the result to a pointer type. Drop the unnecessary cast. Signed-off-by: Bjorn Helgaas Cc: Kishon Vijay Abraham I Cc: Tom Joseph Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/cadence/pci-j721e.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index 918e11082e6a..cd43d1898482 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -354,7 +354,7 @@ static int j721e_pcie_probe(struct platform_device *pde= v) struct device *dev =3D &pdev->dev; struct device_node *node =3D dev->of_node; struct pci_host_bridge *bridge; - struct j721e_pcie_data *data; + const struct j721e_pcie_data *data; struct cdns_pcie *cdns_pcie; struct j721e_pcie *pcie; struct cdns_pcie_rc *rc; @@ -367,7 +367,7 @@ static int j721e_pcie_probe(struct platform_device *pde= v) int ret; int irq; =20 - data =3D (struct j721e_pcie_data *)of_device_get_match_data(dev); + data =3D of_device_get_match_data(dev); if (!data) return -EINVAL; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DDA8C4332F for ; Thu, 23 Dec 2021 01:11:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345724AbhLWBLi (ORCPT ); Wed, 22 Dec 2021 20:11:38 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57674 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345653AbhLWBL3 (ORCPT ); Wed, 22 Dec 2021 20:11:29 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 2D867CE1F05; Thu, 23 Dec 2021 01:11:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E3E5C36AE5; Thu, 23 Dec 2021 01:11:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221886; bh=eL22WxVnfWizuXg7JF9XO7PuirwfJH3BG09wKmU3gYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a6qmGpQ4Z1R+PC0Nzb8OWW8lQu0oF3N4cwXUFNu7vSaIhDnM9fn1gP8qjuhc+D2t/ yQ9S/d/ARscwNN0t3flXrGyZkiPVwLgeD4WySM4ATxlynnMu/Vr1uP1UA8RPdCavhq JmehnTuzMWUdsVMOL9W7cgt2QN+O5SUX6DKB+gD9XRiMiPNRc+H5g4AR4gI0EZNd/A am3gghZL2ewa8t18U0MfNNyBjxEPI911dUFapSpb6aV3mrkECqVOsuxP5nw26pX2zI MmjMbKG41wu9nEz3C8IuBAwHGojkd9uC6h540FZ7l+pnEAiG2EYuWrgJhVf+VtSxbB VAg2rSU6WkJ+g== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Kishon Vijay Abraham I , Tom Joseph , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/23] PCI: j721e: Drop redundant struct device * Date: Wed, 22 Dec 2021 19:10:40 -0600 Message-Id: <20211223011054.1227810-10-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas The struct cdns_pcie already contains the struct device for the j721e PCIe controller. There's no need to store another copy in struct j721e_pcie. Remove the redundant copy from struct j721e_pcie. Signed-off-by: Bjorn Helgaas Cc: Kishon Vijay Abraham I Cc: Tom Joseph Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/cadence/pci-j721e.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index cd43d1898482..489586a4cdc7 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -51,11 +51,10 @@ enum link_status { #define MAX_LANES 2 =20 struct j721e_pcie { - struct device *dev; + struct cdns_pcie *cdns_pcie; struct clk *refclk; u32 mode; u32 num_lanes; - struct cdns_pcie *cdns_pcie; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -99,7 +98,7 @@ static inline void j721e_pcie_intd_writel(struct j721e_pc= ie *pcie, u32 offset, static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) { struct j721e_pcie *pcie =3D priv; - struct device *dev =3D pcie->dev; + struct device *dev =3D pcie->cdns_pcie->dev; u32 reg; =20 reg =3D j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); @@ -165,7 +164,7 @@ static const struct cdns_pcie_ops j721e_pcie_ops =3D { static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *sys= con, unsigned int offset) { - struct device *dev =3D pcie->dev; + struct device *dev =3D pcie->cdns_pcie->dev; u32 mask =3D J721E_MODE_RC; u32 mode =3D pcie->mode; u32 val =3D 0; @@ -184,7 +183,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie,= struct regmap *syscon, static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, struct regmap *syscon, unsigned int offset) { - struct device *dev =3D pcie->dev; + struct device *dev =3D pcie->cdns_pcie->dev; struct device_node *np =3D dev->of_node; int link_speed; u32 val =3D 0; @@ -205,7 +204,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie = *pcie, static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, struct regmap *syscon, unsigned int offset) { - struct device *dev =3D pcie->dev; + struct device *dev =3D pcie->cdns_pcie->dev; u32 lanes =3D pcie->num_lanes; u32 val =3D 0; int ret; @@ -220,7 +219,7 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie = *pcie, =20 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) { - struct device *dev =3D pcie->dev; + struct device *dev =3D pcie->cdns_pcie->dev; struct device_node *node =3D dev->of_node; struct of_phandle_args args; unsigned int offset =3D 0; @@ -377,7 +376,6 @@ static int j721e_pcie_probe(struct platform_device *pde= v) if (!pcie) return -ENOMEM; =20 - pcie->dev =3D dev; pcie->mode =3D mode; pcie->linkdown_irq_regfield =3D data->linkdown_irq_regfield; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97C07C433F5 for ; Thu, 23 Dec 2021 01:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345712AbhLWBLg (ORCPT ); Wed, 22 Dec 2021 20:11:36 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:49628 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345604AbhLWBL3 (ORCPT ); Wed, 22 Dec 2021 20:11:29 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D56B061CF6; Thu, 23 Dec 2021 01:11:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F28B4C36AEE; Thu, 23 Dec 2021 01:11:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221888; bh=wsJZohoQmVTjknhdDfkUOxLkrpbTxrO5J7P5PvzrxB0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hl/3y332u9lBecG8kcbt2lsRwF0d1Ud164kjW18qs81yGdRarExEe91HtLCisM1QJ ruBfOV7ji3exkYooQ0B+s5OZsM42F85p6PAcu2CR9ywicyYht0CBFrpKLszkCc+2Rx 5bjL4LWpD+CiYfii/Dh6LCl3YwMXqHTA7kMNSUgr1zi8UuwE6k/xeEb7rysCFjGJdm Mm6hiQGFSEDtOK7rgazJ7F0mctdELseHR5Drwi3rTEwWVM6E7T99WQ6jq6qt5rrDSk oHUsJbKcgZnIOVwgVpV9XS5bfmZ6M2VvLoUF8TVBkxE7X3SWylemBp78WtPp3t1IZD C8bMSNwWOiYrA== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Rahul Tanwar Subject: [PATCH v2 10/23] PCI: intel-gw: Rename intel_pcie_port to intel_pcie Date: Wed, 22 Dec 2021 19:10:41 -0600 Message-Id: <20211223011054.1227810-11-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei Rename struct intel_pcie_port to intel_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Rahul Tanwar --- drivers/pci/controller/dwc/pcie-intel-gw.c | 204 ++++++++++----------- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index d15cf35fa7f2..5ba144924ff8 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -62,7 +62,7 @@ struct intel_pcie_soc { unsigned int pcie_ver; }; =20 -struct intel_pcie_port { +struct intel_pcie { struct dw_pcie pci; void __iomem *app_base; struct gpio_desc *reset_gpio; @@ -83,53 +83,53 @@ static void pcie_update_bits(void __iomem *base, u32 of= s, u32 mask, u32 val) writel(val, base + ofs); } =20 -static inline void pcie_app_wr(struct intel_pcie_port *lpp, u32 ofs, u32 v= al) +static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) { - writel(val, lpp->app_base + ofs); + writel(val, pcie->app_base + ofs); } =20 -static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs, +static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, u32 mask, u32 val) { - pcie_update_bits(lpp->app_base, ofs, mask, val); + pcie_update_bits(pcie->app_base, ofs, mask, val); } =20 -static inline u32 pcie_rc_cfg_rd(struct intel_pcie_port *lpp, u32 ofs) +static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) { - return dw_pcie_readl_dbi(&lpp->pci, ofs); + return dw_pcie_readl_dbi(&pcie->pci, ofs); } =20 -static inline void pcie_rc_cfg_wr(struct intel_pcie_port *lpp, u32 ofs, u3= 2 val) +static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 va= l) { - dw_pcie_writel_dbi(&lpp->pci, ofs, val); + dw_pcie_writel_dbi(&pcie->pci, ofs, val); } =20 -static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp, u32 ofs, +static void pcie_rc_cfg_wr_mask(struct intel_pcie *pcie, u32 ofs, u32 mask, u32 val) { - pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); + pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val); } =20 -static void intel_pcie_ltssm_enable(struct intel_pcie_port *lpp) +static void intel_pcie_ltssm_enable(struct intel_pcie *pcie) { - pcie_app_wr_mask(lpp, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE, + pcie_app_wr_mask(pcie, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE, PCIE_APP_CCR_LTSSM_ENABLE); } =20 -static void intel_pcie_ltssm_disable(struct intel_pcie_port *lpp) +static void intel_pcie_ltssm_disable(struct intel_pcie *pcie) { - pcie_app_wr_mask(lpp, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE, 0); + pcie_app_wr_mask(pcie, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE, 0); } =20 -static void intel_pcie_link_setup(struct intel_pcie_port *lpp) +static void intel_pcie_link_setup(struct intel_pcie *pcie) { u32 val; - u8 offset =3D dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); =20 - val =3D pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCTL); + val =3D pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL); =20 val &=3D ~(PCI_EXP_LNKCTL_LD | PCI_EXP_LNKCTL_ASPMC); - pcie_rc_cfg_wr(lpp, offset + PCI_EXP_LNKCTL, val); + pcie_rc_cfg_wr(pcie, offset + PCI_EXP_LNKCTL, val); } =20 static void intel_pcie_init_n_fts(struct dw_pcie *pci) @@ -148,14 +148,14 @@ static void intel_pcie_init_n_fts(struct dw_pcie *pci) pci->n_fts[0] =3D PORT_AFR_N_FTS_GEN12_DFT; } =20 -static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp) +static int intel_pcie_ep_rst_init(struct intel_pcie *pcie) { - struct device *dev =3D lpp->pci.dev; + struct device *dev =3D pcie->pci.dev; int ret; =20 - lpp->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(lpp->reset_gpio)) { - ret =3D PTR_ERR(lpp->reset_gpio); + pcie->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(pcie->reset_gpio)) { + ret =3D PTR_ERR(pcie->reset_gpio); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret); return ret; @@ -167,19 +167,19 @@ static int intel_pcie_ep_rst_init(struct intel_pcie_p= ort *lpp) return 0; } =20 -static void intel_pcie_core_rst_assert(struct intel_pcie_port *lpp) +static void intel_pcie_core_rst_assert(struct intel_pcie *pcie) { - reset_control_assert(lpp->core_rst); + reset_control_assert(pcie->core_rst); } =20 -static void intel_pcie_core_rst_deassert(struct intel_pcie_port *lpp) +static void intel_pcie_core_rst_deassert(struct intel_pcie *pcie) { /* * One micro-second delay to make sure the reset pulse * wide enough so that core reset is clean. */ udelay(1); - reset_control_deassert(lpp->core_rst); + reset_control_deassert(pcie->core_rst); =20 /* * Some SoC core reset also reset PHY, more delay needed @@ -188,58 +188,58 @@ static void intel_pcie_core_rst_deassert(struct intel= _pcie_port *lpp) usleep_range(1000, 2000); } =20 -static void intel_pcie_device_rst_assert(struct intel_pcie_port *lpp) +static void intel_pcie_device_rst_assert(struct intel_pcie *pcie) { - gpiod_set_value_cansleep(lpp->reset_gpio, 1); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); } =20 -static void intel_pcie_device_rst_deassert(struct intel_pcie_port *lpp) +static void intel_pcie_device_rst_deassert(struct intel_pcie *pcie) { - msleep(lpp->rst_intrvl); - gpiod_set_value_cansleep(lpp->reset_gpio, 0); + msleep(pcie->rst_intrvl); + gpiod_set_value_cansleep(pcie->reset_gpio, 0); } =20 -static void intel_pcie_core_irq_disable(struct intel_pcie_port *lpp) +static void intel_pcie_core_irq_disable(struct intel_pcie *pcie) { - pcie_app_wr(lpp, PCIE_APP_IRNEN, 0); - pcie_app_wr(lpp, PCIE_APP_IRNCR, PCIE_APP_IRN_INT); + pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); + pcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT); } =20 static int intel_pcie_get_resources(struct platform_device *pdev) { - struct intel_pcie_port *lpp =3D platform_get_drvdata(pdev); - struct dw_pcie *pci =3D &lpp->pci; + struct intel_pcie *pcie =3D platform_get_drvdata(pdev); + struct dw_pcie *pci =3D &pcie->pci; struct device *dev =3D pci->dev; int ret; =20 - lpp->core_clk =3D devm_clk_get(dev, NULL); - if (IS_ERR(lpp->core_clk)) { - ret =3D PTR_ERR(lpp->core_clk); + pcie->core_clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(pcie->core_clk)) { + ret =3D PTR_ERR(pcie->core_clk); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "Failed to get clks: %d\n", ret); return ret; } =20 - lpp->core_rst =3D devm_reset_control_get(dev, NULL); - if (IS_ERR(lpp->core_rst)) { - ret =3D PTR_ERR(lpp->core_rst); + pcie->core_rst =3D devm_reset_control_get(dev, NULL); + if (IS_ERR(pcie->core_rst)) { + ret =3D PTR_ERR(pcie->core_rst); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "Failed to get resets: %d\n", ret); return ret; } =20 ret =3D device_property_read_u32(dev, "reset-assert-ms", - &lpp->rst_intrvl); + &pcie->rst_intrvl); if (ret) - lpp->rst_intrvl =3D RESET_INTERVAL_MS; + pcie->rst_intrvl =3D RESET_INTERVAL_MS; =20 - lpp->app_base =3D devm_platform_ioremap_resource_byname(pdev, "app"); - if (IS_ERR(lpp->app_base)) - return PTR_ERR(lpp->app_base); + pcie->app_base =3D devm_platform_ioremap_resource_byname(pdev, "app"); + if (IS_ERR(pcie->app_base)) + return PTR_ERR(pcie->app_base); =20 - lpp->phy =3D devm_phy_get(dev, "pcie"); - if (IS_ERR(lpp->phy)) { - ret =3D PTR_ERR(lpp->phy); + pcie->phy =3D devm_phy_get(dev, "pcie"); + if (IS_ERR(pcie->phy)) { + ret =3D PTR_ERR(pcie->phy); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "Couldn't get pcie-phy: %d\n", ret); return ret; @@ -248,137 +248,137 @@ static int intel_pcie_get_resources(struct platform= _device *pdev) return 0; } =20 -static int intel_pcie_wait_l2(struct intel_pcie_port *lpp) +static int intel_pcie_wait_l2(struct intel_pcie *pcie) { u32 value; int ret; - struct dw_pcie *pci =3D &lpp->pci; + struct dw_pcie *pci =3D &pcie->pci; =20 if (pci->link_gen < 3) return 0; =20 /* Send PME_TURN_OFF message */ - pcie_app_wr_mask(lpp, PCIE_APP_MSG_CR, PCIE_APP_MSG_XMT_PM_TURNOFF, + pcie_app_wr_mask(pcie, PCIE_APP_MSG_CR, PCIE_APP_MSG_XMT_PM_TURNOFF, PCIE_APP_MSG_XMT_PM_TURNOFF); =20 /* Read PMC status and wait for falling into L2 link state */ - ret =3D readl_poll_timeout(lpp->app_base + PCIE_APP_PMC, value, + ret =3D readl_poll_timeout(pcie->app_base + PCIE_APP_PMC, value, value & PCIE_APP_PMC_IN_L2, 20, jiffies_to_usecs(5 * HZ)); if (ret) - dev_err(lpp->pci.dev, "PCIe link enter L2 timeout!\n"); + dev_err(pcie->pci.dev, "PCIe link enter L2 timeout!\n"); =20 return ret; } =20 -static void intel_pcie_turn_off(struct intel_pcie_port *lpp) +static void intel_pcie_turn_off(struct intel_pcie *pcie) { - if (dw_pcie_link_up(&lpp->pci)) - intel_pcie_wait_l2(lpp); + if (dw_pcie_link_up(&pcie->pci)) + intel_pcie_wait_l2(pcie); =20 /* Put endpoint device in reset state */ - intel_pcie_device_rst_assert(lpp); - pcie_rc_cfg_wr_mask(lpp, PCI_COMMAND, PCI_COMMAND_MEMORY, 0); + intel_pcie_device_rst_assert(pcie); + pcie_rc_cfg_wr_mask(pcie, PCI_COMMAND, PCI_COMMAND_MEMORY, 0); } =20 -static int intel_pcie_host_setup(struct intel_pcie_port *lpp) +static int intel_pcie_host_setup(struct intel_pcie *pcie) { int ret; - struct dw_pcie *pci =3D &lpp->pci; + struct dw_pcie *pci =3D &pcie->pci; =20 - intel_pcie_core_rst_assert(lpp); - intel_pcie_device_rst_assert(lpp); + intel_pcie_core_rst_assert(pcie); + intel_pcie_device_rst_assert(pcie); =20 - ret =3D phy_init(lpp->phy); + ret =3D phy_init(pcie->phy); if (ret) return ret; =20 - intel_pcie_core_rst_deassert(lpp); + intel_pcie_core_rst_deassert(pcie); =20 - ret =3D clk_prepare_enable(lpp->core_clk); + ret =3D clk_prepare_enable(pcie->core_clk); if (ret) { - dev_err(lpp->pci.dev, "Core clock enable failed: %d\n", ret); + dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret); goto clk_err; } =20 pci->atu_base =3D pci->dbi_base + 0xC0000; =20 - intel_pcie_ltssm_disable(lpp); - intel_pcie_link_setup(lpp); + intel_pcie_ltssm_disable(pcie); + intel_pcie_link_setup(pcie); intel_pcie_init_n_fts(pci); dw_pcie_setup_rc(&pci->pp); dw_pcie_upconfig_setup(pci); =20 - intel_pcie_device_rst_deassert(lpp); - intel_pcie_ltssm_enable(lpp); + intel_pcie_device_rst_deassert(pcie); + intel_pcie_ltssm_enable(pcie); =20 ret =3D dw_pcie_wait_for_link(pci); if (ret) goto app_init_err; =20 /* Enable integrated interrupts */ - pcie_app_wr_mask(lpp, PCIE_APP_IRNEN, PCIE_APP_IRN_INT, + pcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT, PCIE_APP_IRN_INT); =20 return 0; =20 app_init_err: - clk_disable_unprepare(lpp->core_clk); + clk_disable_unprepare(pcie->core_clk); clk_err: - intel_pcie_core_rst_assert(lpp); - phy_exit(lpp->phy); + intel_pcie_core_rst_assert(pcie); + phy_exit(pcie->phy); =20 return ret; } =20 -static void __intel_pcie_remove(struct intel_pcie_port *lpp) +static void __intel_pcie_remove(struct intel_pcie *pcie) { - intel_pcie_core_irq_disable(lpp); - intel_pcie_turn_off(lpp); - clk_disable_unprepare(lpp->core_clk); - intel_pcie_core_rst_assert(lpp); - phy_exit(lpp->phy); + intel_pcie_core_irq_disable(pcie); + intel_pcie_turn_off(pcie); + clk_disable_unprepare(pcie->core_clk); + intel_pcie_core_rst_assert(pcie); + phy_exit(pcie->phy); } =20 static int intel_pcie_remove(struct platform_device *pdev) { - struct intel_pcie_port *lpp =3D platform_get_drvdata(pdev); - struct pcie_port *pp =3D &lpp->pci.pp; + struct intel_pcie *pcie =3D platform_get_drvdata(pdev); + struct pcie_port *pp =3D &pcie->pci.pp; =20 dw_pcie_host_deinit(pp); - __intel_pcie_remove(lpp); + __intel_pcie_remove(pcie); =20 return 0; } =20 static int __maybe_unused intel_pcie_suspend_noirq(struct device *dev) { - struct intel_pcie_port *lpp =3D dev_get_drvdata(dev); + struct intel_pcie *pcie =3D dev_get_drvdata(dev); int ret; =20 - intel_pcie_core_irq_disable(lpp); - ret =3D intel_pcie_wait_l2(lpp); + intel_pcie_core_irq_disable(pcie); + ret =3D intel_pcie_wait_l2(pcie); if (ret) return ret; =20 - phy_exit(lpp->phy); - clk_disable_unprepare(lpp->core_clk); + phy_exit(pcie->phy); + clk_disable_unprepare(pcie->core_clk); return ret; } =20 static int __maybe_unused intel_pcie_resume_noirq(struct device *dev) { - struct intel_pcie_port *lpp =3D dev_get_drvdata(dev); + struct intel_pcie *pcie =3D dev_get_drvdata(dev); =20 - return intel_pcie_host_setup(lpp); + return intel_pcie_host_setup(pcie); } =20 static int intel_pcie_rc_init(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct intel_pcie_port *lpp =3D dev_get_drvdata(pci->dev); + struct intel_pcie *pcie =3D dev_get_drvdata(pci->dev); =20 - return intel_pcie_host_setup(lpp); + return intel_pcie_host_setup(pcie); } =20 static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr) @@ -402,17 +402,17 @@ static int intel_pcie_probe(struct platform_device *p= dev) { const struct intel_pcie_soc *data; struct device *dev =3D &pdev->dev; - struct intel_pcie_port *lpp; + struct intel_pcie *pcie; struct pcie_port *pp; struct dw_pcie *pci; int ret; =20 - lpp =3D devm_kzalloc(dev, sizeof(*lpp), GFP_KERNEL); - if (!lpp) + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) return -ENOMEM; =20 - platform_set_drvdata(pdev, lpp); - pci =3D &lpp->pci; + platform_set_drvdata(pdev, pcie); + pci =3D &pcie->pci; pci->dev =3D dev; pp =3D &pci->pp; =20 @@ -420,7 +420,7 @@ static int intel_pcie_probe(struct platform_device *pde= v) if (ret) return ret; =20 - ret =3D intel_pcie_ep_rst_init(lpp); + ret =3D intel_pcie_ep_rst_init(pcie); if (ret) return ret; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35075C433F5 for ; Thu, 23 Dec 2021 01:11:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345747AbhLWBLk (ORCPT ); Wed, 22 Dec 2021 20:11:40 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57720 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345694AbhLWBLd (ORCPT ); Wed, 22 Dec 2021 20:11:33 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id A65F4CE1F12; Thu, 23 Dec 2021 01:11:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B7077C36AE5; Thu, 23 Dec 2021 01:11:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221890; bh=y3pxRiX+qtgtCOGnhVvNZl0hOJWzWrcEKk0/Nd0XPes=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mSJxMrBnD05miAkVZqHAOo3r5V+Has0Fw5v5bB8h4TLDi182/0nzK989zg+rpidjy 3jbny0Ta/y/7bRXdrDeHzLw4WI6BWhdfTvdjKOoUL7wBYJGH2UC4teVAiwTSf8xVxu tvJp8rSYPXxbJHdz6sSh44A4+2h/f+vzApWTT8rDElcElzYyxxg6AGxfAjWcK7OlHa aJPwKFduLkEETH/rpffSVVMiBj6dbw2wyyHLhg7Yh9yS8TUYhkIyI3DLx8jSfZEjRH AebagG5gTVBvX2pKzjOWVMavmC1iGfqxAQN/NKi2tzmyMqY5pua6689Rf7JTBEdEO6 cld1P7lFwwamQ== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 11/23] PCI: iproc: Rename iproc_pcie_bcma_ to iproc_bcma_pcie_ Date: Wed, 22 Dec 2021 19:10:42 -0600 Message-Id: <20211223011054.1227810-12-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename iproc_pcie_bcma_* to iproc_bcma_pcie_* for consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas Cc: Ray Jui Cc: Scott Branden Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/pcie-iproc-bcma.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc-bcma.c b/drivers/pci/control= ler/pcie-iproc-bcma.c index f918c713afb0..54b6e6d5bc64 100644 --- a/drivers/pci/controller/pcie-iproc-bcma.c +++ b/drivers/pci/controller/pcie-iproc-bcma.c @@ -23,7 +23,7 @@ static void bcma_pcie2_fixup_class(struct pci_dev *dev) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8011, bcma_pcie2_fixup_c= lass); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8012, bcma_pcie2_fixup_c= lass); =20 -static int iproc_pcie_bcma_map_irq(const struct pci_dev *dev, u8 slot, u8 = pin) +static int iproc_bcma_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 = pin) { struct iproc_pcie *pcie =3D dev->sysdata; struct bcma_device *bdev =3D container_of(pcie->dev, struct bcma_device, = dev); @@ -31,7 +31,7 @@ static int iproc_pcie_bcma_map_irq(const struct pci_dev *= dev, u8 slot, u8 pin) return bcma_core_irq(bdev, 5); } =20 -static int iproc_pcie_bcma_probe(struct bcma_device *bdev) +static int iproc_bcma_pcie_probe(struct bcma_device *bdev) { struct device *dev =3D &bdev->dev; struct iproc_pcie *pcie; @@ -64,33 +64,33 @@ static int iproc_pcie_bcma_probe(struct bcma_device *bd= ev) if (ret) return ret; =20 - pcie->map_irq =3D iproc_pcie_bcma_map_irq; + pcie->map_irq =3D iproc_bcma_pcie_map_irq; =20 bcma_set_drvdata(bdev, pcie); =20 return iproc_pcie_setup(pcie, &bridge->windows); } =20 -static void iproc_pcie_bcma_remove(struct bcma_device *bdev) +static void iproc_bcma_pcie_remove(struct bcma_device *bdev) { struct iproc_pcie *pcie =3D bcma_get_drvdata(bdev); =20 iproc_pcie_remove(pcie); } =20 -static const struct bcma_device_id iproc_pcie_bcma_table[] =3D { +static const struct bcma_device_id iproc_bcma_pcie_table[] =3D { BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_PCIEG2, BCMA_ANY_REV, BCMA_ANY_CLA= SS), {}, }; -MODULE_DEVICE_TABLE(bcma, iproc_pcie_bcma_table); +MODULE_DEVICE_TABLE(bcma, iproc_bcma_pcie_table); =20 -static struct bcma_driver iproc_pcie_bcma_driver =3D { +static struct bcma_driver iproc_bcma_pcie_driver =3D { .name =3D KBUILD_MODNAME, - .id_table =3D iproc_pcie_bcma_table, - .probe =3D iproc_pcie_bcma_probe, - .remove =3D iproc_pcie_bcma_remove, + .id_table =3D iproc_bcma_pcie_table, + .probe =3D iproc_bcma_pcie_probe, + .remove =3D iproc_bcma_pcie_remove, }; -module_bcma_driver(iproc_pcie_bcma_driver); +module_bcma_driver(iproc_bcma_pcie_driver); =20 MODULE_AUTHOR("Hauke Mehrtens"); MODULE_DESCRIPTION("Broadcom iProc PCIe BCMA driver"); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C589C433FE for ; Thu, 23 Dec 2021 01:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345767AbhLWBLm (ORCPT ); Wed, 22 Dec 2021 20:11:42 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57816 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345711AbhLWBLf (ORCPT ); Wed, 22 Dec 2021 20:11:35 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 7E461CE1F02; Thu, 23 Dec 2021 01:11:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86F11C36AEB; Thu, 23 Dec 2021 01:11:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221891; bh=f04xaSCWCbCEFfwG/HFC1grHJ9t6oRK/Bi24pKjCZyI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nvMXfI+W4QtXhYQ0wlO4ZGP5oRI/bDTLIiZQCZnxqDYqFZHNNnvNRAJgUP/uHpaFI Rn9nowg/KHh9eBZDc4XPV4b069qKgcgPjfIA56aihCYeI4vpGn1krWcUf+B9HwT/8f cs88HTW+jpYAcDiX0IZ9ewhy0+kTetN/aimbDjRNsCaxvXtwjjRo+e48zsZJLV//nb eXxp3z8Yo6XzfIEbH6RVTJDc0/GyPVgFJce7STlxmkrxaIh+c33YHrHPtYLWol9c0V R6weAMgfvq+8wnxzxkHdsGsul/2lD09fHFT/az/+xOiphMyohTyTI5RB5W36StJ512 yzvjwvNWecxFw== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 12/23] PCI: iproc: Rename iproc_pcie_pltfm_ to iproc_pltfm_pcie_ Date: Wed, 22 Dec 2021 19:10:43 -0600 Message-Id: <20211223011054.1227810-13-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename iproc_pcie_pltfm_* to iproc_pltfm_pcie_* for consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas Cc: Ray Jui Cc: Scott Branden Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/pcie-iproc-platform.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc-platform.c b/drivers/pci/con= troller/pcie-iproc-platform.c index b93e7bda101b..538115246c79 100644 --- a/drivers/pci/controller/pcie-iproc-platform.c +++ b/drivers/pci/controller/pcie-iproc-platform.c @@ -37,7 +37,7 @@ static const struct of_device_id iproc_pcie_of_match_tabl= e[] =3D { }; MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table); =20 -static int iproc_pcie_pltfm_probe(struct platform_device *pdev) +static int iproc_pltfm_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct iproc_pcie *pcie; @@ -115,30 +115,30 @@ static int iproc_pcie_pltfm_probe(struct platform_dev= ice *pdev) return 0; } =20 -static int iproc_pcie_pltfm_remove(struct platform_device *pdev) +static int iproc_pltfm_pcie_remove(struct platform_device *pdev) { struct iproc_pcie *pcie =3D platform_get_drvdata(pdev); =20 return iproc_pcie_remove(pcie); } =20 -static void iproc_pcie_pltfm_shutdown(struct platform_device *pdev) +static void iproc_pltfm_pcie_shutdown(struct platform_device *pdev) { struct iproc_pcie *pcie =3D platform_get_drvdata(pdev); =20 iproc_pcie_shutdown(pcie); } =20 -static struct platform_driver iproc_pcie_pltfm_driver =3D { +static struct platform_driver iproc_pltfm_pcie_driver =3D { .driver =3D { .name =3D "iproc-pcie", .of_match_table =3D of_match_ptr(iproc_pcie_of_match_table), }, - .probe =3D iproc_pcie_pltfm_probe, - .remove =3D iproc_pcie_pltfm_remove, - .shutdown =3D iproc_pcie_pltfm_shutdown, + .probe =3D iproc_pltfm_pcie_probe, + .remove =3D iproc_pltfm_pcie_remove, + .shutdown =3D iproc_pltfm_pcie_shutdown, }; -module_platform_driver(iproc_pcie_pltfm_driver); +module_platform_driver(iproc_pltfm_pcie_driver); =20 MODULE_AUTHOR("Ray Jui "); MODULE_DESCRIPTION("Broadcom iPROC PCIe platform driver"); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD0EC433F5 for ; Thu, 23 Dec 2021 01:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345851AbhLWBL6 (ORCPT ); Wed, 22 Dec 2021 20:11:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345696AbhLWBLh (ORCPT ); Wed, 22 Dec 2021 20:11:37 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26F4BC061574; Wed, 22 Dec 2021 17:11:37 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 4697FCE1EFE; Thu, 23 Dec 2021 01:11:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4DAFAC36AE8; Thu, 23 Dec 2021 01:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221893; bh=3Tj4Y1m9tQ5GKnqMmsuZj0fnhQ1cujxeFXKQmeEOGCQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e4T/UIuTuSxuQWUbrBMmwjRXo7GAwjebtuOpycOF3xRaUwUM2hnS7AW4KzQCODVuL Uf1Yow7CEEsRjDShB9kOSUEbTUio5deGIxPBrj9mzei059v6Jc+/MdzpiCmR6d99ux 5yHgct7S8B4wiQWht7gJz7WdNSoUBa9uIAlaPVPQ3BWrxWs31hScI3Ir/CmPZbxXlf NW2QUBNu+FPdkpqfngMl57zmf1aKBKn129Vko91N6N0CDXpFfl7FsCwouaOTfqhW+S /GHJtEcLlQQGri6PeFR033NCsds6cfpRE2LSZCaCvM+6uTb1L9ADJvLfFxiXY2hrOt jT0le0eNfNpXw== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Hou Zhiqiang , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/23] PCI: ls-gen4: Rename ls_pcie_g4 to ls_g4_pcie Date: Wed, 22 Dec 2021 19:10:44 -0600 Message-Id: <20211223011054.1227810-14-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename struct ls_pcie_g4 to ls_g4_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Bjorn Helgaas Cc: Hou Zhiqiang Cc: linux-arm-kernel@lists.infradead.org --- .../mobiveil/pcie-layerscape-gen4.c | 84 +++++++++---------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drive= rs/pci/controller/mobiveil/pcie-layerscape-gen4.c index 306950272fd6..d7b7350f02dd 100644 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c @@ -34,31 +34,31 @@ #define PF_DBG_WE BIT(31) #define PF_DBG_PABR BIT(27) =20 -#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) +#define to_ls_g4_pcie(x) platform_get_drvdata((x)->pdev) =20 -struct ls_pcie_g4 { +struct ls_g4_pcie { struct mobiveil_pcie pci; struct delayed_work dwork; int irq; }; =20 -static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) +static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) { return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); } =20 -static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, +static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, u32 off, u32 val) { iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); } =20 -static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) +static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci) { - struct ls_pcie_g4 *pcie =3D to_ls_pcie_g4(pci); + struct ls_g4_pcie *pcie =3D to_ls_g4_pcie(pci); u32 state; =20 - state =3D ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + state =3D ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); state =3D state & PF_DBG_LTSSM_MASK; =20 if (state =3D=3D PF_DBG_LTSSM_L0) @@ -67,14 +67,14 @@ static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) return 0; } =20 -static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie) +static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) { struct mobiveil_pcie *mv_pci =3D &pcie->pci; =20 mobiveil_csr_writel(mv_pci, 0, PAB_INTP_AMBA_MISC_ENB); } =20 -static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie) +static void ls_g4_pcie_enable_interrupt(struct ls_g4_pcie *pcie) { struct mobiveil_pcie *mv_pci =3D &pcie->pci; u32 val; @@ -87,7 +87,7 @@ static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4= *pcie) mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); } =20 -static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) +static int ls_g4_pcie_reinit_hw(struct ls_g4_pcie *pcie) { struct mobiveil_pcie *mv_pci =3D &pcie->pci; struct device *dev =3D &mv_pci->pdev->dev; @@ -97,7 +97,7 @@ static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) /* Poll for pab_csb_reset to set and PAB activity to clear */ do { usleep_range(10, 15); - val =3D ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT); + val =3D ls_g4_pcie_pf_readl(pcie, PCIE_PF_INT_STAT); act_stat =3D mobiveil_csr_readl(mv_pci, PAB_ACTIVITY_STAT); } while (((val & PF_INT_STAT_PABRST) =3D=3D 0 || act_stat) && to--); if (to < 0) { @@ -106,22 +106,22 @@ static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pc= ie) } =20 /* clear PEX_RESET bit in PEX_PF0_DBG register */ - val =3D ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val =3D ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); val |=3D PF_DBG_WE; - ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val); =20 - val =3D ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val =3D ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); val |=3D PF_DBG_PABR; - ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val); =20 - val =3D ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val =3D ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); val &=3D ~PF_DBG_WE; - ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val); =20 mobiveil_host_init(mv_pci, true); =20 to =3D 100; - while (!ls_pcie_g4_link_up(mv_pci) && to--) + while (!ls_g4_pcie_link_up(mv_pci) && to--) usleep_range(200, 250); if (to < 0) { dev_err(dev, "PCIe link training timeout\n"); @@ -131,9 +131,9 @@ static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) return 0; } =20 -static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id) +static irqreturn_t ls_g4_pcie_isr(int irq, void *dev_id) { - struct ls_pcie_g4 *pcie =3D (struct ls_pcie_g4 *)dev_id; + struct ls_g4_pcie *pcie =3D (struct ls_g4_pcie *)dev_id; struct mobiveil_pcie *mv_pci =3D &pcie->pci; u32 val; =20 @@ -142,7 +142,7 @@ static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id) return IRQ_NONE; =20 if (val & PAB_INTP_RESET) { - ls_pcie_g4_disable_interrupt(pcie); + ls_g4_pcie_disable_interrupt(pcie); schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); } =20 @@ -151,9 +151,9 @@ static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id) return IRQ_HANDLED; } =20 -static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) +static int ls_g4_pcie_interrupt_init(struct mobiveil_pcie *mv_pci) { - struct ls_pcie_g4 *pcie =3D to_ls_pcie_g4(mv_pci); + struct ls_g4_pcie *pcie =3D to_ls_g4_pcie(mv_pci); struct platform_device *pdev =3D mv_pci->pdev; struct device *dev =3D &pdev->dev; int ret; @@ -162,7 +162,7 @@ static int ls_pcie_g4_interrupt_init(struct mobiveil_pc= ie *mv_pci) if (pcie->irq < 0) return pcie->irq; =20 - ret =3D devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr, + ret =3D devm_request_irq(dev, pcie->irq, ls_g4_pcie_isr, IRQF_SHARED, pdev->name, pcie); if (ret) { dev_err(dev, "Can't register PCIe IRQ, errno =3D %d\n", ret); @@ -172,11 +172,11 @@ static int ls_pcie_g4_interrupt_init(struct mobiveil_= pcie *mv_pci) return 0; } =20 -static void ls_pcie_g4_reset(struct work_struct *work) +static void ls_g4_pcie_reset(struct work_struct *work) { struct delayed_work *dwork =3D container_of(work, struct delayed_work, work); - struct ls_pcie_g4 *pcie =3D container_of(dwork, struct ls_pcie_g4, dwork); + struct ls_g4_pcie *pcie =3D container_of(dwork, struct ls_g4_pcie, dwork); struct mobiveil_pcie *mv_pci =3D &pcie->pci; u16 ctrl; =20 @@ -184,26 +184,26 @@ static void ls_pcie_g4_reset(struct work_struct *work) ctrl &=3D ~PCI_BRIDGE_CTL_BUS_RESET; mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); =20 - if (!ls_pcie_g4_reinit_hw(pcie)) + if (!ls_g4_pcie_reinit_hw(pcie)) return; =20 - ls_pcie_g4_enable_interrupt(pcie); + ls_g4_pcie_enable_interrupt(pcie); } =20 -static struct mobiveil_rp_ops ls_pcie_g4_rp_ops =3D { - .interrupt_init =3D ls_pcie_g4_interrupt_init, +static struct mobiveil_rp_ops ls_g4_pcie_rp_ops =3D { + .interrupt_init =3D ls_g4_pcie_interrupt_init, }; =20 -static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops =3D { - .link_up =3D ls_pcie_g4_link_up, +static const struct mobiveil_pab_ops ls_g4_pcie_pab_ops =3D { + .link_up =3D ls_g4_pcie_link_up, }; =20 -static int __init ls_pcie_g4_probe(struct platform_device *pdev) +static int __init ls_g4_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct pci_host_bridge *bridge; struct mobiveil_pcie *mv_pci; - struct ls_pcie_g4 *pcie; + struct ls_g4_pcie *pcie; struct device_node *np =3D dev->of_node; int ret; =20 @@ -220,13 +220,13 @@ static int __init ls_pcie_g4_probe(struct platform_de= vice *pdev) mv_pci =3D &pcie->pci; =20 mv_pci->pdev =3D pdev; - mv_pci->ops =3D &ls_pcie_g4_pab_ops; - mv_pci->rp.ops =3D &ls_pcie_g4_rp_ops; + mv_pci->ops =3D &ls_g4_pcie_pab_ops; + mv_pci->rp.ops =3D &ls_g4_pcie_rp_ops; mv_pci->rp.bridge =3D bridge; =20 platform_set_drvdata(pdev, pcie); =20 - INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset); + INIT_DELAYED_WORK(&pcie->dwork, ls_g4_pcie_reset); =20 ret =3D mobiveil_pcie_host_probe(mv_pci); if (ret) { @@ -234,22 +234,22 @@ static int __init ls_pcie_g4_probe(struct platform_de= vice *pdev) return ret; } =20 - ls_pcie_g4_enable_interrupt(pcie); + ls_g4_pcie_enable_interrupt(pcie); =20 return 0; } =20 -static const struct of_device_id ls_pcie_g4_of_match[] =3D { +static const struct of_device_id ls_g4_pcie_of_match[] =3D { { .compatible =3D "fsl,lx2160a-pcie", }, { }, }; =20 -static struct platform_driver ls_pcie_g4_driver =3D { +static struct platform_driver ls_g4_pcie_driver =3D { .driver =3D { .name =3D "layerscape-pcie-gen4", - .of_match_table =3D ls_pcie_g4_of_match, + .of_match_table =3D ls_g4_pcie_of_match, .suppress_bind_attrs =3D true, }, }; =20 -builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe); +builtin_platform_driver_probe(ls_g4_pcie_driver, ls_g4_pcie_probe); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07C3DC433F5 for ; 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d=kernel.org; s=k20201202; t=1640221895; bh=OUS6SZ3H86mzld6IWPyuVgKtmVSAm+sRnOU5MJr56+Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ja010Bek3D4n6/Sbi1Qu76SZQ+avlrgQBVOFQynq8Qq2fXJm/ftLA6T5yQmykl0PC DhY+XM1rhCb2cykZI1w3L6K9LUr5eFqLdgfKQHiJP+jWdQDeXwFLKBiy5SbuobZsee 5zPArdDFCJHi0V+hH/eiIU7TrVbokvrzmd/1tB3w8OOAC5xkOJPOtgWdV7H3s6OJAv gGSQbAtUOKIJjYxP5cwz0JNoOLl3TT6eTo9GlJy0Pq5UcLR/kisGylV2bX++I6YTWw i/ceQz2ieZqbcelV3sWPsbw/HBLUPqRyM3p98S93XzQEStZa/puE+iTvW28dUWGG0o E1tFzNsmzwZ+w== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Ryder Lee , Jianjun Wang , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 14/23] PCI: mediatek-gen3: Rename mtk_pcie_port to mtk_gen3_pcie Date: Wed, 22 Dec 2021 19:10:45 -0600 Message-Id: <20211223011054.1227810-15-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei Rename struct mtk_pcie_port to mtk_gen3_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Ryder Lee Cc: Jianjun Wang Cc: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/pcie-mediatek-gen3.c | 372 ++++++++++---------- 1 file changed, 186 insertions(+), 186 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 17c59b0d6978..be513fb390cf 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -110,7 +110,7 @@ struct mtk_msi_set { }; =20 /** - * struct mtk_pcie_port - PCIe port information + * struct mtk_gen3_pcie - PCIe port information * @dev: pointer to PCIe device * @base: IO mapped register base * @reg_base: physical register base @@ -129,7 +129,7 @@ struct mtk_msi_set { * @lock: lock protecting IRQ bit map * @msi_irq_in_use: bit map for assigned MSI IRQ */ -struct mtk_pcie_port { +struct mtk_gen3_pcie { struct device *dev; void __iomem *base; phys_addr_t reg_base; @@ -162,7 +162,7 @@ struct mtk_pcie_port { static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int d= evfn, int where, int size) { - struct mtk_pcie_port *port =3D bus->sysdata; + struct mtk_gen3_pcie *pcie =3D bus->sysdata; int bytes; u32 val; =20 @@ -171,15 +171,15 @@ static void mtk_pcie_config_tlp_header(struct pci_bus= *bus, unsigned int devfn, val =3D PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) | PCIE_CFG_HEADER(bus->number, devfn); =20 - writel_relaxed(val, port->base + PCIE_CFGNUM_REG); + writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); } =20 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int de= vfn, int where) { - struct mtk_pcie_port *port =3D bus->sysdata; + struct mtk_gen3_pcie *pcie =3D bus->sysdata; =20 - return port->base + PCIE_CFG_OFFSET_ADDR + where; + return pcie->base + PCIE_CFG_OFFSET_ADDR + where; } =20 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, @@ -207,7 +207,7 @@ static struct pci_ops mtk_pcie_ops =3D { .write =3D mtk_pcie_config_write, }; =20 -static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port, +static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, resource_size_t cpu_addr, resource_size_t pci_addr, resource_size_t size, @@ -217,12 +217,12 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_p= ort *port, u32 val; =20 if (num >=3D PCIE_MAX_TRANS_TABLES) { - dev_err(port->dev, "not enough translate table for addr: %#llx, limited = to [%d]\n", + dev_err(pcie->dev, "not enough translate table for addr: %#llx, limited = to [%d]\n", (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES); return -ENODEV; } =20 - table =3D port->base + PCIE_TRANS_TABLE_BASE_REG + + table =3D pcie->base + PCIE_TRANS_TABLE_BASE_REG + num * PCIE_ATR_TLB_SET_OFFSET; =20 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1), @@ -244,63 +244,63 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_p= ort *port, return 0; } =20 -static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) +static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) { int i; u32 val; =20 for (i =3D 0; i < PCIE_MSI_SET_NUM; i++) { - struct mtk_msi_set *msi_set =3D &port->msi_sets[i]; + struct mtk_msi_set *msi_set =3D &pcie->msi_sets[i]; =20 - msi_set->base =3D port->base + PCIE_MSI_SET_BASE_REG + + msi_set->base =3D pcie->base + PCIE_MSI_SET_BASE_REG + i * PCIE_MSI_SET_OFFSET; - msi_set->msg_addr =3D port->reg_base + PCIE_MSI_SET_BASE_REG + + msi_set->msg_addr =3D pcie->reg_base + PCIE_MSI_SET_BASE_REG + i * PCIE_MSI_SET_OFFSET; =20 /* Configure the MSI capture address */ writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); writel_relaxed(upper_32_bits(msi_set->msg_addr), - port->base + PCIE_MSI_SET_ADDR_HI_BASE + + pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + i * PCIE_MSI_SET_ADDR_HI_OFFSET); } =20 - val =3D readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG); + val =3D readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); val |=3D PCIE_MSI_SET_ENABLE; - writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG); + writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); =20 - val =3D readl_relaxed(port->base + PCIE_INT_ENABLE_REG); + val =3D readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); val |=3D PCIE_MSI_ENABLE; - writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); + writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); } =20 -static int mtk_pcie_startup_port(struct mtk_pcie_port *port) +static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) { struct resource_entry *entry; - struct pci_host_bridge *host =3D pci_host_bridge_from_priv(port); + struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); unsigned int table_index =3D 0; int err; u32 val; =20 /* Set as RC mode */ - val =3D readl_relaxed(port->base + PCIE_SETTING_REG); + val =3D readl_relaxed(pcie->base + PCIE_SETTING_REG); val |=3D PCIE_RC_MODE; - writel_relaxed(val, port->base + PCIE_SETTING_REG); + writel_relaxed(val, pcie->base + PCIE_SETTING_REG); =20 /* Set class code */ - val =3D readl_relaxed(port->base + PCIE_PCI_IDS_1); + val =3D readl_relaxed(pcie->base + PCIE_PCI_IDS_1); val &=3D ~GENMASK(31, 8); val |=3D PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - writel_relaxed(val, port->base + PCIE_PCI_IDS_1); + writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1); =20 /* Mask all INTx interrupts */ - val =3D readl_relaxed(port->base + PCIE_INT_ENABLE_REG); + val =3D readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); val &=3D ~PCIE_INTX_ENABLE; - writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); + writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); =20 /* Assert all reset signals */ - val =3D readl_relaxed(port->base + PCIE_RST_CTRL_REG); + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; - writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); =20 /* * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) @@ -312,19 +312,19 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port= *port) =20 /* De-assert reset signals */ val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); - writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); =20 /* Check if the link is up or not */ - err =3D readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val, + err =3D readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, !!(val & PCIE_PORT_LINKUP), 20, PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); if (err) { - val =3D readl_relaxed(port->base + PCIE_LTSSM_STATUS_REG); - dev_err(port->dev, "PCIe link down, ltssm reg val: %#x\n", val); + val =3D readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG); + dev_err(pcie->dev, "PCIe link down, ltssm reg val: %#x\n", val); return err; } =20 - mtk_pcie_enable_msi(port); + mtk_pcie_enable_msi(pcie); =20 /* Set PCIe translation windows */ resource_list_for_each_entry(entry, &host->windows) { @@ -347,12 +347,12 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port= *port) =20 pci_addr =3D res->start - entry->offset; size =3D resource_size(res); - err =3D mtk_pcie_set_trans_table(port, cpu_addr, pci_addr, size, + err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, type, table_index); if (err) return err; =20 - dev_dbg(port->dev, "set %s trans window[%d]: cpu_addr =3D %#llx, pci_add= r =3D %#llx, size =3D %#llx\n", + dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr =3D %#llx, pci_add= r =3D %#llx, size =3D %#llx\n", range_type, table_index, (unsigned long long)cpu_addr, (unsigned long long)pci_addr, (unsigned long long)size); =20 @@ -396,7 +396,7 @@ static struct msi_domain_info mtk_msi_domain_info =3D { static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct mtk_msi_set *msi_set =3D irq_data_get_irq_chip_data(data); - struct mtk_pcie_port *port =3D data->domain->host_data; + struct mtk_gen3_pcie *pcie =3D data->domain->host_data; unsigned long hwirq; =20 hwirq =3D data->hwirq % PCIE_MSI_IRQS_PER_SET; @@ -404,7 +404,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, = struct msi_msg *msg) msg->address_hi =3D upper_32_bits(msi_set->msg_addr); msg->address_lo =3D lower_32_bits(msi_set->msg_addr); msg->data =3D hwirq; - dev_dbg(port->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", + dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", hwirq, msg->address_hi, msg->address_lo, msg->data); } =20 @@ -421,33 +421,33 @@ static void mtk_msi_bottom_irq_ack(struct irq_data *d= ata) static void mtk_msi_bottom_irq_mask(struct irq_data *data) { struct mtk_msi_set *msi_set =3D irq_data_get_irq_chip_data(data); - struct mtk_pcie_port *port =3D data->domain->host_data; + struct mtk_gen3_pcie *pcie =3D data->domain->host_data; unsigned long hwirq, flags; u32 val; =20 hwirq =3D data->hwirq % PCIE_MSI_IRQS_PER_SET; =20 - raw_spin_lock_irqsave(&port->irq_lock, flags); + raw_spin_lock_irqsave(&pcie->irq_lock, flags); val =3D readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); val &=3D ~BIT(hwirq); writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); - raw_spin_unlock_irqrestore(&port->irq_lock, flags); + raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); } =20 static void mtk_msi_bottom_irq_unmask(struct irq_data *data) { struct mtk_msi_set *msi_set =3D irq_data_get_irq_chip_data(data); - struct mtk_pcie_port *port =3D data->domain->host_data; + struct mtk_gen3_pcie *pcie =3D data->domain->host_data; unsigned long hwirq, flags; u32 val; =20 hwirq =3D data->hwirq % PCIE_MSI_IRQS_PER_SET; =20 - raw_spin_lock_irqsave(&port->irq_lock, flags); + raw_spin_lock_irqsave(&pcie->irq_lock, flags); val =3D readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); val |=3D BIT(hwirq); writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); - raw_spin_unlock_irqrestore(&port->irq_lock, flags); + raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); } =20 static struct irq_chip mtk_msi_bottom_irq_chip =3D { @@ -463,22 +463,22 @@ static int mtk_msi_bottom_domain_alloc(struct irq_dom= ain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { - struct mtk_pcie_port *port =3D domain->host_data; + struct mtk_gen3_pcie *pcie =3D domain->host_data; struct mtk_msi_set *msi_set; int i, hwirq, set_idx; =20 - mutex_lock(&port->lock); + mutex_lock(&pcie->lock); =20 - hwirq =3D bitmap_find_free_region(port->msi_irq_in_use, PCIE_MSI_IRQS_NUM, + hwirq =3D bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM, order_base_2(nr_irqs)); =20 - mutex_unlock(&port->lock); + mutex_unlock(&pcie->lock); =20 if (hwirq < 0) return -ENOSPC; =20 set_idx =3D hwirq / PCIE_MSI_IRQS_PER_SET; - msi_set =3D &port->msi_sets[set_idx]; + msi_set =3D &pcie->msi_sets[set_idx]; =20 for (i =3D 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, hwirq + i, @@ -491,15 +491,15 @@ static int mtk_msi_bottom_domain_alloc(struct irq_dom= ain *domain, static void mtk_msi_bottom_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { - struct mtk_pcie_port *port =3D domain->host_data; + struct mtk_gen3_pcie *pcie =3D domain->host_data; struct irq_data *data =3D irq_domain_get_irq_data(domain, virq); =20 - mutex_lock(&port->lock); + mutex_lock(&pcie->lock); =20 - bitmap_release_region(port->msi_irq_in_use, data->hwirq, + bitmap_release_region(pcie->msi_irq_in_use, data->hwirq, order_base_2(nr_irqs)); =20 - mutex_unlock(&port->lock); + mutex_unlock(&pcie->lock); =20 irq_domain_free_irqs_common(domain, virq, nr_irqs); } @@ -511,28 +511,28 @@ static const struct irq_domain_ops mtk_msi_bottom_dom= ain_ops =3D { =20 static void mtk_intx_mask(struct irq_data *data) { - struct mtk_pcie_port *port =3D irq_data_get_irq_chip_data(data); + struct mtk_gen3_pcie *pcie =3D irq_data_get_irq_chip_data(data); unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&port->irq_lock, flags); - val =3D readl_relaxed(port->base + PCIE_INT_ENABLE_REG); + raw_spin_lock_irqsave(&pcie->irq_lock, flags); + val =3D readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); val &=3D ~BIT(data->hwirq + PCIE_INTX_SHIFT); - writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); - raw_spin_unlock_irqrestore(&port->irq_lock, flags); + writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); + raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); } =20 static void mtk_intx_unmask(struct irq_data *data) { - struct mtk_pcie_port *port =3D irq_data_get_irq_chip_data(data); + struct mtk_gen3_pcie *pcie =3D irq_data_get_irq_chip_data(data); unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&port->irq_lock, flags); - val =3D readl_relaxed(port->base + PCIE_INT_ENABLE_REG); + raw_spin_lock_irqsave(&pcie->irq_lock, flags); + val =3D readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); val |=3D BIT(data->hwirq + PCIE_INTX_SHIFT); - writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); - raw_spin_unlock_irqrestore(&port->irq_lock, flags); + writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); + raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); } =20 /** @@ -545,11 +545,11 @@ static void mtk_intx_unmask(struct irq_data *data) */ static void mtk_intx_eoi(struct irq_data *data) { - struct mtk_pcie_port *port =3D irq_data_get_irq_chip_data(data); + struct mtk_gen3_pcie *pcie =3D irq_data_get_irq_chip_data(data); unsigned long hwirq; =20 hwirq =3D data->hwirq + PCIE_INTX_SHIFT; - writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG); + writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG); } =20 static struct irq_chip mtk_intx_irq_chip =3D { @@ -573,13 +573,13 @@ static const struct irq_domain_ops intx_domain_ops = =3D { .map =3D mtk_pcie_intx_map, }; =20 -static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port) +static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; struct device_node *intc_node, *node =3D dev->of_node; int ret; =20 - raw_spin_lock_init(&port->irq_lock); + raw_spin_lock_init(&pcie->irq_lock); =20 /* Setup INTx */ intc_node =3D of_get_child_by_name(node, "interrupt-controller"); @@ -588,28 +588,28 @@ static int mtk_pcie_init_irq_domains(struct mtk_pcie_= port *port) return -ENODEV; } =20 - port->intx_domain =3D irq_domain_add_linear(intc_node, PCI_NUM_INTX, - &intx_domain_ops, port); - if (!port->intx_domain) { + pcie->intx_domain =3D irq_domain_add_linear(intc_node, PCI_NUM_INTX, + &intx_domain_ops, pcie); + if (!pcie->intx_domain) { dev_err(dev, "failed to create INTx IRQ domain\n"); return -ENODEV; } =20 /* Setup MSI */ - mutex_init(&port->lock); + mutex_init(&pcie->lock); =20 - port->msi_bottom_domain =3D irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, - &mtk_msi_bottom_domain_ops, port); - if (!port->msi_bottom_domain) { + pcie->msi_bottom_domain =3D irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, + &mtk_msi_bottom_domain_ops, pcie); + if (!pcie->msi_bottom_domain) { dev_err(dev, "failed to create MSI bottom domain\n"); ret =3D -ENODEV; goto err_msi_bottom_domain; } =20 - port->msi_domain =3D pci_msi_create_irq_domain(dev->fwnode, + pcie->msi_domain =3D pci_msi_create_irq_domain(dev->fwnode, &mtk_msi_domain_info, - port->msi_bottom_domain); - if (!port->msi_domain) { + pcie->msi_bottom_domain); + if (!pcie->msi_domain) { dev_err(dev, "failed to create MSI domain\n"); ret =3D -ENODEV; goto err_msi_domain; @@ -618,32 +618,32 @@ static int mtk_pcie_init_irq_domains(struct mtk_pcie_= port *port) return 0; =20 err_msi_domain: - irq_domain_remove(port->msi_bottom_domain); + irq_domain_remove(pcie->msi_bottom_domain); err_msi_bottom_domain: - irq_domain_remove(port->intx_domain); + irq_domain_remove(pcie->intx_domain); =20 return ret; } =20 -static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port) +static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) { - irq_set_chained_handler_and_data(port->irq, NULL, NULL); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); =20 - if (port->intx_domain) - irq_domain_remove(port->intx_domain); + if (pcie->intx_domain) + irq_domain_remove(pcie->intx_domain); =20 - if (port->msi_domain) - irq_domain_remove(port->msi_domain); + if (pcie->msi_domain) + irq_domain_remove(pcie->msi_domain); =20 - if (port->msi_bottom_domain) - irq_domain_remove(port->msi_bottom_domain); + if (pcie->msi_bottom_domain) + irq_domain_remove(pcie->msi_bottom_domain); =20 - irq_dispose_mapping(port->irq); + irq_dispose_mapping(pcie->irq); } =20 -static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx) +static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx) { - struct mtk_msi_set *msi_set =3D &port->msi_sets[set_idx]; + struct mtk_msi_set *msi_set =3D &pcie->msi_sets[set_idx]; unsigned long msi_enable, msi_status; irq_hw_number_t bit, hwirq; =20 @@ -658,59 +658,59 @@ static void mtk_pcie_msi_handler(struct mtk_pcie_port= *port, int set_idx) =20 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) { hwirq =3D bit + set_idx * PCIE_MSI_IRQS_PER_SET; - generic_handle_domain_irq(port->msi_bottom_domain, hwirq); + generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq); } } while (true); } =20 static void mtk_pcie_irq_handler(struct irq_desc *desc) { - struct mtk_pcie_port *port =3D irq_desc_get_handler_data(desc); + struct mtk_gen3_pcie *pcie =3D irq_desc_get_handler_data(desc); struct irq_chip *irqchip =3D irq_desc_get_chip(desc); unsigned long status; irq_hw_number_t irq_bit =3D PCIE_INTX_SHIFT; =20 chained_irq_enter(irqchip, desc); =20 - status =3D readl_relaxed(port->base + PCIE_INT_STATUS_REG); + status =3D readl_relaxed(pcie->base + PCIE_INT_STATUS_REG); for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX + PCIE_INTX_SHIFT) - generic_handle_domain_irq(port->intx_domain, + generic_handle_domain_irq(pcie->intx_domain, irq_bit - PCIE_INTX_SHIFT); =20 irq_bit =3D PCIE_MSI_SHIFT; for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + PCIE_MSI_SHIFT) { - mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT); + mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT); =20 - writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG); + writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG); } =20 chained_irq_exit(irqchip, desc); } =20 -static int mtk_pcie_setup_irq(struct mtk_pcie_port *port) +static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; struct platform_device *pdev =3D to_platform_device(dev); int err; =20 - err =3D mtk_pcie_init_irq_domains(port); + err =3D mtk_pcie_init_irq_domains(pcie); if (err) return err; =20 - port->irq =3D platform_get_irq(pdev, 0); - if (port->irq < 0) - return port->irq; + pcie->irq =3D platform_get_irq(pdev, 0); + if (pcie->irq < 0) + return pcie->irq; =20 - irq_set_chained_handler_and_data(port->irq, mtk_pcie_irq_handler, port); + irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie); =20 return 0; } =20 -static int mtk_pcie_parse_port(struct mtk_pcie_port *port) +static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; struct platform_device *pdev =3D to_platform_device(dev); struct resource *regs; int ret; @@ -718,77 +718,77 @@ static int mtk_pcie_parse_port(struct mtk_pcie_port *= port) regs =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); if (!regs) return -EINVAL; - port->base =3D devm_ioremap_resource(dev, regs); - if (IS_ERR(port->base)) { + pcie->base =3D devm_ioremap_resource(dev, regs); + if (IS_ERR(pcie->base)) { dev_err(dev, "failed to map register base\n"); - return PTR_ERR(port->base); + return PTR_ERR(pcie->base); } =20 - port->reg_base =3D regs->start; + pcie->reg_base =3D regs->start; =20 - port->phy_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy"); - if (IS_ERR(port->phy_reset)) { - ret =3D PTR_ERR(port->phy_reset); + pcie->phy_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy"); + if (IS_ERR(pcie->phy_reset)) { + ret =3D PTR_ERR(pcie->phy_reset); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "failed to get PHY reset\n"); =20 return ret; } =20 - port->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); - if (IS_ERR(port->mac_reset)) { - ret =3D PTR_ERR(port->mac_reset); + pcie->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); + if (IS_ERR(pcie->mac_reset)) { + ret =3D PTR_ERR(pcie->mac_reset); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "failed to get MAC reset\n"); =20 return ret; } =20 - port->phy =3D devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(port->phy)) { - ret =3D PTR_ERR(port->phy); + pcie->phy =3D devm_phy_optional_get(dev, "pcie-phy"); + if (IS_ERR(pcie->phy)) { + ret =3D PTR_ERR(pcie->phy); if (ret !=3D -EPROBE_DEFER) dev_err(dev, "failed to get PHY\n"); =20 return ret; } =20 - port->num_clks =3D devm_clk_bulk_get_all(dev, &port->clks); - if (port->num_clks < 0) { + pcie->num_clks =3D devm_clk_bulk_get_all(dev, &pcie->clks); + if (pcie->num_clks < 0) { dev_err(dev, "failed to get clocks\n"); - return port->num_clks; + return pcie->num_clks; } =20 return 0; } =20 -static int mtk_pcie_power_up(struct mtk_pcie_port *port) +static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; int err; =20 /* PHY power on and enable pipe clock */ - reset_control_deassert(port->phy_reset); + reset_control_deassert(pcie->phy_reset); =20 - err =3D phy_init(port->phy); + err =3D phy_init(pcie->phy); if (err) { dev_err(dev, "failed to initialize PHY\n"); goto err_phy_init; } =20 - err =3D phy_power_on(port->phy); + err =3D phy_power_on(pcie->phy); if (err) { dev_err(dev, "failed to power on PHY\n"); goto err_phy_on; } =20 /* MAC power on and enable transaction layer clocks */ - reset_control_deassert(port->mac_reset); + reset_control_deassert(pcie->mac_reset); =20 pm_runtime_enable(dev); pm_runtime_get_sync(dev); =20 - err =3D clk_bulk_prepare_enable(port->num_clks, port->clks); + err =3D clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to enable clocks\n"); goto err_clk_init; @@ -799,55 +799,55 @@ static int mtk_pcie_power_up(struct mtk_pcie_port *po= rt) err_clk_init: pm_runtime_put_sync(dev); pm_runtime_disable(dev); - reset_control_assert(port->mac_reset); - phy_power_off(port->phy); + reset_control_assert(pcie->mac_reset); + phy_power_off(pcie->phy); err_phy_on: - phy_exit(port->phy); + phy_exit(pcie->phy); err_phy_init: - reset_control_assert(port->phy_reset); + reset_control_assert(pcie->phy_reset); =20 return err; } =20 -static void mtk_pcie_power_down(struct mtk_pcie_port *port) +static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) { - clk_bulk_disable_unprepare(port->num_clks, port->clks); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); =20 - pm_runtime_put_sync(port->dev); - pm_runtime_disable(port->dev); - reset_control_assert(port->mac_reset); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); + reset_control_assert(pcie->mac_reset); =20 - phy_power_off(port->phy); - phy_exit(port->phy); - reset_control_assert(port->phy_reset); + phy_power_off(pcie->phy); + phy_exit(pcie->phy); + reset_control_assert(pcie->phy_reset); } =20 -static int mtk_pcie_setup(struct mtk_pcie_port *port) +static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) { int err; =20 - err =3D mtk_pcie_parse_port(port); + err =3D mtk_pcie_parse_port(pcie); if (err) return err; =20 /* Don't touch the hardware registers before power up */ - err =3D mtk_pcie_power_up(port); + err =3D mtk_pcie_power_up(pcie); if (err) return err; =20 /* Try link up */ - err =3D mtk_pcie_startup_port(port); + err =3D mtk_pcie_startup_port(pcie); if (err) goto err_setup; =20 - err =3D mtk_pcie_setup_irq(port); + err =3D mtk_pcie_setup_irq(pcie); if (err) goto err_setup; =20 return 0; =20 err_setup: - mtk_pcie_power_down(port); + mtk_pcie_power_down(pcie); =20 return err; } @@ -855,30 +855,30 @@ static int mtk_pcie_setup(struct mtk_pcie_port *port) static int mtk_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct mtk_pcie_port *port; + struct mtk_gen3_pcie *pcie; struct pci_host_bridge *host; int err; =20 - host =3D devm_pci_alloc_host_bridge(dev, sizeof(*port)); + host =3D devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!host) return -ENOMEM; =20 - port =3D pci_host_bridge_priv(host); + pcie =3D pci_host_bridge_priv(host); =20 - port->dev =3D dev; - platform_set_drvdata(pdev, port); + pcie->dev =3D dev; + platform_set_drvdata(pdev, pcie); =20 - err =3D mtk_pcie_setup(port); + err =3D mtk_pcie_setup(pcie); if (err) return err; =20 host->ops =3D &mtk_pcie_ops; - host->sysdata =3D port; + host->sysdata =3D pcie; =20 err =3D pci_host_probe(host); if (err) { - mtk_pcie_irq_teardown(port); - mtk_pcie_power_down(port); + mtk_pcie_irq_teardown(pcie); + mtk_pcie_power_down(pcie); return err; } =20 @@ -887,66 +887,66 @@ static int mtk_pcie_probe(struct platform_device *pde= v) =20 static int mtk_pcie_remove(struct platform_device *pdev) { - struct mtk_pcie_port *port =3D platform_get_drvdata(pdev); - struct pci_host_bridge *host =3D pci_host_bridge_from_priv(port); + struct mtk_gen3_pcie *pcie =3D platform_get_drvdata(pdev); + struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); =20 pci_lock_rescan_remove(); pci_stop_root_bus(host->bus); pci_remove_root_bus(host->bus); pci_unlock_rescan_remove(); =20 - mtk_pcie_irq_teardown(port); - mtk_pcie_power_down(port); + mtk_pcie_irq_teardown(pcie); + mtk_pcie_power_down(pcie); =20 return 0; } =20 -static void __maybe_unused mtk_pcie_irq_save(struct mtk_pcie_port *port) +static void __maybe_unused mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) { int i; =20 - raw_spin_lock(&port->irq_lock); + raw_spin_lock(&pcie->irq_lock); =20 - port->saved_irq_state =3D readl_relaxed(port->base + PCIE_INT_ENABLE_REG); + pcie->saved_irq_state =3D readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); =20 for (i =3D 0; i < PCIE_MSI_SET_NUM; i++) { - struct mtk_msi_set *msi_set =3D &port->msi_sets[i]; + struct mtk_msi_set *msi_set =3D &pcie->msi_sets[i]; =20 msi_set->saved_irq_state =3D readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); } =20 - raw_spin_unlock(&port->irq_lock); + raw_spin_unlock(&pcie->irq_lock); } =20 -static void __maybe_unused mtk_pcie_irq_restore(struct mtk_pcie_port *port) +static void __maybe_unused mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie) { int i; =20 - raw_spin_lock(&port->irq_lock); + raw_spin_lock(&pcie->irq_lock); =20 - writel_relaxed(port->saved_irq_state, port->base + PCIE_INT_ENABLE_REG); + writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG); =20 for (i =3D 0; i < PCIE_MSI_SET_NUM; i++) { - struct mtk_msi_set *msi_set =3D &port->msi_sets[i]; + struct mtk_msi_set *msi_set =3D &pcie->msi_sets[i]; =20 writel_relaxed(msi_set->saved_irq_state, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); } =20 - raw_spin_unlock(&port->irq_lock); + raw_spin_unlock(&pcie->irq_lock); } =20 -static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *por= t) +static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pci= e) { u32 val; =20 - val =3D readl_relaxed(port->base + PCIE_ICMD_PM_REG); + val =3D readl_relaxed(pcie->base + PCIE_ICMD_PM_REG); val |=3D PCIE_TURN_OFF_LINK; - writel_relaxed(val, port->base + PCIE_ICMD_PM_REG); + writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG); =20 /* Check the link is L2 */ - return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val, + return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val, (PCIE_LTSSM_STATE(val) =3D=3D PCIE_LTSSM_STATE_L2_IDLE), 20, 50 * USEC_PER_MSEC); @@ -954,46 +954,46 @@ static int __maybe_unused mtk_pcie_turn_off_link(stru= ct mtk_pcie_port *port) =20 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) { - struct mtk_pcie_port *port =3D dev_get_drvdata(dev); + struct mtk_gen3_pcie *pcie =3D dev_get_drvdata(dev); int err; u32 val; =20 /* Trigger link to L2 state */ - err =3D mtk_pcie_turn_off_link(port); + err =3D mtk_pcie_turn_off_link(pcie); if (err) { - dev_err(port->dev, "cannot enter L2 state\n"); + dev_err(pcie->dev, "cannot enter L2 state\n"); return err; } =20 /* Pull down the PERST# pin */ - val =3D readl_relaxed(port->base + PCIE_RST_CTRL_REG); + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); val |=3D PCIE_PE_RSTB; - writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); =20 - dev_dbg(port->dev, "entered L2 states successfully"); + dev_dbg(pcie->dev, "entered L2 states successfully"); =20 - mtk_pcie_irq_save(port); - mtk_pcie_power_down(port); + mtk_pcie_irq_save(pcie); + mtk_pcie_power_down(pcie); =20 return 0; } =20 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) { - struct mtk_pcie_port *port =3D dev_get_drvdata(dev); + struct mtk_gen3_pcie *pcie =3D dev_get_drvdata(dev); int err; =20 - err =3D mtk_pcie_power_up(port); + err =3D mtk_pcie_power_up(pcie); if (err) return err; =20 - err =3D mtk_pcie_startup_port(port); + err =3D mtk_pcie_startup_port(pcie); if (err) { - mtk_pcie_power_down(port); + mtk_pcie_power_down(pcie); return err; } =20 - mtk_pcie_irq_restore(port); + mtk_pcie_irq_restore(pcie); =20 return 0; } --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6173AC433F5 for ; Thu, 23 Dec 2021 01:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345974AbhLWBMR (ORCPT ); Wed, 22 Dec 2021 20:12:17 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57894 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345743AbhLWBLk (ORCPT ); Wed, 22 Dec 2021 20:11:40 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id F23C3CE1F05; Thu, 23 Dec 2021 01:11:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0A2A1C36AED; Thu, 23 Dec 2021 01:11:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221897; bh=0QYOsHS5wj8XlJwNRMAGvRqv6+NUOG9O0hN3WUXDp44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M6OSkDDvAFIANsXOdvzGFs8IpZScUztP7K7pwQlGe2BZ8KSI+LKIWBQRVnwmfFBiW gOqd0n32/EFKsepqNKAH6SAl2rkxrJIr45yUmb8Sy+lrg1uhvKujTD5ZdvIkStL/G/ 8F3wyDQnuhlrIKF9FbMj0LjKMYLCB/WaJPeyAPiopoVtboAZMhhGrvOIA1TmCsx1kP xBW8SSHMD4wyOwNVS2gUhj417U/JSpkPVJumEsVRKu+2fgZ18RZ2oRA5At1R0qJa8N t+kmEkG+KZVFKO6eJqhotVWLyQmuDPb+sxXNIBDRna8N796xuvMLNNbw7BYo/FqHMY Mkekpg0L6pjTw== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Daire McNamara Subject: [PATCH v2 15/23] PCI: microchip: Rename mc_port to mc_pcie Date: Wed, 22 Dec 2021 19:10:46 -0600 Message-Id: <20211223011054.1227810-16-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename struct mc_port to mc_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Bjorn Helgaas Cc: Daire McNamara --- drivers/pci/controller/pcie-microchip-host.c | 42 ++++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/con= troller/pcie-microchip-host.c index 329f930d17aa..29d8e81e4181 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -262,7 +262,7 @@ struct mc_msi { DECLARE_BITMAP(used, MC_NUM_MSI_IRQS); }; =20 -struct mc_port { +struct mc_pcie { void __iomem *axi_base_addr; struct device *dev; struct irq_domain *intx_domain; @@ -382,7 +382,7 @@ static struct { =20 static char poss_clks[][5] =3D { "fic0", "fic1", "fic2", "fic3" }; =20 -static void mc_pcie_enable_msi(struct mc_port *port, void __iomem *base) +static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base) { struct mc_msi *msi =3D &port->msi; u32 cap_offset =3D MC_MSI_CAP_CTRL_OFFSET; @@ -405,7 +405,7 @@ static void mc_pcie_enable_msi(struct mc_port *port, vo= id __iomem *base) =20 static void mc_handle_msi(struct irq_desc *desc) { - struct mc_port *port =3D irq_desc_get_handler_data(desc); + struct mc_pcie *port =3D irq_desc_get_handler_data(desc); struct device *dev =3D port->dev; struct mc_msi *msi =3D &port->msi; void __iomem *bridge_base_addr =3D @@ -428,7 +428,7 @@ static void mc_handle_msi(struct irq_desc *desc) =20 static void mc_msi_bottom_irq_ack(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; u32 bitpos =3D data->hwirq; @@ -443,7 +443,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) =20 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); phys_addr_t addr =3D port->msi.vector_phy; =20 msg->address_lo =3D lower_32_bits(addr); @@ -470,7 +470,7 @@ static struct irq_chip mc_msi_bottom_irq_chip =3D { static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int= virq, unsigned int nr_irqs, void *args) { - struct mc_port *port =3D domain->host_data; + struct mc_pcie *port =3D domain->host_data; struct mc_msi *msi =3D &port->msi; void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; @@ -503,7 +503,7 @@ static void mc_irq_msi_domain_free(struct irq_domain *d= omain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); - struct mc_port *port =3D irq_data_get_irq_chip_data(d); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(d); struct mc_msi *msi =3D &port->msi; =20 mutex_lock(&msi->lock); @@ -534,7 +534,7 @@ static struct msi_domain_info mc_msi_domain_info =3D { .chip =3D &mc_msi_irq_chip, }; =20 -static int mc_allocate_msi_domains(struct mc_port *port) +static int mc_allocate_msi_domains(struct mc_pcie *port) { struct device *dev =3D port->dev; struct fwnode_handle *fwnode =3D of_node_to_fwnode(dev->of_node); @@ -562,7 +562,7 @@ static int mc_allocate_msi_domains(struct mc_port *port) =20 static void mc_handle_intx(struct irq_desc *desc) { - struct mc_port *port =3D irq_desc_get_handler_data(desc); + struct mc_pcie *port =3D irq_desc_get_handler_data(desc); struct device *dev =3D port->dev; void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; @@ -585,7 +585,7 @@ static void mc_handle_intx(struct irq_desc *desc) =20 static void mc_ack_intx_irq(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; u32 mask =3D BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -595,7 +595,7 @@ static void mc_ack_intx_irq(struct irq_data *data) =20 static void mc_mask_intx_irq(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; unsigned long flags; @@ -611,7 +611,7 @@ static void mc_mask_intx_irq(struct irq_data *data) =20 static void mc_unmask_intx_irq(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; unsigned long flags; @@ -698,7 +698,7 @@ static u32 local_events(void __iomem *addr) return val; } =20 -static u32 get_events(struct mc_port *port) +static u32 get_events(struct mc_pcie *port) { void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; @@ -715,7 +715,7 @@ static u32 get_events(struct mc_port *port) =20 static irqreturn_t mc_event_handler(int irq, void *dev_id) { - struct mc_port *port =3D dev_id; + struct mc_pcie *port =3D dev_id; struct device *dev =3D port->dev; struct irq_data *data; =20 @@ -731,7 +731,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_= id) =20 static void mc_handle_event(struct irq_desc *desc) { - struct mc_port *port =3D irq_desc_get_handler_data(desc); + struct mc_pcie *port =3D irq_desc_get_handler_data(desc); unsigned long events; u32 bit; struct irq_chip *chip =3D irq_desc_get_chip(desc); @@ -748,7 +748,7 @@ static void mc_handle_event(struct irq_desc *desc) =20 static void mc_ack_event_irq(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); u32 event =3D data->hwirq; void __iomem *addr; u32 mask; @@ -763,7 +763,7 @@ static void mc_ack_event_irq(struct irq_data *data) =20 static void mc_mask_event_irq(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); u32 event =3D data->hwirq; void __iomem *addr; u32 mask; @@ -793,7 +793,7 @@ static void mc_mask_event_irq(struct irq_data *data) =20 static void mc_unmask_event_irq(struct irq_data *data) { - struct mc_port *port =3D irq_data_get_irq_chip_data(data); + struct mc_pcie *port =3D irq_data_get_irq_chip_data(data); u32 event =3D data->hwirq; void __iomem *addr; u32 mask; @@ -881,7 +881,7 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } =20 -static int mc_pcie_init_irq_domains(struct mc_port *port) +static int mc_pcie_init_irq_domains(struct mc_pcie *port) { struct device *dev =3D port->dev; struct device_node *node =3D dev->of_node; @@ -957,7 +957,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_b= ase_addr, u32 index, } =20 static int mc_pcie_setup_windows(struct platform_device *pdev, - struct mc_port *port) + struct mc_pcie *port) { void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; @@ -983,7 +983,7 @@ static int mc_platform_init(struct pci_config_window *c= fg) { struct device *dev =3D cfg->parent; struct platform_device *pdev =3D to_platform_device(dev); - struct mc_port *port; + struct mc_pcie *port; void __iomem *bridge_base_addr; void __iomem *ctrl_base_addr; int ret; --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05FE6C433F5 for ; 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d=kernel.org; s=k20201202; t=1640221899; bh=yk13MRO3FM7shpr7LfUCSVTd5vxWDh8QBr8p3FTIj6o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p86PrC/3UkOgCOBz8Trt8CCDybc9gaN8i4CKAT6mgCNoa4W5sP31nSCO2wtXdwrwC DG+7sw+rKG5902vb07CknOC1eT9zSe7T/nvDchjKfaZhnI8H99RnGZ+2tRz21zJv2D b1FpEnnC6HHCOv4ULeXMv77z7w2plKA533FSEiZctUCPwObd2OZ0zct7/igbYQt468 CHnLVPVoZ3uk9Qp+ogbAj7ktPnIWnuJsFIPb8lJn4RzFc46O04DgUcqjBqsWH6Vdmh GWIc5rlM+wYrN+mNobXcZ+YXkYfFA8biFX1dyMTJ0krQQbaJ/xoMPfkCEcG/6HTqh/ 1j1iEvCDxYU0Q== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Sergio Paracuellos , Matthias Brugger , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 16/23] PCI: mt7621: Make pci_ops static Date: Wed, 22 Dec 2021 19:10:47 -0600 Message-Id: <20211223011054.1227810-17-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas mt7621_pci_ops is used only in this file. Make it static. Signed-off-by: Bjorn Helgaas Cc: Sergio Paracuellos Cc: Matthias Brugger Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org --- drivers/pci/controller/pcie-mt7621.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/= pcie-mt7621.c index b60dfb45ef7b..4138c0e83513 100644 --- a/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c @@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus= *bus, return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); } =20 -struct pci_ops mt7621_pci_ops =3D { +static struct pci_ops mt7621_pci_ops =3D { .map_bus =3D mt7621_pcie_map_bus, .read =3D pci_generic_config_read, .write =3D pci_generic_config_write, --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 087BFC433F5 for ; Thu, 23 Dec 2021 01:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345998AbhLWBM1 (ORCPT ); Wed, 22 Dec 2021 20:12:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345754AbhLWBLm (ORCPT ); Wed, 22 Dec 2021 20:11:42 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF7B8C061746; Wed, 22 Dec 2021 17:11:41 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5FF4761C04; Thu, 23 Dec 2021 01:11:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9BB67C36AE8; Thu, 23 Dec 2021 01:11:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221900; bh=JEMd6rbvAJo5/E0VVbBCtxpY1OwkDouz6ExYkZiuVQU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hW0hvav0Nme8bJkjVlYbJCp4QsLxXxZtPVZphM7W3oFDqz+0Dwc7l6amya0PB4RNc 9hdMc9o3yDOCsEzZtWGM04BvH+GbSb1qS/dxZNFDYS/3SAIyfSPsY4jTq/9+KDq9ys lMG3FQwHF8i8YXznN9YQT7zJSjctduMwkNpRpbytk2IkJFk5qkcI38p2xxfMEyT7er owdv/I6d6/oReZn5tuXFKN4xP4GUzQ20V3QRO6CmhP9TIINcey+ZwuZJQPkt3Gm3cV g8R8kAHaMKKOz0R0/1H7iMiwdMSImmzIcU1ymEdE0QxsCiRIC7FqTjuF8tqPI736XI dHGJ2KzX33Byg== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Sergio Paracuellos , Matthias Brugger , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 17/23] PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_ Date: Wed, 22 Dec 2021 19:10:48 -0600 Message-Id: <20211223011054.1227810-18-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename mt7621_pci_* structs and functions to mt7621_pcie_* for consistency with the rest of the file. Signed-off-by: Bjorn Helgaas Cc: Sergio Paracuellos Cc: Matthias Brugger Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org --- drivers/pci/controller/pcie-mt7621.c | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/= pcie-mt7621.c index 4138c0e83513..b8fea7afdb1b 100644 --- a/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c @@ -93,8 +93,8 @@ struct mt7621_pcie_port { * reset lines are inverted. */ struct mt7621_pcie { - void __iomem *base; struct device *dev; + void __iomem *base; struct list_head ports; bool resets_inverted; }; @@ -129,7 +129,7 @@ static inline void pcie_port_write(struct mt7621_pcie_p= ort *port, writel_relaxed(val, port->base + reg); } =20 -static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int sl= ot, +static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int s= lot, unsigned int func, unsigned int where) { return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | @@ -140,7 +140,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus= *bus, unsigned int devfn, int where) { struct mt7621_pcie *pcie =3D bus->sysdata; - u32 address =3D mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + u32 address =3D mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where); =20 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); @@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus= *bus, return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); } =20 -static struct pci_ops mt7621_pci_ops =3D { +static struct pci_ops mt7621_pcie_ops =3D { .map_bus =3D mt7621_pcie_map_bus, .read =3D pci_generic_config_read, .write =3D pci_generic_config_write, @@ -156,7 +156,7 @@ static struct pci_ops mt7621_pci_ops =3D { =20 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { - u32 address =3D mt7621_pci_get_cfgaddr(0, dev, 0, reg); + u32 address =3D mt7621_pcie_get_cfgaddr(0, dev, 0, reg); =20 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); @@ -165,7 +165,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsign= ed int dev, u32 reg) static void write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) { - u32 address =3D mt7621_pci_get_cfgaddr(0, dev, 0, reg); + u32 address =3D mt7621_pcie_get_cfgaddr(0, dev, 0, reg); =20 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); @@ -505,16 +505,16 @@ static int mt7621_pcie_register_host(struct pci_host_= bridge *host) { struct mt7621_pcie *pcie =3D pci_host_bridge_priv(host); =20 - host->ops =3D &mt7621_pci_ops; + host->ops =3D &mt7621_pcie_ops; host->sysdata =3D pcie; return pci_host_probe(host); } =20 -static const struct soc_device_attribute mt7621_pci_quirks_match[] =3D { +static const struct soc_device_attribute mt7621_pcie_quirks_match[] =3D { { .soc_id =3D "mt7621", .revision =3D "E2" } }; =20 -static int mt7621_pci_probe(struct platform_device *pdev) +static int mt7621_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; const struct soc_device_attribute *attr; @@ -535,7 +535,7 @@ static int mt7621_pci_probe(struct platform_device *pde= v) platform_set_drvdata(pdev, pcie); INIT_LIST_HEAD(&pcie->ports); =20 - attr =3D soc_device_match(mt7621_pci_quirks_match); + attr =3D soc_device_match(mt7621_pcie_quirks_match); if (attr) pcie->resets_inverted =3D true; =20 @@ -572,7 +572,7 @@ static int mt7621_pci_probe(struct platform_device *pde= v) return err; } =20 -static int mt7621_pci_remove(struct platform_device *pdev) +static int mt7621_pcie_remove(struct platform_device *pdev) { struct mt7621_pcie *pcie =3D platform_get_drvdata(pdev); struct mt7621_pcie_port *port; @@ -583,18 +583,18 @@ static int mt7621_pci_remove(struct platform_device *= pdev) return 0; } =20 -static const struct of_device_id mt7621_pci_ids[] =3D { +static const struct of_device_id mt7621_pcie_ids[] =3D { { .compatible =3D "mediatek,mt7621-pci" }, {}, }; -MODULE_DEVICE_TABLE(of, mt7621_pci_ids); +MODULE_DEVICE_TABLE(of, mt7621_pcie_ids); =20 -static struct platform_driver mt7621_pci_driver =3D { - .probe =3D mt7621_pci_probe, - .remove =3D mt7621_pci_remove, +static struct platform_driver mt7621_pcie_driver =3D { + .probe =3D mt7621_pcie_probe, + .remove =3D mt7621_pcie_remove, .driver =3D { .name =3D "mt7621-pci", - .of_match_table =3D of_match_ptr(mt7621_pci_ids), + .of_match_table =3D of_match_ptr(mt7621_pcie_ids), }, }; -builtin_platform_driver(mt7621_pci_driver); +builtin_platform_driver(mt7621_pcie_driver); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9CB5C43217 for ; Thu, 23 Dec 2021 01:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346021AbhLWBMh (ORCPT ); Wed, 22 Dec 2021 20:12:37 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57946 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345786AbhLWBLq (ORCPT ); Wed, 22 Dec 2021 20:11:46 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 4859BCE1EFD; Thu, 23 Dec 2021 01:11:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53991C36AEB; Thu, 23 Dec 2021 01:11:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221902; bh=LFg3f+vxhc16OiGKNO9DQqvVW+Fx4PcKl6aq6BZtG3Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qHjAgDrE+WWnLnH/YfCSYiGYmFP3MNAlBQLYffSYSwj/hC0+g4Nac7mY7Ivkg1bvu i1hQ/QFtSXiJ48k7TmMab4HNFvF+oJVd0Ttq1d9hHc6sj8H6i0Ui1sNgAJNSz27xxO 1DVyZNiLxkrltMG1hq1AKGjYtFUnghQAy0Mq9OSvx+sjkxz2AnHeWkrMfxYOK3yn9L PbEDJQoxiu//L0qhhx8Vpu3wv1mG2tIOeVk1NRUz/qMOdtwiPvka92S5Xo0Jdj/NDz BbYbaZp7gQxazMfRVqveTm50lS3eupXkIkXCUIKMCS6FjEo7HrxksPhjs1JKcvaj16 Xa4Maj8K2MEWA== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 18/23] PCI: rcar-gen2: Rename rcar_pci_priv to rcar_pci Date: Wed, 22 Dec 2021 19:10:49 -0600 Message-Id: <20211223011054.1227810-19-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename struct rcar_pci_priv to rcar_pci to match the convention of _pci. No functional change intended. Signed-off-by: Bjorn Helgaas Cc: Marek Vasut Cc: Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org --- drivers/pci/controller/pci-rcar-gen2.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controlle= r/pci-rcar-gen2.c index afde4aa8f6dc..35804ea394fd 100644 --- a/drivers/pci/controller/pci-rcar-gen2.c +++ b/drivers/pci/controller/pci-rcar-gen2.c @@ -93,7 +93,7 @@ =20 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48) =20 -struct rcar_pci_priv { +struct rcar_pci { struct device *dev; void __iomem *reg; struct resource mem_res; @@ -105,7 +105,7 @@ struct rcar_pci_priv { static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int d= evfn, int where) { - struct rcar_pci_priv *priv =3D bus->sysdata; + struct rcar_pci *priv =3D bus->sysdata; int slot, val; =20 if (!pci_is_root_bus(bus) || PCI_FUNC(devfn)) @@ -132,7 +132,7 @@ static void __iomem *rcar_pci_cfg_base(struct pci_bus *= bus, unsigned int devfn, =20 static irqreturn_t rcar_pci_err_irq(int irq, void *pw) { - struct rcar_pci_priv *priv =3D pw; + struct rcar_pci *priv =3D pw; struct device *dev =3D priv->dev; u32 status =3D ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); =20 @@ -148,7 +148,7 @@ static irqreturn_t rcar_pci_err_irq(int irq, void *pw) return IRQ_NONE; } =20 -static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) +static void rcar_pci_setup_errirq(struct rcar_pci *priv) { struct device *dev =3D priv->dev; int ret; @@ -166,11 +166,11 @@ static void rcar_pci_setup_errirq(struct rcar_pci_pri= v *priv) iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG); } #else -static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { } +static inline void rcar_pci_setup_errirq(struct rcar_pci *priv) { } #endif =20 /* PCI host controller setup */ -static void rcar_pci_setup(struct rcar_pci_priv *priv) +static void rcar_pci_setup(struct rcar_pci *priv) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(priv); struct device *dev =3D priv->dev; @@ -279,7 +279,7 @@ static int rcar_pci_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct resource *cfg_res, *mem_res; - struct rcar_pci_priv *priv; + struct rcar_pci *priv; struct pci_host_bridge *bridge; void __iomem *reg; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A22FC433F5 for ; Thu, 23 Dec 2021 01:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345696AbhLWBMk (ORCPT ); Wed, 22 Dec 2021 20:12:40 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:57976 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345744AbhLWBLs (ORCPT ); Wed, 22 Dec 2021 20:11:48 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 26721CE1EFE; Thu, 23 Dec 2021 01:11:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BDD3C36AEA; Thu, 23 Dec 2021 01:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221904; bh=da32GrMecsebm7SuUZ0AlEjEM3Ft5LJCscRUp1dqa5k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lTtQcUxZ2HtjZgjoF/k2NFaPD6uIqgXcHu4AtA2ERmd9+DcDpo+/gSTfCZPVQOe0p qKTAXDnMDkn7PpWY9xjUY/TZnZhPNqUPCC4273XWJMIYcX2UoPzx9/gsekD69jblkx ZCqPxEWgsv7Gabwllx1jfwpBPNJTqzRbpn3s4b/fQTwAKTszqWHp6pnE/nuGBvMlsT xq/iYhKsL0NkCKurUHdsZr1IcpWUFLlrLOEf2d18OvuNLpZCA70o/RMXY5XFmIxnhe 4ygrQfLb7cKuBWLBPalG/i58EnDUdJ95MelaWzMEBpbHubLnNAhEE5buxrYhlK5U8O rrrxx+eEKoaLw== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org Subject: [PATCH v2 19/23] PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie Date: Wed, 22 Dec 2021 19:10:50 -0600 Message-Id: <20211223011054.1227810-20-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei Rename tegra_pcie_dw to tegra194_pcie to match the convention of _pcie. No functional change intended. [bhelgaas: rename functions similarly] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org --- drivers/pci/controller/dwc/pcie-tegra194.c | 222 ++++++++++----------- 1 file changed, 111 insertions(+), 111 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 904976913081..b1b5f836a806 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -245,7 +245,7 @@ static const unsigned int pcie_gen_freq[] =3D { GEN4_CORE_CLK_FREQ }; =20 -struct tegra_pcie_dw { +struct tegra194_pcie { struct device *dev; struct resource *appl_res; struct resource *dbi_res; @@ -289,22 +289,22 @@ struct tegra_pcie_dw { int ep_state; }; =20 -struct tegra_pcie_dw_of_data { +struct tegra194_pcie_of_data { enum dw_pcie_device_mode mode; }; =20 -static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) +static inline struct tegra194_pcie *to_tegra_pcie(struct dw_pcie *pci) { - return container_of(pci, struct tegra_pcie_dw, pci); + return container_of(pci, struct tegra194_pcie, pci); } =20 -static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, +static inline void appl_writel(struct tegra194_pcie *pcie, const u32 value, const u32 reg) { writel_relaxed(value, pcie->appl_base + reg); } =20 -static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) +static inline u32 appl_readl(struct tegra194_pcie *pcie, const u32 reg) { return readl_relaxed(pcie->appl_base + reg); } @@ -316,7 +316,7 @@ struct tegra_pcie_soc { static void apply_bad_link_workaround(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); u32 current_link_width; u16 val; =20 @@ -349,7 +349,7 @@ static void apply_bad_link_workaround(struct pcie_port = *pp) =20 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) { - struct tegra_pcie_dw *pcie =3D arg; + struct tegra194_pcie *pcie =3D arg; struct dw_pcie *pci =3D &pcie->pci; struct pcie_port *pp =3D &pci->pp; u32 val, tmp; @@ -420,7 +420,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) return IRQ_HANDLED; } =20 -static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie) +static void pex_ep_event_hot_rst_done(struct tegra194_pcie *pcie) { u32 val; =20 @@ -448,7 +448,7 @@ static void pex_ep_event_hot_rst_done(struct tegra_pcie= _dw *pcie) =20 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) { - struct tegra_pcie_dw *pcie =3D arg; + struct tegra194_pcie *pcie =3D arg; struct dw_pcie *pci =3D &pcie->pci; u32 val, speed; =20 @@ -494,7 +494,7 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, vo= id *arg) =20 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) { - struct tegra_pcie_dw *pcie =3D arg; + struct tegra194_pcie *pcie =3D arg; struct dw_pcie_ep *ep =3D &pcie->pci.ep; int spurious =3D 1; u32 status_l0, status_l1, link_status; @@ -537,7 +537,7 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void= *arg) return IRQ_HANDLED; } =20 -static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int w= here, +static int tegra194_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, int w= here, int size, u32 *val) { /* @@ -554,7 +554,7 @@ static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bu= s, u32 devfn, int where, return pci_generic_config_read(bus, devfn, where, size, val); } =20 -static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int w= here, +static int tegra194_pcie_wr_own_conf(struct pci_bus *bus, u32 devfn, int w= here, int size, u32 val) { /* @@ -571,8 +571,8 @@ static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bu= s, u32 devfn, int where, =20 static struct pci_ops tegra_pci_ops =3D { .map_bus =3D dw_pcie_own_conf_map_bus, - .read =3D tegra_pcie_dw_rd_own_conf, - .write =3D tegra_pcie_dw_wr_own_conf, + .read =3D tegra194_pcie_rd_own_conf, + .write =3D tegra194_pcie_wr_own_conf, }; =20 #if defined(CONFIG_PCIEASPM) @@ -594,7 +594,7 @@ static const u32 event_cntr_data_offset[] =3D { 0x1dc }; =20 -static void disable_aspm_l11(struct tegra_pcie_dw *pcie) +static void disable_aspm_l11(struct tegra194_pcie *pcie) { u32 val; =20 @@ -603,7 +603,7 @@ static void disable_aspm_l11(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); } =20 -static void disable_aspm_l12(struct tegra_pcie_dw *pcie) +static void disable_aspm_l12(struct tegra194_pcie *pcie) { u32 val; =20 @@ -612,7 +612,7 @@ static void disable_aspm_l12(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); } =20 -static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) +static inline u32 event_counter_prog(struct tegra194_pcie *pcie, u32 event) { u32 val; =20 @@ -629,7 +629,7 @@ static inline u32 event_counter_prog(struct tegra_pcie_= dw *pcie, u32 event) =20 static int aspm_state_cnt(struct seq_file *s, void *data) { - struct tegra_pcie_dw *pcie =3D (struct tegra_pcie_dw *) + struct tegra194_pcie *pcie =3D (struct tegra194_pcie *) dev_get_drvdata(s->private); u32 val; =20 @@ -660,7 +660,7 @@ static int aspm_state_cnt(struct seq_file *s, void *dat= a) return 0; } =20 -static void init_host_aspm(struct tegra_pcie_dw *pcie) +static void init_host_aspm(struct tegra194_pcie *pcie) { struct dw_pcie *pci =3D &pcie->pci; u32 val; @@ -688,22 +688,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); } =20 -static void init_debugfs(struct tegra_pcie_dw *pcie) +static void init_debugfs(struct tegra194_pcie *pcie) { debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, aspm_state_cnt); } #else -static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; } -static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; } -static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; } -static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; } +static inline void disable_aspm_l12(struct tegra194_pcie *pcie) { return; } +static inline void disable_aspm_l11(struct tegra194_pcie *pcie) { return; } +static inline void init_host_aspm(struct tegra194_pcie *pcie) { return; } +static inline void init_debugfs(struct tegra194_pcie *pcie) { return; } #endif =20 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); u32 val; u16 val_w; =20 @@ -741,7 +741,7 @@ static void tegra_pcie_enable_system_interrupts(struct = pcie_port *pp) static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); u32 val; =20 /* Enable legacy interrupt generation */ @@ -762,7 +762,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct = pcie_port *pp) static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); u32 val; =20 /* Enable MSI interrupt generation */ @@ -775,7 +775,7 @@ static void tegra_pcie_enable_msi_interrupts(struct pci= e_port *pp) static void tegra_pcie_enable_interrupts(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); =20 /* Clear interrupt statuses before enabling interrupts */ appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); @@ -800,7 +800,7 @@ static void tegra_pcie_enable_interrupts(struct pcie_po= rt *pp) tegra_pcie_enable_msi_interrupts(pp); } =20 -static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) +static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie) { struct dw_pcie *pci =3D &pcie->pci; u32 val, offset, i; @@ -853,10 +853,10 @@ static void config_gen3_gen4_eq_presets(struct tegra_= pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); } =20 -static int tegra_pcie_dw_host_init(struct pcie_port *pp) +static int tegra194_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); u32 val; =20 pp->bridge->ops =3D &tegra_pci_ops; @@ -914,10 +914,10 @@ static int tegra_pcie_dw_host_init(struct pcie_port *= pp) return 0; } =20 -static int tegra_pcie_dw_start_link(struct dw_pcie *pci) +static int tegra194_pcie_start_link(struct dw_pcie *pci) { u32 val, offset, speed, tmp; - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); struct pcie_port *pp =3D &pci->pp; bool retry =3D true; =20 @@ -982,7 +982,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) val &=3D ~PCI_DLF_EXCHANGE_ENABLE; dw_pcie_writel_dbi(pci, offset, val); =20 - tegra_pcie_dw_host_init(pp); + tegra194_pcie_host_init(pp); dw_pcie_setup_rc(pp); =20 retry =3D false; @@ -998,32 +998,32 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *p= ci) return 0; } =20 -static int tegra_pcie_dw_link_up(struct dw_pcie *pci) +static int tegra194_pcie_link_up(struct dw_pcie *pci) { - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); u32 val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); =20 return !!(val & PCI_EXP_LNKSTA_DLLLA); } =20 -static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) +static void tegra194_pcie_stop_link(struct dw_pcie *pci) { - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); =20 disable_irq(pcie->pex_rst_irq); } =20 static const struct dw_pcie_ops tegra_dw_pcie_ops =3D { - .link_up =3D tegra_pcie_dw_link_up, - .start_link =3D tegra_pcie_dw_start_link, - .stop_link =3D tegra_pcie_dw_stop_link, + .link_up =3D tegra194_pcie_link_up, + .start_link =3D tegra194_pcie_start_link, + .stop_link =3D tegra194_pcie_stop_link, }; =20 -static const struct dw_pcie_host_ops tegra_pcie_dw_host_ops =3D { - .host_init =3D tegra_pcie_dw_host_init, +static const struct dw_pcie_host_ops tegra194_pcie_host_ops =3D { + .host_init =3D tegra194_pcie_host_init, }; =20 -static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) +static void tegra_pcie_disable_phy(struct tegra194_pcie *pcie) { unsigned int phy_count =3D pcie->phy_count; =20 @@ -1033,7 +1033,7 @@ static void tegra_pcie_disable_phy(struct tegra_pcie_= dw *pcie) } } =20 -static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) +static int tegra_pcie_enable_phy(struct tegra194_pcie *pcie) { unsigned int i; int ret; @@ -1060,7 +1060,7 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw= *pcie) return ret; } =20 -static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) +static int tegra194_pcie_parse_dt(struct tegra194_pcie *pcie) { struct platform_device *pdev =3D to_platform_device(pcie->dev); struct device_node *np =3D pcie->dev->of_node; @@ -1156,7 +1156,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_d= w *pcie) return 0; } =20 -static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra194_pcie *pcie, bool enable) { struct mrq_uphy_response resp; @@ -1184,7 +1184,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegr= a_pcie_dw *pcie, return tegra_bpmp_transfer(pcie->bpmp, &msg); } =20 -static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, +static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie, bool enable) { struct mrq_uphy_response resp; @@ -1212,7 +1212,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra= _pcie_dw *pcie, return tegra_bpmp_transfer(pcie->bpmp, &msg); } =20 -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) +static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie) { struct pcie_port *pp =3D &pcie->pci.pp; struct pci_bus *child, *root_bus =3D NULL; @@ -1250,7 +1250,7 @@ static void tegra_pcie_downstream_dev_to_D0(struct te= gra_pcie_dw *pcie) } } =20 -static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) +static int tegra_pcie_get_slot_regulators(struct tegra194_pcie *pcie) { pcie->slot_ctl_3v3 =3D devm_regulator_get_optional(pcie->dev, "vpcie3v3"); if (IS_ERR(pcie->slot_ctl_3v3)) { @@ -1271,7 +1271,7 @@ static int tegra_pcie_get_slot_regulators(struct tegr= a_pcie_dw *pcie) return 0; } =20 -static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) +static int tegra_pcie_enable_slot_regulators(struct tegra194_pcie *pcie) { int ret; =20 @@ -1309,7 +1309,7 @@ static int tegra_pcie_enable_slot_regulators(struct t= egra_pcie_dw *pcie) return ret; } =20 -static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) +static void tegra_pcie_disable_slot_regulators(struct tegra194_pcie *pcie) { if (pcie->slot_ctl_12v) regulator_disable(pcie->slot_ctl_12v); @@ -1317,7 +1317,7 @@ static void tegra_pcie_disable_slot_regulators(struct= tegra_pcie_dw *pcie) regulator_disable(pcie->slot_ctl_3v3); } =20 -static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, +static int tegra_pcie_config_controller(struct tegra194_pcie *pcie, bool en_hw_hot_rst) { int ret; @@ -1414,7 +1414,7 @@ static int tegra_pcie_config_controller(struct tegra_= pcie_dw *pcie, return ret; } =20 -static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie) { int ret; =20 @@ -1442,7 +1442,7 @@ static void tegra_pcie_unconfig_controller(struct teg= ra_pcie_dw *pcie) pcie->cid, ret); } =20 -static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) +static int tegra_pcie_init_controller(struct tegra194_pcie *pcie) { struct dw_pcie *pci =3D &pcie->pci; struct pcie_port *pp =3D &pci->pp; @@ -1452,7 +1452,7 @@ static int tegra_pcie_init_controller(struct tegra_pc= ie_dw *pcie) if (ret < 0) return ret; =20 - pp->ops =3D &tegra_pcie_dw_host_ops; + pp->ops =3D &tegra194_pcie_host_ops; =20 ret =3D dw_pcie_host_init(pp); if (ret < 0) { @@ -1467,11 +1467,11 @@ static int tegra_pcie_init_controller(struct tegra_= pcie_dw *pcie) return ret; } =20 -static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) +static int tegra_pcie_try_link_l2(struct tegra194_pcie *pcie) { u32 val; =20 - if (!tegra_pcie_dw_link_up(&pcie->pci)) + if (!tegra194_pcie_link_up(&pcie->pci)) return 0; =20 val =3D appl_readl(pcie, APPL_RADM_STATUS); @@ -1483,12 +1483,12 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie= _dw *pcie) 1, PME_ACK_TIMEOUT); } =20 -static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) +static void tegra194_pcie_pme_turnoff(struct tegra194_pcie *pcie) { u32 data; int err; =20 - if (!tegra_pcie_dw_link_up(&pcie->pci)) { + if (!tegra194_pcie_link_up(&pcie->pci)) { dev_dbg(pcie->dev, "PCIe link is not up...!\n"); return; } @@ -1545,15 +1545,15 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_= pcie_dw *pcie) appl_writel(pcie, data, APPL_PINMUX); } =20 -static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_deinit_controller(struct tegra194_pcie *pcie) { tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); - tegra_pcie_dw_pme_turnoff(pcie); + tegra194_pcie_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); } =20 -static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) +static int tegra_pcie_config_rp(struct tegra194_pcie *pcie) { struct device *dev =3D pcie->dev; char *name; @@ -1580,7 +1580,7 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw = *pcie) goto fail_pm_get_sync; } =20 - pcie->link_state =3D tegra_pcie_dw_link_up(&pcie->pci); + pcie->link_state =3D tegra194_pcie_link_up(&pcie->pci); if (!pcie->link_state) { ret =3D -ENOMEDIUM; goto fail_host_init; @@ -1605,7 +1605,7 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw = *pcie) return ret; } =20 -static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) +static void pex_ep_event_pex_rst_assert(struct tegra194_pcie *pcie) { u32 val; int ret; @@ -1644,7 +1644,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra_= pcie_dw *pcie) dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); } =20 -static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) +static void pex_ep_event_pex_rst_deassert(struct tegra194_pcie *pcie) { struct dw_pcie *pci =3D &pcie->pci; struct dw_pcie_ep *ep =3D &pci->ep; @@ -1809,7 +1809,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegr= a_pcie_dw *pcie) =20 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) { - struct tegra_pcie_dw *pcie =3D arg; + struct tegra194_pcie *pcie =3D arg; =20 if (gpiod_get_value(pcie->pex_rst_gpiod)) pex_ep_event_pex_rst_assert(pcie); @@ -1819,7 +1819,7 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq,= void *arg) return IRQ_HANDLED; } =20 -static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 = irq) +static int tegra_pcie_ep_raise_legacy_irq(struct tegra194_pcie *pcie, u16 = irq) { /* Tegra194 supports only INTA */ if (irq > 1) @@ -1831,7 +1831,7 @@ static int tegra_pcie_ep_raise_legacy_irq(struct tegr= a_pcie_dw *pcie, u16 irq) return 0; } =20 -static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) +static int tegra_pcie_ep_raise_msi_irq(struct tegra194_pcie *pcie, u16 irq) { if (unlikely(irq > 31)) return -EINVAL; @@ -1841,7 +1841,7 @@ static int tegra_pcie_ep_raise_msi_irq(struct tegra_p= cie_dw *pcie, u16 irq) return 0; } =20 -static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 ir= q) +static int tegra_pcie_ep_raise_msix_irq(struct tegra194_pcie *pcie, u16 ir= q) { struct dw_pcie_ep *ep =3D &pcie->pci.ep; =20 @@ -1855,7 +1855,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep = *ep, u8 func_no, u16 interrupt_num) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct tegra194_pcie *pcie =3D to_tegra_pcie(pci); =20 switch (type) { case PCI_EPC_IRQ_LEGACY: @@ -1896,7 +1896,7 @@ static const struct dw_pcie_ep_ops pcie_ep_ops =3D { .get_features =3D tegra_pcie_ep_get_features, }; =20 -static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, +static int tegra_pcie_config_ep(struct tegra194_pcie *pcie, struct platform_device *pdev) { struct dw_pcie *pci =3D &pcie->pci; @@ -1957,12 +1957,12 @@ static int tegra_pcie_config_ep(struct tegra_pcie_d= w *pcie, return 0; } =20 -static int tegra_pcie_dw_probe(struct platform_device *pdev) +static int tegra194_pcie_probe(struct platform_device *pdev) { - const struct tegra_pcie_dw_of_data *data; + const struct tegra194_pcie_of_data *data; struct device *dev =3D &pdev->dev; struct resource *atu_dma_res; - struct tegra_pcie_dw *pcie; + struct tegra194_pcie *pcie; struct pcie_port *pp; struct dw_pcie *pci; struct phy **phys; @@ -1988,7 +1988,7 @@ static int tegra_pcie_dw_probe(struct platform_device= *pdev) pcie->dev =3D &pdev->dev; pcie->mode =3D (enum dw_pcie_device_mode)data->mode; =20 - ret =3D tegra_pcie_dw_parse_dt(pcie); + ret =3D tegra194_pcie_parse_dt(pcie); if (ret < 0) { const char *level =3D KERN_ERR; =20 @@ -2146,9 +2146,9 @@ static int tegra_pcie_dw_probe(struct platform_device= *pdev) return ret; } =20 -static int tegra_pcie_dw_remove(struct platform_device *pdev) +static int tegra194_pcie_remove(struct platform_device *pdev) { - struct tegra_pcie_dw *pcie =3D platform_get_drvdata(pdev); + struct tegra194_pcie *pcie =3D platform_get_drvdata(pdev); =20 if (!pcie->link_state) return 0; @@ -2164,9 +2164,9 @@ static int tegra_pcie_dw_remove(struct platform_devic= e *pdev) return 0; } =20 -static int tegra_pcie_dw_suspend_late(struct device *dev) +static int tegra194_pcie_suspend_late(struct device *dev) { - struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); + struct tegra194_pcie *pcie =3D dev_get_drvdata(dev); u32 val; =20 if (!pcie->link_state) @@ -2182,9 +2182,9 @@ static int tegra_pcie_dw_suspend_late(struct device *= dev) return 0; } =20 -static int tegra_pcie_dw_suspend_noirq(struct device *dev) +static int tegra194_pcie_suspend_noirq(struct device *dev) { - struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); + struct tegra194_pcie *pcie =3D dev_get_drvdata(dev); =20 if (!pcie->link_state) return 0; @@ -2193,15 +2193,15 @@ static int tegra_pcie_dw_suspend_noirq(struct devic= e *dev) pcie->msi_ctrl_int =3D dw_pcie_readl_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN); tegra_pcie_downstream_dev_to_D0(pcie); - tegra_pcie_dw_pme_turnoff(pcie); + tegra194_pcie_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); =20 return 0; } =20 -static int tegra_pcie_dw_resume_noirq(struct device *dev) +static int tegra194_pcie_resume_noirq(struct device *dev) { - struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); + struct tegra194_pcie *pcie =3D dev_get_drvdata(dev); int ret; =20 if (!pcie->link_state) @@ -2211,7 +2211,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *= dev) if (ret < 0) return ret; =20 - ret =3D tegra_pcie_dw_host_init(&pcie->pci.pp); + ret =3D tegra194_pcie_host_init(&pcie->pci.pp); if (ret < 0) { dev_err(dev, "Failed to init host: %d\n", ret); goto fail_host_init; @@ -2219,7 +2219,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *= dev) =20 dw_pcie_setup_rc(&pcie->pci.pp); =20 - ret =3D tegra_pcie_dw_start_link(&pcie->pci); + ret =3D tegra194_pcie_start_link(&pcie->pci); if (ret < 0) goto fail_host_init; =20 @@ -2234,9 +2234,9 @@ static int tegra_pcie_dw_resume_noirq(struct device *= dev) return ret; } =20 -static int tegra_pcie_dw_resume_early(struct device *dev) +static int tegra194_pcie_resume_early(struct device *dev) { - struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); + struct tegra194_pcie *pcie =3D dev_get_drvdata(dev); u32 val; =20 if (pcie->mode =3D=3D DW_PCIE_EP_TYPE) { @@ -2259,9 +2259,9 @@ static int tegra_pcie_dw_resume_early(struct device *= dev) return 0; } =20 -static void tegra_pcie_dw_shutdown(struct platform_device *pdev) +static void tegra194_pcie_shutdown(struct platform_device *pdev) { - struct tegra_pcie_dw *pcie =3D platform_get_drvdata(pdev); + struct tegra194_pcie *pcie =3D platform_get_drvdata(pdev); =20 if (!pcie->link_state) return; @@ -2273,50 +2273,50 @@ static void tegra_pcie_dw_shutdown(struct platform_= device *pdev) if (IS_ENABLED(CONFIG_PCI_MSI)) disable_irq(pcie->pci.pp.msi_irq); =20 - tegra_pcie_dw_pme_turnoff(pcie); + tegra194_pcie_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); } =20 -static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data =3D { +static const struct tegra194_pcie_of_data tegra194_pcie_rc_of_data =3D { .mode =3D DW_PCIE_RC_TYPE, }; =20 -static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data =3D { +static const struct tegra194_pcie_of_data tegra194_pcie_ep_of_data =3D { .mode =3D DW_PCIE_EP_TYPE, }; =20 -static const struct of_device_id tegra_pcie_dw_of_match[] =3D { +static const struct of_device_id tegra194_pcie_of_match[] =3D { { .compatible =3D "nvidia,tegra194-pcie", - .data =3D &tegra_pcie_dw_rc_of_data, + .data =3D &tegra194_pcie_rc_of_data, }, { .compatible =3D "nvidia,tegra194-pcie-ep", - .data =3D &tegra_pcie_dw_ep_of_data, + .data =3D &tegra194_pcie_ep_of_data, }, {}, }; =20 -static const struct dev_pm_ops tegra_pcie_dw_pm_ops =3D { - .suspend_late =3D tegra_pcie_dw_suspend_late, - .suspend_noirq =3D tegra_pcie_dw_suspend_noirq, - .resume_noirq =3D tegra_pcie_dw_resume_noirq, - .resume_early =3D tegra_pcie_dw_resume_early, +static const struct dev_pm_ops tegra194_pcie_pm_ops =3D { + .suspend_late =3D tegra194_pcie_suspend_late, + .suspend_noirq =3D tegra194_pcie_suspend_noirq, + .resume_noirq =3D tegra194_pcie_resume_noirq, + .resume_early =3D tegra194_pcie_resume_early, }; =20 -static struct platform_driver tegra_pcie_dw_driver =3D { - .probe =3D tegra_pcie_dw_probe, - .remove =3D tegra_pcie_dw_remove, - .shutdown =3D tegra_pcie_dw_shutdown, +static struct platform_driver tegra194_pcie_driver =3D { + .probe =3D tegra194_pcie_probe, + .remove =3D tegra194_pcie_remove, + .shutdown =3D tegra194_pcie_shutdown, .driver =3D { .name =3D "tegra194-pcie", - .pm =3D &tegra_pcie_dw_pm_ops, - .of_match_table =3D tegra_pcie_dw_of_match, + .pm =3D &tegra194_pcie_pm_ops, + .of_match_table =3D tegra194_pcie_of_match, }, }; -module_platform_driver(tegra_pcie_dw_driver); +module_platform_driver(tegra194_pcie_driver); =20 -MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match); +MODULE_DEVICE_TABLE(of, tegra194_pcie_of_match); =20 MODULE_AUTHOR("Vidya Sagar "); MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 518B3C43219 for ; Thu, 23 Dec 2021 01:12:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346025AbhLWBMi (ORCPT ); Wed, 22 Dec 2021 20:12:38 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:49958 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345738AbhLWBLr (ORCPT ); Wed, 22 Dec 2021 20:11:47 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DD4DF61C2A; Thu, 23 Dec 2021 01:11:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0343EC36AE8; Thu, 23 Dec 2021 01:11:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221906; bh=M3t+lYIXIkPfI+UwADZM/xjt7JNOzevFEnzomazcJes=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HhYwZhS0dAU9IsRl37aORWZLva/2wElYTog1Pve5HDNyEL+5uHvmiEUIVwHE2A8Qf Nd1EAcymov+zksjZz1p7Ymy9Zvx9ghLBqI0Db1nqwkLWgplE9OBeY9ibDikZsEq3tT 4htCDAeuX+/R1STiQJC5QlUmHUHXSLLIRPaQhCgd6DS7xzzV8KvfCZPv4mN+SEZiWX cHu+8bV03v5+6n57WhWckuQ7y9PtTgDGoxu1nibLAnrnAUvSVt25S0A3pD7U7I1q2u E6u5e4v+QXXFV/OnTGiAMdK0EWqX2oZJndvXIB2IiZwJJxNe2/6avUA9ih9rrDonA2 8vfwMw55obHbQ== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Kunihiko Hayashi , Masami Hiramatsu , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 20/23] PCI: uniphier: Rename uniphier_pcie_priv to uniphier_pcie Date: Wed, 22 Dec 2021 19:10:51 -0600 Message-Id: <20211223011054.1227810-21-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei Rename struct uniphier_pcie_priv to uniphier_pcie to match the convention of _pcie. No functional change intended. [bhelgaas: drop extraneous uniphier_pcie_irq_ack() from patch] Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Kunihiko Hayashi Cc: Masami Hiramatsu Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/dwc/pcie-uniphier.c | 147 +++++++++++---------- 1 file changed, 74 insertions(+), 73 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/contr= oller/dwc/pcie-uniphier.c index d05be942956e..b45ac3754242 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -61,9 +61,9 @@ #define PCL_RDLH_LINK_UP BIT(1) #define PCL_XMLH_LINK_UP BIT(0) =20 -struct uniphier_pcie_priv { - void __iomem *base; +struct uniphier_pcie { struct dw_pcie pci; + void __iomem *base; struct clk *clk; struct reset_control *rst; struct phy *phy; @@ -72,62 +72,62 @@ struct uniphier_pcie_priv { =20 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) =20 -static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv, +static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, bool enable) { u32 val; =20 - val =3D readl(priv->base + PCL_APP_READY_CTRL); + val =3D readl(pcie->base + PCL_APP_READY_CTRL); if (enable) val |=3D PCL_APP_LTSSM_ENABLE; else val &=3D ~PCL_APP_LTSSM_ENABLE; - writel(val, priv->base + PCL_APP_READY_CTRL); + writel(val, pcie->base + PCL_APP_READY_CTRL); } =20 -static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv) +static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) { u32 val; =20 /* set RC MODE */ - val =3D readl(priv->base + PCL_MODE); + val =3D readl(pcie->base + PCL_MODE); val |=3D PCL_MODE_REGEN; val &=3D ~PCL_MODE_REGVAL; - writel(val, priv->base + PCL_MODE); + writel(val, pcie->base + PCL_MODE); =20 /* use auxiliary power detection */ - val =3D readl(priv->base + PCL_APP_PM0); + val =3D readl(pcie->base + PCL_APP_PM0); val |=3D PCL_SYS_AUX_PWR_DET; - writel(val, priv->base + PCL_APP_PM0); + writel(val, pcie->base + PCL_APP_PM0); =20 /* assert PERST# */ - val =3D readl(priv->base + PCL_PINCTRL0); + val =3D readl(pcie->base + PCL_PINCTRL0); val &=3D ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL | PCL_PERST_PLDN_REGVAL); val |=3D PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN | PCL_PERST_PLDN_REGEN; - writel(val, priv->base + PCL_PINCTRL0); + writel(val, pcie->base + PCL_PINCTRL0); =20 - uniphier_pcie_ltssm_enable(priv, false); + uniphier_pcie_ltssm_enable(pcie, false); =20 usleep_range(100000, 200000); =20 /* deassert PERST# */ - val =3D readl(priv->base + PCL_PINCTRL0); + val =3D readl(pcie->base + PCL_PINCTRL0); val |=3D PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN; - writel(val, priv->base + PCL_PINCTRL0); + writel(val, pcie->base + PCL_PINCTRL0); } =20 -static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv) +static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie) { u32 status; int ret; =20 /* wait PIPE clock */ - ret =3D readl_poll_timeout(priv->base + PCL_PIPEMON, status, + ret =3D readl_poll_timeout(pcie->base + PCL_PIPEMON, status, status & PCL_PCLK_ALIVE, 100000, 1000000); if (ret) { - dev_err(priv->pci.dev, + dev_err(pcie->pci.dev, "Failed to initialize controller in RC mode\n"); return ret; } @@ -137,10 +137,10 @@ static int uniphier_pcie_wait_rc(struct uniphier_pcie= _priv *priv) =20 static int uniphier_pcie_link_up(struct dw_pcie *pci) { - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); u32 val, mask; =20 - val =3D readl(priv->base + PCL_STATUS_LINK); + val =3D readl(pcie->base + PCL_STATUS_LINK); mask =3D PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP; =20 return (val & mask) =3D=3D mask; @@ -148,39 +148,40 @@ static int uniphier_pcie_link_up(struct dw_pcie *pci) =20 static int uniphier_pcie_start_link(struct dw_pcie *pci) { - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); =20 - uniphier_pcie_ltssm_enable(priv, true); + uniphier_pcie_ltssm_enable(pcie, true); =20 return 0; } =20 static void uniphier_pcie_stop_link(struct dw_pcie *pci) { - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); =20 - uniphier_pcie_ltssm_enable(priv, false); + uniphier_pcie_ltssm_enable(pcie, false); } =20 -static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) +static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie) { - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); - writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); + writel(PCL_RCV_INT_ALL_ENABLE, pcie->base + PCL_RCV_INT); + writel(PCL_RCV_INTX_ALL_ENABLE, pcie->base + PCL_RCV_INTX); } =20 + static void uniphier_pcie_irq_mask(struct irq_data *d) { struct pcie_port *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); unsigned long flags; u32 val; =20 raw_spin_lock_irqsave(&pp->lock, flags); =20 - val =3D readl(priv->base + PCL_RCV_INTX); + val =3D readl(pcie->base + PCL_RCV_INTX); val |=3D BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); - writel(val, priv->base + PCL_RCV_INTX); + writel(val, pcie->base + PCL_RCV_INTX); =20 raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -189,15 +190,15 @@ static void uniphier_pcie_irq_unmask(struct irq_data = *d) { struct pcie_port *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); unsigned long flags; u32 val; =20 raw_spin_lock_irqsave(&pp->lock, flags); =20 - val =3D readl(priv->base + PCL_RCV_INTX); + val =3D readl(pcie->base + PCL_RCV_INTX); val &=3D ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); - writel(val, priv->base + PCL_RCV_INTX); + writel(val, pcie->base + PCL_RCV_INTX); =20 raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -226,13 +227,13 @@ static void uniphier_pcie_irq_handler(struct irq_desc= *desc) { struct pcie_port *pp =3D irq_desc_get_handler_data(desc); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); struct irq_chip *chip =3D irq_desc_get_chip(desc); unsigned long reg; u32 val, bit; =20 /* INT for debug */ - val =3D readl(priv->base + PCL_RCV_INT); + val =3D readl(pcie->base + PCL_RCV_INT); =20 if (val & PCL_CFG_BW_MGT_STATUS) dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); @@ -243,16 +244,16 @@ static void uniphier_pcie_irq_handler(struct irq_desc= *desc) if (val & PCL_CFG_PME_MSI_STATUS) dev_dbg(pci->dev, "PME Interrupt\n"); =20 - writel(val, priv->base + PCL_RCV_INT); + writel(val, pcie->base + PCL_RCV_INT); =20 /* INTx */ chained_irq_enter(chip, desc); =20 - val =3D readl(priv->base + PCL_RCV_INTX); + val =3D readl(pcie->base + PCL_RCV_INTX); reg =3D FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val); =20 for_each_set_bit(bit, ®, PCI_NUM_INTX) - generic_handle_domain_irq(priv->legacy_irq_domain, bit); + generic_handle_domain_irq(pcie->legacy_irq_domain, bit); =20 chained_irq_exit(chip, desc); } @@ -260,7 +261,7 @@ static void uniphier_pcie_irq_handler(struct irq_desc *= desc) static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); struct device_node *np =3D pci->dev->of_node; struct device_node *np_intc; int ret =3D 0; @@ -278,9 +279,9 @@ static int uniphier_pcie_config_legacy_irq(struct pcie_= port *pp) goto out_put_node; } =20 - priv->legacy_irq_domain =3D irq_domain_add_linear(np_intc, PCI_NUM_INTX, + pcie->legacy_irq_domain =3D irq_domain_add_linear(np_intc, PCI_NUM_INTX, &uniphier_intx_domain_ops, pp); - if (!priv->legacy_irq_domain) { + if (!pcie->legacy_irq_domain) { dev_err(pci->dev, "Failed to get INTx domain\n"); ret =3D -ENODEV; goto out_put_node; @@ -297,14 +298,14 @@ static int uniphier_pcie_config_legacy_irq(struct pci= e_port *pp) static int uniphier_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct uniphier_pcie_priv *priv =3D to_uniphier_pcie(pci); + struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); int ret; =20 ret =3D uniphier_pcie_config_legacy_irq(pp); if (ret) return ret; =20 - uniphier_pcie_irq_enable(priv); + uniphier_pcie_irq_enable(pcie); =20 return 0; } @@ -313,36 +314,36 @@ static const struct dw_pcie_host_ops uniphier_pcie_ho= st_ops =3D { .host_init =3D uniphier_pcie_host_init, }; =20 -static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv) +static int uniphier_pcie_host_enable(struct uniphier_pcie *pcie) { int ret; =20 - ret =3D clk_prepare_enable(priv->clk); + ret =3D clk_prepare_enable(pcie->clk); if (ret) return ret; =20 - ret =3D reset_control_deassert(priv->rst); + ret =3D reset_control_deassert(pcie->rst); if (ret) goto out_clk_disable; =20 - uniphier_pcie_init_rc(priv); + uniphier_pcie_init_rc(pcie); =20 - ret =3D phy_init(priv->phy); + ret =3D phy_init(pcie->phy); if (ret) goto out_rst_assert; =20 - ret =3D uniphier_pcie_wait_rc(priv); + ret =3D uniphier_pcie_wait_rc(pcie); if (ret) goto out_phy_exit; =20 return 0; =20 out_phy_exit: - phy_exit(priv->phy); + phy_exit(pcie->phy); out_rst_assert: - reset_control_assert(priv->rst); + reset_control_assert(pcie->rst); out_clk_disable: - clk_disable_unprepare(priv->clk); + clk_disable_unprepare(pcie->clk); =20 return ret; } @@ -356,41 +357,41 @@ static const struct dw_pcie_ops dw_pcie_ops =3D { static int uniphier_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct uniphier_pcie_priv *priv; + struct uniphier_pcie *pcie; int ret; =20 - priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) return -ENOMEM; =20 - priv->pci.dev =3D dev; - priv->pci.ops =3D &dw_pcie_ops; + pcie->pci.dev =3D dev; + pcie->pci.ops =3D &dw_pcie_ops; =20 - priv->base =3D devm_platform_ioremap_resource_byname(pdev, "link"); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + pcie->base =3D devm_platform_ioremap_resource_byname(pdev, "link"); + if (IS_ERR(pcie->base)) + return PTR_ERR(pcie->base); =20 - priv->clk =3D devm_clk_get(dev, NULL); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); + pcie->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk)) + return PTR_ERR(pcie->clk); =20 - priv->rst =3D devm_reset_control_get_shared(dev, NULL); - if (IS_ERR(priv->rst)) - return PTR_ERR(priv->rst); + pcie->rst =3D devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(pcie->rst)) + return PTR_ERR(pcie->rst); =20 - priv->phy =3D devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(priv->phy)) - return PTR_ERR(priv->phy); + pcie->phy =3D devm_phy_optional_get(dev, "pcie-phy"); + if (IS_ERR(pcie->phy)) + return PTR_ERR(pcie->phy); =20 - platform_set_drvdata(pdev, priv); + platform_set_drvdata(pdev, pcie); =20 - ret =3D uniphier_pcie_host_enable(priv); + ret =3D uniphier_pcie_host_enable(pcie); if (ret) return ret; =20 - priv->pci.pp.ops =3D &uniphier_pcie_host_ops; + pcie->pci.pp.ops =3D &uniphier_pcie_host_ops; =20 - return dw_pcie_host_init(&priv->pci.pp); + return dw_pcie_host_init(&pcie->pci.pp); } =20 static const struct of_device_id uniphier_pcie_match[] =3D { --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34C9FC4332F for ; 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d=kernel.org; s=k20201202; t=1640221908; bh=nS4jZXintt2/E8Abk/nP0Fk/9b5PD0tHeYSlLq6cHOI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MUvff4NOpoMHiKn9owcavbgXndI9pASWDCl9B285UyXHqdoSbo6qPW4Z9MsyvTiDQ bd9kL/nfDFHosHieTg58wCePz9FGJLioHc7HEq2GWSAH8fYV51dTu7hottYqZwN8KT R/kzDUomx0ZPFiYpYN7Gl4tKrYbcGYnwMU8YbkN9usgJVgXzDvC6SpGEfkQMtzfQJJ okMa7epMeY2E3jrtkKcQkZyCPwEBhu4/GK3S5Xcbvv420dz90ctsy6rM0s8D5cp8SQ PHWM6+wGzZXKdBzA37/t+AGbsI/qYA/1h96nSJRP/pl/kwrcoS2DD4Ed9m43/9RkJW v3c7WSEl6j2CA== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Toan Le , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 21/23] PCI: xgene: Rename xgene_pcie_port to xgene_pcie Date: Wed, 22 Dec 2021 19:10:52 -0600 Message-Id: <20211223011054.1227810-22-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei Rename struct xgene_pcie_port to xgene_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Toan Le Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/pci-xgene.c | 46 +++++++++++++++--------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pc= i-xgene.c index 56d0d50338c8..ba11f369a1c9 100644 --- a/drivers/pci/controller/pci-xgene.c +++ b/drivers/pci/controller/pci-xgene.c @@ -60,7 +60,7 @@ #define XGENE_PCIE_IP_VER_2 2 =20 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_P= CI_QUIRKS)) -struct xgene_pcie_port { +struct xgene_pcie { struct device_node *node; struct device *dev; struct clk *clk; @@ -71,12 +71,12 @@ struct xgene_pcie_port { u32 version; }; =20 -static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg) +static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg) { return readl(port->csr_base + reg); } =20 -static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 v= al) +static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val) { writel(val, port->csr_base + reg); } @@ -86,15 +86,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags) return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; } =20 -static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus) +static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus) { struct pci_config_window *cfg; =20 if (acpi_disabled) - return (struct xgene_pcie_port *)(bus->sysdata); + return (struct xgene_pcie *)(bus->sysdata); =20 cfg =3D bus->sysdata; - return (struct xgene_pcie_port *)(cfg->priv); + return (struct xgene_pcie *)(cfg->priv); } =20 /* @@ -103,7 +103,7 @@ static inline struct xgene_pcie_port *pcie_bus_to_port(= struct pci_bus *bus) */ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) { - struct xgene_pcie_port *port =3D pcie_bus_to_port(bus); + struct xgene_pcie *port =3D pcie_bus_to_port(bus); =20 if (bus->number >=3D (bus->primary + 1)) return port->cfg_base + AXI_EP_CFG_ACCESS; @@ -117,7 +117,7 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci= _bus *bus) */ static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) { - struct xgene_pcie_port *port =3D pcie_bus_to_port(bus); + struct xgene_pcie *port =3D pcie_bus_to_port(bus); unsigned int b, d, f; u32 rtdid_val =3D 0; =20 @@ -164,7 +164,7 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus = *bus, unsigned int devfn, static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devf= n, int where, int size, u32 *val) { - struct xgene_pcie_port *port =3D pcie_bus_to_port(bus); + struct xgene_pcie *port =3D pcie_bus_to_port(bus); =20 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=3D PCIBIOS_SUCCESSFUL) @@ -227,7 +227,7 @@ static int xgene_pcie_ecam_init(struct pci_config_windo= w *cfg, u32 ipversion) { struct device *dev =3D cfg->parent; struct acpi_device *adev =3D to_acpi_device(dev); - struct xgene_pcie_port *port; + struct xgene_pcie *port; struct resource csr; int ret; =20 @@ -281,7 +281,7 @@ const struct pci_ecam_ops xgene_v2_pcie_ecam_ops =3D { #endif =20 #if defined(CONFIG_PCI_XGENE) -static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, +static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr, u32 flags, u64 size) { u64 mask =3D (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; @@ -307,7 +307,7 @@ static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_por= t *port, u32 addr, return mask; } =20 -static void xgene_pcie_linkup(struct xgene_pcie_port *port, +static void xgene_pcie_linkup(struct xgene_pcie *port, u32 *lanes, u32 *speed) { u32 val32; @@ -322,7 +322,7 @@ static void xgene_pcie_linkup(struct xgene_pcie_port *p= ort, } } =20 -static int xgene_pcie_init_port(struct xgene_pcie_port *port) +static int xgene_pcie_init_port(struct xgene_pcie *port) { struct device *dev =3D port->dev; int rc; @@ -342,7 +342,7 @@ static int xgene_pcie_init_port(struct xgene_pcie_port = *port) return 0; } =20 -static int xgene_pcie_map_reg(struct xgene_pcie_port *port, +static int xgene_pcie_map_reg(struct xgene_pcie *port, struct platform_device *pdev) { struct device *dev =3D port->dev; @@ -362,7 +362,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *p= ort, return 0; } =20 -static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, +static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port, struct resource *res, u32 offset, u64 cpu_addr, u64 pci_addr) { @@ -394,7 +394,7 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_p= ort *port, xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); } =20 -static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port) +static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port) { u64 addr =3D port->cfg_addr; =20 @@ -403,7 +403,7 @@ static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_= port *port) xgene_pcie_writel(port, CFGCTL, EN_REG); } =20 -static int xgene_pcie_map_ranges(struct xgene_pcie_port *port) +static int xgene_pcie_map_ranges(struct xgene_pcie *port) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(port); struct resource_entry *window; @@ -444,7 +444,7 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port= *port) return 0; } =20 -static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_re= g, +static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg, u64 pim, u64 size) { xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); @@ -478,7 +478,7 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u6= 4 size) return -EINVAL; } =20 -static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, +static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port, struct resource_entry *entry, u8 *ib_reg_mask) { @@ -529,7 +529,7 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_p= ort *port, xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); } =20 -static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) +static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(port); struct resource_entry *entry; @@ -542,7 +542,7 @@ static int xgene_pcie_parse_map_dma_ranges(struct xgene= _pcie_port *port) } =20 /* clear BAR configuration which was done by firmware */ -static void xgene_pcie_clear_config(struct xgene_pcie_port *port) +static void xgene_pcie_clear_config(struct xgene_pcie *port) { int i; =20 @@ -550,7 +550,7 @@ static void xgene_pcie_clear_config(struct xgene_pcie_p= ort *port) xgene_pcie_writel(port, i, 0); } =20 -static int xgene_pcie_setup(struct xgene_pcie_port *port) +static int xgene_pcie_setup(struct xgene_pcie *port) { struct device *dev =3D port->dev; u32 val, lanes =3D 0, speed =3D 0; @@ -588,7 +588,7 @@ static int xgene_pcie_probe(struct platform_device *pde= v) { struct device *dev =3D &pdev->dev; struct device_node *dn =3D dev->of_node; - struct xgene_pcie_port *port; + struct xgene_pcie *port; struct pci_host_bridge *bridge; int ret; =20 --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 550DCC433F5 for ; Thu, 23 Dec 2021 01:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345954AbhLWBNC (ORCPT ); Wed, 22 Dec 2021 20:13:02 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:50010 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345794AbhLWBLu (ORCPT ); Wed, 22 Dec 2021 20:11:50 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7A89961C1E; Thu, 23 Dec 2021 01:11:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 98242C36AEB; Thu, 23 Dec 2021 01:11:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640221909; bh=9UKJBUxEZvoZo/e15jpwBlXdUhaenan804n2bqh7j4E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NoBsavntB5D3fKWBYETvLiz82gYYnkMuytuRu/vEhVQKQtZPLIuvEVso7db5+NgLQ WPRybHSbXsR5A1+5uzlRueT+Qmheghwl/JRdb3JyYWA5C4o5oIeQV1vgZBCzKaLR74 h/DFD56xIM3nO/haaPXz3DXLHhK9ONbP/4XXQ8/kNQwr+yC3Q0TaGQJWsL3RDW/d52 3ySdJAy+8DdV1C5/DXE/N6z2ZD8+ClIyFyo4rJHE+Uh6euH9Phi1vFm1Dj0frk2foy JE7DhF/l4+MFfMfiYqbhnKwn6H9A1pgp9X0GxrtnO5D575WV5ZBIzDbDoXQ+dgUIhL vKUEPzF7L1gcA== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Michal Simek , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 22/23] PCI: xilinx: Rename xilinx_pcie_port to xilinx_pcie Date: Wed, 22 Dec 2021 19:10:53 -0600 Message-Id: <20211223011054.1227810-23-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fan Fei Rename struct xilinx_pcie_port to xilinx_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Fan Fei Signed-off-by: Bjorn Helgaas Cc: Michal Simek Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/pcie-xilinx.c | 158 +++++++++++++-------------- 1 file changed, 79 insertions(+), 79 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/= pcie-xilinx.c index aa9bdcebc838..cb6e9f7b0152 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -91,18 +91,18 @@ #define XILINX_NUM_MSI_IRQS 128 =20 /** - * struct xilinx_pcie_port - PCIe port information - * @reg_base: IO Mapped Register Base + * struct xilinx_pcie - PCIe port information * @dev: Device pointer + * @reg_base: IO Mapped Register Base * @msi_map: Bitmap of allocated MSIs * @map_lock: Mutex protecting the MSI allocation * @msi_domain: MSI IRQ domain pointer * @leg_domain: Legacy IRQ domain pointer * @resources: Bus Resources */ -struct xilinx_pcie_port { - void __iomem *reg_base; +struct xilinx_pcie { struct device *dev; + void __iomem *reg_base; unsigned long msi_map[BITS_TO_LONGS(XILINX_NUM_MSI_IRQS)]; struct mutex map_lock; struct irq_domain *msi_domain; @@ -110,35 +110,35 @@ struct xilinx_pcie_port { struct list_head resources; }; =20 -static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg) +static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) { - return readl(port->reg_base + reg); + return readl(pcie->reg_base + reg); } =20 -static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 = reg) +static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) { - writel(val, port->reg_base + reg); + writel(val, pcie->reg_base + reg); } =20 -static inline bool xilinx_pcie_link_up(struct xilinx_pcie_port *port) +static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) { - return (pcie_read(port, XILINX_PCIE_REG_PSCR) & + return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0; } =20 /** * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts - * @port: PCIe port information + * @pcie: PCIe port information */ -static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port) +static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie) { - struct device *dev =3D port->dev; - unsigned long val =3D pcie_read(port, XILINX_PCIE_REG_RPEFR); + struct device *dev =3D pcie->dev; + unsigned long val =3D pcie_read(pcie, XILINX_PCIE_REG_RPEFR); =20 if (val & XILINX_PCIE_RPEFR_ERR_VALID) { dev_dbg(dev, "Requester ID %lu\n", val & XILINX_PCIE_RPEFR_REQ_ID); - pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK, + pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK, XILINX_PCIE_REG_RPEFR); } } @@ -152,11 +152,11 @@ static void xilinx_pcie_clear_err_interrupts(struct x= ilinx_pcie_port *port) */ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int dev= fn) { - struct xilinx_pcie_port *port =3D bus->sysdata; + struct xilinx_pcie *pcie =3D bus->sysdata; =20 - /* Check if link is up when trying to access downstream ports */ + /* Check if link is up when trying to access downstream pcie ports */ if (!pci_is_root_bus(bus)) { - if (!xilinx_pcie_link_up(port)) + if (!xilinx_pcie_link_up(pcie)) return false; } else if (devfn > 0) { /* Only one device down on each root port */ @@ -177,12 +177,12 @@ static bool xilinx_pcie_valid_device(struct pci_bus *= bus, unsigned int devfn) static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { - struct xilinx_pcie_port *port =3D bus->sysdata; + struct xilinx_pcie *pcie =3D bus->sysdata; =20 if (!xilinx_pcie_valid_device(bus, devfn)) return NULL; =20 - return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + return pcie->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } =20 /* PCIe operations */ @@ -215,7 +215,7 @@ static int xilinx_msi_set_affinity(struct irq_data *d, = const struct cpumask *mas =20 static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *= msg) { - struct xilinx_pcie_port *pcie =3D irq_data_get_irq_chip_data(data); + struct xilinx_pcie *pcie =3D irq_data_get_irq_chip_data(data); phys_addr_t pa =3D ALIGN_DOWN(virt_to_phys(pcie), SZ_4K); =20 msg->address_lo =3D lower_32_bits(pa); @@ -232,14 +232,14 @@ static struct irq_chip xilinx_msi_bottom_chip =3D { static int xilinx_msi_domain_alloc(struct irq_domain *domain, unsigned int= virq, unsigned int nr_irqs, void *args) { - struct xilinx_pcie_port *port =3D domain->host_data; + struct xilinx_pcie *pcie =3D domain->host_data; int hwirq, i; =20 - mutex_lock(&port->map_lock); + mutex_lock(&pcie->map_lock); =20 - hwirq =3D bitmap_find_free_region(port->msi_map, XILINX_NUM_MSI_IRQS, ord= er_base_2(nr_irqs)); + hwirq =3D bitmap_find_free_region(pcie->msi_map, XILINX_NUM_MSI_IRQS, ord= er_base_2(nr_irqs)); =20 - mutex_unlock(&port->map_lock); + mutex_unlock(&pcie->map_lock); =20 if (hwirq < 0) return -ENOSPC; @@ -256,13 +256,13 @@ static void xilinx_msi_domain_free(struct irq_domain = *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); - struct xilinx_pcie_port *port =3D domain->host_data; + struct xilinx_pcie *pcie =3D domain->host_data; =20 - mutex_lock(&port->map_lock); + mutex_lock(&pcie->map_lock); =20 - bitmap_release_region(port->msi_map, d->hwirq, order_base_2(nr_irqs)); + bitmap_release_region(pcie->msi_map, d->hwirq, order_base_2(nr_irqs)); =20 - mutex_unlock(&port->map_lock); + mutex_unlock(&pcie->map_lock); } =20 static const struct irq_domain_ops xilinx_msi_domain_ops =3D { @@ -275,7 +275,7 @@ static struct msi_domain_info xilinx_msi_info =3D { .chip =3D &xilinx_msi_top_chip, }; =20 -static int xilinx_allocate_msi_domains(struct xilinx_pcie_port *pcie) +static int xilinx_allocate_msi_domains(struct xilinx_pcie *pcie) { struct fwnode_handle *fwnode =3D dev_fwnode(pcie->dev); struct irq_domain *parent; @@ -298,7 +298,7 @@ static int xilinx_allocate_msi_domains(struct xilinx_pc= ie_port *pcie) return 0; } =20 -static void xilinx_free_msi_domains(struct xilinx_pcie_port *pcie) +static void xilinx_free_msi_domains(struct xilinx_pcie *pcie) { struct irq_domain *parent =3D pcie->msi_domain->parent; =20 @@ -342,13 +342,13 @@ static const struct irq_domain_ops intx_domain_ops = =3D { */ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) { - struct xilinx_pcie_port *port =3D (struct xilinx_pcie_port *)data; - struct device *dev =3D port->dev; + struct xilinx_pcie *pcie =3D (struct xilinx_pcie *)data; + struct device *dev =3D pcie->dev; u32 val, mask, status; =20 /* Read interrupt decode and mask registers */ - val =3D pcie_read(port, XILINX_PCIE_REG_IDR); - mask =3D pcie_read(port, XILINX_PCIE_REG_IMR); + val =3D pcie_read(pcie, XILINX_PCIE_REG_IDR); + mask =3D pcie_read(pcie, XILINX_PCIE_REG_IMR); =20 status =3D val & mask; if (!status) @@ -371,23 +371,23 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, = void *data) =20 if (status & XILINX_PCIE_INTR_CORRECTABLE) { dev_warn(dev, "Correctable error message\n"); - xilinx_pcie_clear_err_interrupts(port); + xilinx_pcie_clear_err_interrupts(pcie); } =20 if (status & XILINX_PCIE_INTR_NONFATAL) { dev_warn(dev, "Non fatal error message\n"); - xilinx_pcie_clear_err_interrupts(port); + xilinx_pcie_clear_err_interrupts(pcie); } =20 if (status & XILINX_PCIE_INTR_FATAL) { dev_warn(dev, "Fatal error message\n"); - xilinx_pcie_clear_err_interrupts(port); + xilinx_pcie_clear_err_interrupts(pcie); } =20 if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { struct irq_domain *domain; =20 - val =3D pcie_read(port, XILINX_PCIE_REG_RPIFR1); + val =3D pcie_read(pcie, XILINX_PCIE_REG_RPIFR1); =20 /* Check whether interrupt valid */ if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { @@ -397,17 +397,17 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, = void *data) =20 /* Decode the IRQ number */ if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { - val =3D pcie_read(port, XILINX_PCIE_REG_RPIFR2) & + val =3D pcie_read(pcie, XILINX_PCIE_REG_RPIFR2) & XILINX_PCIE_RPIFR2_MSG_DATA; - domain =3D port->msi_domain->parent; + domain =3D pcie->msi_domain->parent; } else { val =3D (val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT; - domain =3D port->leg_domain; + domain =3D pcie->leg_domain; } =20 /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + pcie_write(pcie, XILINX_PCIE_RPIFR1_ALL_MASK, XILINX_PCIE_REG_RPIFR1); =20 generic_handle_domain_irq(domain, val); @@ -442,20 +442,20 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, = void *data) =20 error: /* Clear the Interrupt Decode register */ - pcie_write(port, status, XILINX_PCIE_REG_IDR); + pcie_write(pcie, status, XILINX_PCIE_REG_IDR); =20 return IRQ_HANDLED; } =20 /** * xilinx_pcie_init_irq_domain - Initialize IRQ domain - * @port: PCIe port information + * @pcie: PCIe port information * * Return: '0' on success and error value on failure */ -static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) +static int xilinx_pcie_init_irq_domain(struct xilinx_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; struct device_node *pcie_intc_node; int ret; =20 @@ -466,25 +466,25 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_= pcie_port *port) return -ENODEV; } =20 - port->leg_domain =3D irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, + pcie->leg_domain =3D irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, &intx_domain_ops, - port); + pcie); of_node_put(pcie_intc_node); - if (!port->leg_domain) { + if (!pcie->leg_domain) { dev_err(dev, "Failed to get a INTx IRQ domain\n"); return -ENODEV; } =20 /* Setup MSI */ if (IS_ENABLED(CONFIG_PCI_MSI)) { - phys_addr_t pa =3D ALIGN_DOWN(virt_to_phys(port), SZ_4K); + phys_addr_t pa =3D ALIGN_DOWN(virt_to_phys(pcie), SZ_4K); =20 - ret =3D xilinx_allocate_msi_domains(port); + ret =3D xilinx_allocate_msi_domains(pcie); if (ret) return ret; =20 - pcie_write(port, upper_32_bits(pa), XILINX_PCIE_REG_MSIBASE1); - pcie_write(port, lower_32_bits(pa), XILINX_PCIE_REG_MSIBASE2); + pcie_write(pcie, upper_32_bits(pa), XILINX_PCIE_REG_MSIBASE1); + pcie_write(pcie, lower_32_bits(pa), XILINX_PCIE_REG_MSIBASE2); } =20 return 0; @@ -492,44 +492,44 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_= pcie_port *port) =20 /** * xilinx_pcie_init_port - Initialize hardware - * @port: PCIe port information + * @pcie: PCIe port information */ -static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) +static void xilinx_pcie_init_port(struct xilinx_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; =20 - if (xilinx_pcie_link_up(port)) + if (xilinx_pcie_link_up(pcie)) dev_info(dev, "PCIe Link is UP\n"); else dev_info(dev, "PCIe Link is DOWN\n"); =20 /* Disable all interrupts */ - pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK, + pcie_write(pcie, ~XILINX_PCIE_IDR_ALL_MASK, XILINX_PCIE_REG_IMR); =20 /* Clear pending interrupts */ - pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) & + pcie_write(pcie, pcie_read(pcie, XILINX_PCIE_REG_IDR) & XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IDR); =20 /* Enable all interrupts we handle */ - pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR); + pcie_write(pcie, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR); =20 /* Enable the Bridge enable bit */ - pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) | + pcie_write(pcie, pcie_read(pcie, XILINX_PCIE_REG_RPSC) | XILINX_PCIE_REG_RPSC_BEN, XILINX_PCIE_REG_RPSC); } =20 /** * xilinx_pcie_parse_dt - Parse Device tree - * @port: PCIe port information + * @pcie: PCIe port information * * Return: '0' on success and error value on failure */ -static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port) +static int xilinx_pcie_parse_dt(struct xilinx_pcie *pcie) { - struct device *dev =3D port->dev; + struct device *dev =3D pcie->dev; struct device_node *node =3D dev->of_node; struct resource regs; unsigned int irq; @@ -541,14 +541,14 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_po= rt *port) return err; } =20 - port->reg_base =3D devm_pci_remap_cfg_resource(dev, ®s); - if (IS_ERR(port->reg_base)) - return PTR_ERR(port->reg_base); + pcie->reg_base =3D devm_pci_remap_cfg_resource(dev, ®s); + if (IS_ERR(pcie->reg_base)) + return PTR_ERR(pcie->reg_base); =20 irq =3D irq_of_parse_and_map(node, 0); err =3D devm_request_irq(dev, irq, xilinx_pcie_intr_handler, IRQF_SHARED | IRQF_NO_THREAD, - "xilinx-pcie", port); + "xilinx-pcie", pcie); if (err) { dev_err(dev, "unable to request irq %d\n", irq); return err; @@ -566,41 +566,41 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_po= rt *port) static int xilinx_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct xilinx_pcie_port *port; + struct xilinx_pcie *pcie; struct pci_host_bridge *bridge; int err; =20 if (!dev->of_node) return -ENODEV; =20 - bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*port)); + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!bridge) return -ENODEV; =20 - port =3D pci_host_bridge_priv(bridge); - mutex_init(&port->map_lock); - port->dev =3D dev; + pcie =3D pci_host_bridge_priv(bridge); + mutex_init(&pcie->map_lock); + pcie->dev =3D dev; =20 - err =3D xilinx_pcie_parse_dt(port); + err =3D xilinx_pcie_parse_dt(pcie); if (err) { dev_err(dev, "Parsing DT failed\n"); return err; } =20 - xilinx_pcie_init_port(port); + xilinx_pcie_init_port(pcie); =20 - err =3D xilinx_pcie_init_irq_domain(port); + err =3D xilinx_pcie_init_irq_domain(pcie); if (err) { dev_err(dev, "Failed creating IRQ Domain\n"); return err; } =20 - bridge->sysdata =3D port; + bridge->sysdata =3D pcie; bridge->ops =3D &xilinx_pcie_ops; =20 err =3D pci_host_probe(bridge); if (err) - xilinx_free_msi_domains(port); + xilinx_free_msi_domains(pcie); =20 return err; } --=20 2.25.1 From nobody Wed Jul 1 09:55:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1031C433EF for ; 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d=kernel.org; s=k20201202; t=1640221911; bh=NIHlxx32hZquI6e6s7ce33q6+j4ig8ruxqlAWwHME8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q0CiPqthI0XC+sVnpYnHPXcP0K2YhieePFjgiVH+s2E0u6hIs1HSo5MzttON2ai8S FfbTnK/jBmE74ntz5xYnVXaOAc0Lw082Bb6jYop7sK4TJtmP6yec8DuuM8XFiy+uFb YoaVgN1BmL97qrD8RQ2OJRdlMlnUqSzmkKGohRPJWUwo3QBm58UbjSPMsCpMHtWsmB 1CTg+j9ZLJdYP9SsedjFFSeXcZ3ie50nMg5epoQsxDS4OiwaQsECaDXLbGOi7wAgm5 zY1fuWZ3vlL9AbO6HR1xpXYeuHAoordqu/sGkWWd6IwZP9lOv1N6rXchDSCSPqacFu dYzqEfMr48j3A== From: Bjorn Helgaas To: linux-pci@vger.kernel.org, Fan Fei Cc: Lorenzo Pieralisi , Rob Herring , linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Shuah Khan , Bjorn Helgaas , Michal Simek , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 23/23] PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcie Date: Wed, 22 Dec 2021 19:10:54 -0600 Message-Id: <20211223011054.1227810-24-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211223011054.1227810-1-helgaas@kernel.org> References: <20211223011054.1227810-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas Rename struct xilinx_cpm_pcie_port to xilinx_cpm_pcie to match the convention of _pcie. No functional change intended. Signed-off-by: Bjorn Helgaas Cc: Michal Simek Cc: linux-arm-kernel@lists.infradead.org --- drivers/pci/controller/pcie-xilinx-cpm.c | 44 ++++++++++++------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/control= ler/pcie-xilinx-cpm.c index 95426df03200..c7cd44ed4dfc 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -99,10 +99,10 @@ #define XILINX_CPM_PCIE_REG_PSCR_LNKUP BIT(11) =20 /** - * struct xilinx_cpm_pcie_port - PCIe port information + * struct xilinx_cpm_pcie - PCIe port information + * @dev: Device pointer * @reg_base: Bridge Register Base * @cpm_base: CPM System Level Control and Status Register(SLCR) Base - * @dev: Device pointer * @intx_domain: Legacy IRQ domain pointer * @cpm_domain: CPM IRQ domain pointer * @cfg: Holds mappings of config space window @@ -110,10 +110,10 @@ * @irq: Error interrupt number * @lock: lock protecting shared register access */ -struct xilinx_cpm_pcie_port { +struct xilinx_cpm_pcie { + struct device *dev; void __iomem *reg_base; void __iomem *cpm_base; - struct device *dev; struct irq_domain *intx_domain; struct irq_domain *cpm_domain; struct pci_config_window *cfg; @@ -122,24 +122,24 @@ struct xilinx_cpm_pcie_port { raw_spinlock_t lock; }; =20 -static u32 pcie_read(struct xilinx_cpm_pcie_port *port, u32 reg) +static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) { return readl_relaxed(port->reg_base + reg); } =20 -static void pcie_write(struct xilinx_cpm_pcie_port *port, +static void pcie_write(struct xilinx_cpm_pcie *port, u32 val, u32 reg) { writel_relaxed(val, port->reg_base + reg); } =20 -static bool cpm_pcie_link_up(struct xilinx_cpm_pcie_port *port) +static bool cpm_pcie_link_up(struct xilinx_cpm_pcie *port) { return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) & XILINX_CPM_PCIE_REG_PSCR_LNKUP); } =20 -static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie_port *por= t) +static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie *port) { unsigned long val =3D pcie_read(port, XILINX_CPM_PCIE_REG_RPEFR); =20 @@ -153,7 +153,7 @@ static void cpm_pcie_clear_err_interrupts(struct xilinx= _cpm_pcie_port *port) =20 static void xilinx_cpm_mask_leg_irq(struct irq_data *data) { - struct xilinx_cpm_pcie_port *port =3D irq_data_get_irq_chip_data(data); + struct xilinx_cpm_pcie *port =3D irq_data_get_irq_chip_data(data); unsigned long flags; u32 mask; u32 val; @@ -167,7 +167,7 @@ static void xilinx_cpm_mask_leg_irq(struct irq_data *da= ta) =20 static void xilinx_cpm_unmask_leg_irq(struct irq_data *data) { - struct xilinx_cpm_pcie_port *port =3D irq_data_get_irq_chip_data(data); + struct xilinx_cpm_pcie *port =3D irq_data_get_irq_chip_data(data); unsigned long flags; u32 mask; u32 val; @@ -211,7 +211,7 @@ static const struct irq_domain_ops intx_domain_ops =3D { =20 static void xilinx_cpm_pcie_intx_flow(struct irq_desc *desc) { - struct xilinx_cpm_pcie_port *port =3D irq_desc_get_handler_data(desc); + struct xilinx_cpm_pcie *port =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); unsigned long val; int i; @@ -229,7 +229,7 @@ static void xilinx_cpm_pcie_intx_flow(struct irq_desc *= desc) =20 static void xilinx_cpm_mask_event_irq(struct irq_data *d) { - struct xilinx_cpm_pcie_port *port =3D irq_data_get_irq_chip_data(d); + struct xilinx_cpm_pcie *port =3D irq_data_get_irq_chip_data(d); u32 val; =20 raw_spin_lock(&port->lock); @@ -241,7 +241,7 @@ static void xilinx_cpm_mask_event_irq(struct irq_data *= d) =20 static void xilinx_cpm_unmask_event_irq(struct irq_data *d) { - struct xilinx_cpm_pcie_port *port =3D irq_data_get_irq_chip_data(d); + struct xilinx_cpm_pcie *port =3D irq_data_get_irq_chip_data(d); u32 val; =20 raw_spin_lock(&port->lock); @@ -273,7 +273,7 @@ static const struct irq_domain_ops event_domain_ops =3D= { =20 static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) { - struct xilinx_cpm_pcie_port *port =3D irq_desc_get_handler_data(desc); + struct xilinx_cpm_pcie *port =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); unsigned long val; int i; @@ -327,7 +327,7 @@ static const struct { =20 static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id) { - struct xilinx_cpm_pcie_port *port =3D dev_id; + struct xilinx_cpm_pcie *port =3D dev_id; struct device *dev =3D port->dev; struct irq_data *d; =20 @@ -350,7 +350,7 @@ static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq= , void *dev_id) return IRQ_HANDLED; } =20 -static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie_port *port) +static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie *port) { if (port->intx_domain) { irq_domain_remove(port->intx_domain); @@ -369,7 +369,7 @@ static void xilinx_cpm_free_irq_domains(struct xilinx_c= pm_pcie_port *port) * * Return: '0' on success and error value on failure */ -static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie_port *po= rt) +static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port) { struct device *dev =3D port->dev; struct device_node *node =3D dev->of_node; @@ -410,7 +410,7 @@ static int xilinx_cpm_pcie_init_irq_domain(struct xilin= x_cpm_pcie_port *port) return -ENOMEM; } =20 -static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie_port *port) +static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port) { struct device *dev =3D port->dev; struct platform_device *pdev =3D to_platform_device(dev); @@ -462,7 +462,7 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie_= port *port) * xilinx_cpm_pcie_init_port - Initialize hardware * @port: PCIe port information */ -static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie_port *port) +static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { if (cpm_pcie_link_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); @@ -497,7 +497,7 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm= _pcie_port *port) * * Return: '0' on success and error value on failure */ -static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie_port *port, +static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, struct resource *bus_range) { struct device *dev =3D port->dev; @@ -523,7 +523,7 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_p= cie_port *port, return 0; } =20 -static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie_port *port) +static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie *port) { irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL); irq_set_chained_handler_and_data(port->irq, NULL, NULL); @@ -537,7 +537,7 @@ static void xilinx_cpm_free_interrupts(struct xilinx_cp= m_pcie_port *port) */ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) { - struct xilinx_cpm_pcie_port *port; + struct xilinx_cpm_pcie *port; struct device *dev =3D &pdev->dev; struct pci_host_bridge *bridge; struct resource_entry *bus; --=20 2.25.1