From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C375BC433F5 for ; Fri, 17 Dec 2021 22:01:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231136AbhLQWBu (ORCPT ); Fri, 17 Dec 2021 17:01:50 -0500 Received: from mga11.intel.com ([192.55.52.93]:26492 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbhLQWBs (ORCPT ); Fri, 17 Dec 2021 17:01:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778508; x=1671314508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vrJ/zKRVUU6ZR06GrFfxZCmYCCjEMizfBdO6/ux2RvU=; b=JOsmFRhquO0/lkAVTgVBlCwKFAfp2cLo5PR+wlM5c3ku2pnFQ5RmIIeo zbiClsJYg4jCLevU9ZYKgtdMkyLikacHb8kP6vZaaWCO2jriXV9usIyXF mRRNWBlBK0hktsSFsA1/2zGLSp9UePpyuGGthWSyaA93Pse40KT/UFg3i BQb/zJ1GyGRdLs5m+2j5SEvfvZ8W3/vCYY8jHCCO97vbVxaEhqhtFcmDo Q13yKUFj6g3VDoJlf6bEs3lyLhE5ac5hSegucN1a6+OUBAdVfNTBxVPat lf4dCgLOMOuUjQqKxUavkIxaewceK6khdGfs/+7qM3g1WDeB0VS1vWQEa w==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381584" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381584" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928073" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:46 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 01/11] iommu/sva: Rename CONFIG_IOMMU_SVA_LIB to CONFIG_IOMMU_SVA Date: Fri, 17 Dec 2021 22:01:26 +0000 Message-Id: <20211217220136.2762116-2-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This CONFIG option originally only referred to the Shared Virtual Address (SVA) library. But it is now also used for non-library portions of code. Drop the "_LIB" suffix so that there is just one configuration options for all code relating to SVA. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Add this patch for more meaningful name CONFIG_IOMMU_SVA drivers/iommu/Kconfig | 6 +++--- drivers/iommu/Makefile | 2 +- drivers/iommu/intel/Kconfig | 2 +- drivers/iommu/iommu-sva-lib.h | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 3eb68fa1b8cc..c79a0df090c0 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -144,8 +144,8 @@ config IOMMU_DMA select IRQ_MSI_IOMMU select NEED_SG_DMA_LENGTH =20 -# Shared Virtual Addressing library -config IOMMU_SVA_LIB +# Shared Virtual Addressing +config IOMMU_SVA bool select IOASID =20 @@ -379,7 +379,7 @@ config ARM_SMMU_V3 config ARM_SMMU_V3_SVA bool "Shared Virtual Addressing support for the ARM SMMUv3" depends on ARM_SMMU_V3 - select IOMMU_SVA_LIB + select IOMMU_SVA select MMU_NOTIFIER help Support for sharing process address spaces with devices using the diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index bc7f730edbb0..44475a9b3eea 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -27,6 +27,6 @@ obj-$(CONFIG_FSL_PAMU) +=3D fsl_pamu.o fsl_pamu_domain.o obj-$(CONFIG_S390_IOMMU) +=3D s390-iommu.o obj-$(CONFIG_HYPERV_IOMMU) +=3D hyperv-iommu.o obj-$(CONFIG_VIRTIO_IOMMU) +=3D virtio-iommu.o -obj-$(CONFIG_IOMMU_SVA_LIB) +=3D iommu-sva-lib.o io-pgfault.o +obj-$(CONFIG_IOMMU_SVA) +=3D iommu-sva-lib.o io-pgfault.o obj-$(CONFIG_SPRD_IOMMU) +=3D sprd-iommu.o obj-$(CONFIG_APPLE_DART) +=3D apple-dart.o diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig index 247d0f2d5fdf..39a06d245f12 100644 --- a/drivers/iommu/intel/Kconfig +++ b/drivers/iommu/intel/Kconfig @@ -52,7 +52,7 @@ config INTEL_IOMMU_SVM select PCI_PRI select MMU_NOTIFIER select IOASID - select IOMMU_SVA_LIB + select IOMMU_SVA help Shared Virtual Memory (SVM) provides a facility for devices to access DMA resources through process address space by diff --git a/drivers/iommu/iommu-sva-lib.h b/drivers/iommu/iommu-sva-lib.h index 031155010ca8..95dc3ebc1928 100644 --- a/drivers/iommu/iommu-sva-lib.h +++ b/drivers/iommu/iommu-sva-lib.h @@ -17,7 +17,7 @@ struct device; struct iommu_fault; struct iopf_queue; =20 -#ifdef CONFIG_IOMMU_SVA_LIB +#ifdef CONFIG_IOMMU_SVA int iommu_queue_iopf(struct iommu_fault *fault, void *cookie); =20 int iopf_queue_add_device(struct iopf_queue *queue, struct device *dev); @@ -28,7 +28,7 @@ struct iopf_queue *iopf_queue_alloc(const char *name); void iopf_queue_free(struct iopf_queue *queue); int iopf_queue_discard_partial(struct iopf_queue *queue); =20 -#else /* CONFIG_IOMMU_SVA_LIB */ +#else /* CONFIG_IOMMU_SVA */ static inline int iommu_queue_iopf(struct iommu_fault *fault, void *cookie) { return -ENODEV; @@ -64,5 +64,5 @@ static inline int iopf_queue_discard_partial(struct iopf_= queue *queue) { return -ENODEV; } -#endif /* CONFIG_IOMMU_SVA_LIB */ +#endif /* CONFIG_IOMMU_SVA */ #endif /* _IOMMU_SVA_LIB_H */ --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED5B9C433EF for ; Fri, 17 Dec 2021 22:01:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231138AbhLQWBw (ORCPT ); Fri, 17 Dec 2021 17:01:52 -0500 Received: from mga11.intel.com ([192.55.52.93]:26492 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbhLQWBs (ORCPT ); Fri, 17 Dec 2021 17:01:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778508; x=1671314508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NHuCxyOdESdoiv75buH1o0WjIBI3bzfAYUCIy2K5lYI=; b=bAy93BPmwYowB7KeNRrC4s/ALFrqq1l/E7P4pje1pJUxkJaDeuaUspF3 lkkyXyNHRZPdD7zsYjGzviK1/ACB3gsvQ0rOmk/ekQgma0JV19Ngm9jhF ZfUvpNVCVnxpe/ahWFJAFar5ze0OEonkujPpiVnu0ANUjBbxLUVwo1ftW CM9+lcPaB4UrncoMdujJWxUapQiGzfUE/W+L+tZotOri0nehDADrjDh2F k0A5kYC5nPl+3xEKNwf+nS3j9NRoVMtm+IKhtP/LyEuCngxxr6QptYKLv 5jCUhtD7krXMB6aOLdrzDzzyoypHzP7exRd67/wEVXf7accZ90o1iec6r g==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381585" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381585" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928076" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:47 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 02/11] mm: Change CONFIG option for mm->pasid field Date: Fri, 17 Dec 2021 22:01:27 +0000 Message-Id: <20211217220136.2762116-3-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This currently depends on CONFIG_IOMMU_SUPPORT. But it is only needed when CONFIG_IOMMU_SVA option is enabled. Change the CONFIG guards around definition and initialization of mm->pasid field. Suggested-by: Jacob Pan Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change condition to more accurate CONFIG_IOMMU_SVA (Jacob and Tony) include/linux/mm_types.h | 2 +- kernel/fork.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index c3a6e6209600..6d92121d5bd9 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -643,7 +643,7 @@ struct mm_struct { #endif struct work_struct async_put_work; =20 -#ifdef CONFIG_IOMMU_SUPPORT +#ifdef CONFIG_IOMMU_SVA u32 pasid; #endif } __randomize_layout; diff --git a/kernel/fork.c b/kernel/fork.c index 3244cc56b697..b33c52021d4e 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1020,7 +1020,7 @@ static void mm_init_owner(struct mm_struct *mm, struc= t task_struct *p) =20 static void mm_init_pasid(struct mm_struct *mm) { -#ifdef CONFIG_IOMMU_SUPPORT +#ifdef CONFIG_IOMMU_SVA mm->pasid =3D INIT_PASID; #endif } --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C996C433FE for ; Fri, 17 Dec 2021 22:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231246AbhLQWB5 (ORCPT ); Fri, 17 Dec 2021 17:01:57 -0500 Received: from mga11.intel.com ([192.55.52.93]:26496 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230498AbhLQWBs (ORCPT ); Fri, 17 Dec 2021 17:01:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778508; x=1671314508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h2zjBHw31kxQlzvVTL7vpb6HSLLXWXz/ULtGSJqMjjU=; b=XA13eyqAU+lEiYeCuGPJYLbdhXP70jHn3nNxyv9XSod2o/4b9iYiecTX 61g9h8V3X68c52RnfFABs55HomXh9/P6rxk/l+wnLh3WUoJHcB0EgCDnO XC4lr5C//vLSxyACNKe+upMg4lnPv5Wt36mL2VRJ5cQutwPPo1AUESdJ2 leXRZFTrq0nVloi7/FD3bw2EgBWqotX3OFmN0FpRUlNb+DhrLloeZ9SsT fbMHMX2OXGwiAkVtRNRsv7jCGzIWVD9jsLtZF1VibcCjt3kZVIY3anjwq TuseeusmH0IWxuYNdZtQbO6XA+0sDozdtj/HZk8Iui+8/r9yfdD8nyYBf Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381587" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381587" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928082" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:47 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 03/11] iommu/ioasid: Introduce a helper to check for valid PASIDs Date: Fri, 17 Dec 2021 22:01:28 +0000 Message-Id: <20211217220136.2762116-4-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" pasid_valid() is defined to check if a given PASID is valid. Suggested-by: Ashok Raj Suggested-by: Jacob Pan Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Define a helper pasid_valid() (Ashok, Jacob, Thomas, Tony) include/linux/ioasid.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/ioasid.h b/include/linux/ioasid.h index e9dacd4b9f6b..2237f64dbaae 100644 --- a/include/linux/ioasid.h +++ b/include/linux/ioasid.h @@ -41,6 +41,10 @@ void *ioasid_find(struct ioasid_set *set, ioasid_t ioasi= d, int ioasid_register_allocator(struct ioasid_allocator_ops *allocator); void ioasid_unregister_allocator(struct ioasid_allocator_ops *allocator); int ioasid_set_data(ioasid_t ioasid, void *data); +static inline bool pasid_valid(ioasid_t ioasid) +{ + return ioasid !=3D INVALID_IOASID; +} =20 #else /* !CONFIG_IOASID */ static inline ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, @@ -78,5 +82,10 @@ static inline int ioasid_set_data(ioasid_t ioasid, void = *data) return -ENOTSUPP; } =20 +static inline bool pasid_valid(ioasid_t ioasid) +{ + return false; +} + #endif /* CONFIG_IOASID */ #endif /* __LINUX_IOASID_H */ --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8385FC433F5 for ; Fri, 17 Dec 2021 22:01:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231151AbhLQWBy (ORCPT ); Fri, 17 Dec 2021 17:01:54 -0500 Received: from mga11.intel.com ([192.55.52.93]:26492 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbhLQWBt (ORCPT ); Fri, 17 Dec 2021 17:01:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778508; x=1671314508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uaN1ppSyx00sbK+6ZvuNPJeDvV+BViDU9aY3XKLPb00=; b=Q+/l72Q9SCvBqxBn5IbdJhsnY/9wrlD79ITObOhoG48Ht7VAfttNhiVB PyWGOK2vs1F4hYpUj/VZWdhUOaokEB6q1BHyAH9yG0hCxrlf+f7nv2Ujq Y8n/Fi9DJDUL0aRbBkNa9B0PeX0OIbTSULXLw7kxCu9xeoVS+Y3yTbmqh w5LjMQkUcXJyichDTiw7C5lzzUwEno/Zz2cVp5WAhZwm3kindl99N1+Gk KAVD3lpfBhnzNNfOwTvS/BCsfL7RneqP/HR5ltOBb8LfCOEQy4zNEiUvI edz+fuTM0JbZKHG5z5NgNHzMjHd0R6vnaQ8RDIvQVSk+Dw5qRlTE1ClBC g==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381589" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381589" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928090" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:48 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 04/11] kernel/fork: Initialize mm's PASID Date: Fri, 17 Dec 2021 22:01:29 +0000 Message-Id: <20211217220136.2762116-5-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" A new mm doesn't have a PASID yet when it's created. Initialize the mm's PASID on fork() or for init_mm to INVALID_IOASID (-1). Suggested-by: Dave Hansen Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change condition to more accurate CONFIG_IOMMU_SVA (Jacob) include/linux/sched/mm.h | 10 ++++++++++ kernel/fork.c | 10 ++-------- mm/init-mm.c | 4 ++++ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h index aca874d33fe6..394c4359c4e1 100644 --- a/include/linux/sched/mm.h +++ b/include/linux/sched/mm.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 /* * Routines for handling mm_structs @@ -407,4 +408,13 @@ static inline void membarrier_update_current_mm(struct= mm_struct *next_mm) } #endif =20 +#ifdef CONFIG_IOMMU_SVA +static inline void mm_pasid_init(struct mm_struct *mm) +{ + mm->pasid =3D INVALID_IOASID; +} +#else +static inline void mm_pasid_init(struct mm_struct *mm) {} +#endif + #endif /* _LINUX_SCHED_MM_H */ diff --git a/kernel/fork.c b/kernel/fork.c index b33c52021d4e..4e799c9b13bb 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -96,6 +96,7 @@ #include #include #include +#include =20 #include #include @@ -1018,13 +1019,6 @@ static void mm_init_owner(struct mm_struct *mm, stru= ct task_struct *p) #endif } =20 -static void mm_init_pasid(struct mm_struct *mm) -{ -#ifdef CONFIG_IOMMU_SVA - mm->pasid =3D INIT_PASID; -#endif -} - static void mm_init_uprobes_state(struct mm_struct *mm) { #ifdef CONFIG_UPROBES @@ -1053,7 +1047,7 @@ static struct mm_struct *mm_init(struct mm_struct *mm= , struct task_struct *p, mm_init_cpumask(mm); mm_init_aio(mm); mm_init_owner(mm, p); - mm_init_pasid(mm); + mm_pasid_init(mm); RCU_INIT_POINTER(mm->exe_file, NULL); mmu_notifier_subscriptions_init(mm); init_tlb_flush_pending(mm); diff --git a/mm/init-mm.c b/mm/init-mm.c index b4a6f38fb51d..fbe7844d0912 100644 --- a/mm/init-mm.c +++ b/mm/init-mm.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include =20 #ifndef INIT_MM_CONTEXT @@ -38,6 +39,9 @@ struct mm_struct init_mm =3D { .mmlist =3D LIST_HEAD_INIT(init_mm.mmlist), .user_ns =3D &init_user_ns, .cpu_bitmap =3D CPU_BITS_NONE, +#ifdef CONFIG_IOMMU_SVA + .pasid =3D INVALID_IOASID, +#endif INIT_MM_CONTEXT(init_mm) }; =20 --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 647A2C433EF for ; Fri, 17 Dec 2021 22:02:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231283AbhLQWB6 (ORCPT ); Fri, 17 Dec 2021 17:01:58 -0500 Received: from mga11.intel.com ([192.55.52.93]:26498 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229708AbhLQWBt (ORCPT ); Fri, 17 Dec 2021 17:01:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778509; x=1671314509; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uwIHb5zj6Jp1q7vDF3B1k2nArvxSaD/bhIY0C76LGDw=; b=atbhhPMGXwDYBU6qZeuMShaea6WO6Ri2kqlObXlIpLWriAkLqN6QQtHU 7wPcyIsvVbRhrHpN9AZ9paQUA17Q7MFCvBz1xi8g9xsXaFnBmXv5w+Jaz +Yv1fjL417f5ggga1M78nrNZ9JhOnUszQoA+nynHI2uyKOF7RSMGm2vhI V0lF0y+PrFMziGODCcp4kumTeesx2f5h8kgTH34rBwjxYC8WhAkEq8uVH qYC2HMbpIACJWRdxEMCV5vGXxa2/d/fiM0fGrasQroBjG3cao7pss9e08 o8DVgFZSElNi5EGzYqZsJ9xcfR95Rl5MyG5Ai+xENptt8YEegUPCMwJfe A==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381591" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381591" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928094" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:48 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 05/11] iommu/sva: Assign a PASID to mm on PASID allocation and free it on mm exit Date: Fri, 17 Dec 2021 22:01:30 +0000 Message-Id: <20211217220136.2762116-6-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To avoid complexity of updating each thread's PASID status (e.g. sending IPI to update IA32_PASID MSR) on allocating and freeing PASID, once allocated and assigned to an mm, the PASID stays with the mm for the rest of the mm's lifetime. A reference to the PASID is taken on allocating the PASID. Binding/unbinding the PASID won't change refcount. The reference is dropped on mm exit and thus the PASID is freed. Two helpers mm_pasid_get() and mm_pasid_drop() are defined in mm because the PASID operations handle the pasid member in mm_struct and should be part of mm operations. 20-bit PASID allows up to 1M processes bound to PASIDs at the same time. With cgroups and other controls that might limit the number of process creation, the limited number of PASIDs is not a realistic issue for lazy PASID free. Suggested-by: Dave Hansen Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Free PASID on mm exit instead of in exit(2) or unbind() (Thomas, AndyL, PeterZ) - Add mm_pasid_init(), mm_pasid_get(), and mm_pasid_drop() functions in mm. So the mm's PASID operations are generic for both X86 and ARM (Dave Hansen) .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +-- drivers/iommu/intel/svm.c | 9 ----- drivers/iommu/iommu-sva-lib.c | 39 ++++++------------- drivers/iommu/iommu-sva-lib.h | 1 - include/linux/sched/mm.h | 16 ++++++++ kernel/fork.c | 1 + 6 files changed, 30 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index ee66d1f4cb81..c153ffae5462 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -340,14 +340,12 @@ __arm_smmu_sva_bind(struct device *dev, struct mm_str= uct *mm) bond->smmu_mn =3D arm_smmu_mmu_notifier_get(smmu_domain, mm); if (IS_ERR(bond->smmu_mn)) { ret =3D PTR_ERR(bond->smmu_mn); - goto err_free_pasid; + goto err_free_bond; } =20 list_add(&bond->list, &master->bonds); return &bond->sva; =20 -err_free_pasid: - iommu_sva_free_pasid(mm); err_free_bond: kfree(bond); return ERR_PTR(ret); @@ -377,7 +375,6 @@ void arm_smmu_sva_unbind(struct iommu_sva *handle) if (refcount_dec_and_test(&bond->refs)) { list_del(&bond->list); arm_smmu_mmu_notifier_put(bond->smmu_mn); - iommu_sva_free_pasid(bond->mm); kfree(bond); } mutex_unlock(&sva_lock); diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 5b5d69b04fcc..51ac2096b3da 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -514,11 +514,6 @@ static int intel_svm_alloc_pasid(struct device *dev, s= truct mm_struct *mm, return iommu_sva_alloc_pasid(mm, PASID_MIN, max_pasid - 1); } =20 -static void intel_svm_free_pasid(struct mm_struct *mm) -{ - iommu_sva_free_pasid(mm); -} - static struct iommu_sva *intel_svm_bind_mm(struct intel_iommu *iommu, struct device *dev, struct mm_struct *mm, @@ -662,8 +657,6 @@ static int intel_svm_unbind_mm(struct device *dev, u32 = pasid) kfree(svm); } } - /* Drop a PASID reference and free it if no reference. */ - intel_svm_free_pasid(mm); } out: return ret; @@ -1047,8 +1040,6 @@ struct iommu_sva *intel_svm_bind(struct device *dev, = struct mm_struct *mm, void } =20 sva =3D intel_svm_bind_mm(iommu, dev, mm, flags); - if (IS_ERR_OR_NULL(sva)) - intel_svm_free_pasid(mm); mutex_unlock(&pasid_mutex); =20 return sva; diff --git a/drivers/iommu/iommu-sva-lib.c b/drivers/iommu/iommu-sva-lib.c index bd41405d34e9..ee2294e02716 100644 --- a/drivers/iommu/iommu-sva-lib.c +++ b/drivers/iommu/iommu-sva-lib.c @@ -18,8 +18,7 @@ static DECLARE_IOASID_SET(iommu_sva_pasid); * * Try to allocate a PASID for this mm, or take a reference to the existin= g one * provided it fits within the [@min, @max] range. On success the PASID is - * available in mm->pasid, and must be released with iommu_sva_free_pasid(= ). - * @min must be greater than 0, because 0 indicates an unused mm->pasid. + * available in mm->pasid and will be available for the lifetime of the mm. * * Returns 0 on success and < 0 on error. */ @@ -33,38 +32,24 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_= t min, ioasid_t max) return -EINVAL; =20 mutex_lock(&iommu_sva_lock); - if (mm->pasid) { - if (mm->pasid >=3D min && mm->pasid <=3D max) - ioasid_get(mm->pasid); - else + /* Is a PASID already associated with this mm? */ + if (pasid_valid(mm->pasid)) { + if (mm->pasid < min || mm->pasid >=3D max) ret =3D -EOVERFLOW; - } else { - pasid =3D ioasid_alloc(&iommu_sva_pasid, min, max, mm); - if (pasid =3D=3D INVALID_IOASID) - ret =3D -ENOMEM; - else - mm->pasid =3D pasid; + goto out; } + + pasid =3D ioasid_alloc(&iommu_sva_pasid, min, max, mm); + if (!pasid_valid(pasid)) + ret =3D -ENOMEM; + else + mm_pasid_get(mm, pasid); +out: mutex_unlock(&iommu_sva_lock); return ret; } EXPORT_SYMBOL_GPL(iommu_sva_alloc_pasid); =20 -/** - * iommu_sva_free_pasid - Release the mm's PASID - * @mm: the mm - * - * Drop one reference to a PASID allocated with iommu_sva_alloc_pasid() - */ -void iommu_sva_free_pasid(struct mm_struct *mm) -{ - mutex_lock(&iommu_sva_lock); - if (ioasid_put(mm->pasid)) - mm->pasid =3D 0; - mutex_unlock(&iommu_sva_lock); -} -EXPORT_SYMBOL_GPL(iommu_sva_free_pasid); - /* ioasid_find getter() requires a void * argument */ static bool __mmget_not_zero(void *mm) { diff --git a/drivers/iommu/iommu-sva-lib.h b/drivers/iommu/iommu-sva-lib.h index 95dc3ebc1928..8909ea1094e3 100644 --- a/drivers/iommu/iommu-sva-lib.h +++ b/drivers/iommu/iommu-sva-lib.h @@ -9,7 +9,6 @@ #include =20 int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max= ); -void iommu_sva_free_pasid(struct mm_struct *mm); struct mm_struct *iommu_sva_find(ioasid_t pasid); =20 /* I/O Page fault */ diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h index 394c4359c4e1..21cd094283ad 100644 --- a/include/linux/sched/mm.h +++ b/include/linux/sched/mm.h @@ -413,8 +413,24 @@ static inline void mm_pasid_init(struct mm_struct *mm) { mm->pasid =3D INVALID_IOASID; } + +/* Associate a PASID with an mm_struct: */ +static inline void mm_pasid_get(struct mm_struct *mm, u32 pasid) +{ + mm->pasid =3D pasid; +} + +static inline void mm_pasid_drop(struct mm_struct *mm) +{ + if (pasid_valid(mm->pasid)) { + ioasid_put(mm->pasid); + mm->pasid =3D INVALID_IOASID; + } +} #else static inline void mm_pasid_init(struct mm_struct *mm) {} +static inline void mm_pasid_get(struct mm_struct *mm, u32 pasid) {} +static inline void mm_pasid_drop(struct mm_struct *mm) {} #endif =20 #endif /* _LINUX_SCHED_MM_H */ diff --git a/kernel/fork.c b/kernel/fork.c index 4e799c9b13bb..3adad225cc09 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1114,6 +1114,7 @@ static inline void __mmput(struct mm_struct *mm) } if (mm->binfmt) module_put(mm->binfmt->module); + mm_pasid_drop(mm); mmdrop(mm); } =20 --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77DDEC433F5 for ; Fri, 17 Dec 2021 22:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231354AbhLQWCA (ORCPT ); Fri, 17 Dec 2021 17:02:00 -0500 Received: from mga11.intel.com ([192.55.52.93]:26498 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230514AbhLQWBt (ORCPT ); Fri, 17 Dec 2021 17:01:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778509; x=1671314509; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TQwS440v7IbXqfoaDLFqxTIfDX/CqMUM6Yd9UQpEfkM=; b=mIsEDPgkD6OT7Ly2jNONj0ryFJbw+1opi891FL15RdfrzIViMwnqqyvP BfyzIRDv3D+w0cpTOR5AxA3wrlxHnWCp/EsqEnwijy2ZUul5jnnMRt+E7 12CmYoc564mwxabRHNNdbacvdrPJxmcfZBayhlpW7aTG/+8r4Pkh/qROa oXDrptkE4RwXibnZ7SPeuVC/ObS0wd7qyhVnLwapfw4f20vCuRvapJp+F 3MaroBD6UIWiOWmjfqnWDVszmpy3KyksGAsqiML1Sht28BJqtAnCKG40l ECwAIrmiNTUH/Pu2aKASonxIL4C4D/lSaQcLIKDE7qN1ih/snngzKSaJ0 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381594" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381594" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928098" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:49 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 06/11] x86/fpu: Clear PASID when copying fpstate Date: Fri, 17 Dec 2021 22:01:31 +0000 Message-Id: <20211217220136.2762116-7-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kernel must allocate a Process Address Space ID (PASID) on behalf of each process which will use ENQCMD and program it into the new MSR to communicate the process identity to platform hardware. ENQCMD uses the PASID stored in this MSR to tag requests from this process. The PASID state must be cleared on fork() since fork creates a new address space. For clone(), it would be functionally OK to copy the PASID. However, clearing it is _also_ functionally OK since any PASID use will trigger the #GP handler to populate the MSR. Copying the PASID state has two main downsides: * It requires differentiating fork() and clone() in the code, both in the FPU code and keeping tsk->pasid_activated consistent. * It guarantees that the PASID is out of its init state, which incurs small but non-zero cost on every XSAVE/XRSTOR. The main downside of clearing the PASID at fpstate copy is the future, one-time #GP for the thread. Use the simplest approach: clear the PASID state both on clone() and fork(). Rely on the #GP handler for MSR population in children. Also, just clear the PASID bit from xfeatures if XSAVE is supported. This will have no effect on systems that do not have PASID support. It is virtually zero overhead because 'dst_fpu' was just written and the whole thing is cache hot. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Rewrite changelog (Dave Hansen). - Move xfeature tweaking into fpu_clone() and make it unconditional if XSAVE is supported (Dave Hansen). arch/x86/kernel/fpu/core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 8ea306b1bf8e..13fc0ea52237 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -518,6 +518,13 @@ int fpu_clone(struct task_struct *dst, unsigned long c= lone_flags) fpu_inherit_perms(dst_fpu); fpregs_unlock(); =20 + /* + * Children never inherit PASID state. + * Force it to have its init value: + */ + if (use_xsave()) + dst_fpu->fpstate->regs.xsave.header.xfeatures &=3D ~XFEATURE_MASK_PASID; + trace_x86_fpu_copy_src(src_fpu); trace_x86_fpu_copy_dst(dst_fpu); =20 --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD8E3C43217 for ; Fri, 17 Dec 2021 22:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231405AbhLQWCB (ORCPT ); Fri, 17 Dec 2021 17:02:01 -0500 Received: from mga11.intel.com ([192.55.52.93]:26498 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231137AbhLQWBu (ORCPT ); Fri, 17 Dec 2021 17:01:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778510; x=1671314510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UnMZO3dIpMprFJhYU1oJBcxLAM+pPp7MOtKZRkV+U7g=; b=WO26FheBg1Pje1/l8YZ3TYZHiCSumGFB8YBYuKbU/Golyi6ge2yFL2Tx dMd/hhAieM1qK14LoyORbd8ph9moEvAqUkeoh+YriV5HHb+YGGDD+0Axt MdanOQXPdKquM1vN4oTxm8UO5S77I2C2I+5g42Ieo1rrKkmBipnJsglJH mO+Pe+OQ8GK+Obz/PA5DOWujVT3xar4Rtx3IcHPmNK56JuxBDzl6QOwY9 k80RAI/mDi5KabIdHOLzsIt6ok+/iE2cLGRQxo4p/kH/+ISXq8yJ57Y9D 9BC25vFGczcu2iDetGGMkv0sUN87mAB7IkiNIF1Wr2W5Q0j3nN4UWGfeW g==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381600" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381600" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928102" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:49 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 07/11] sched: Define and initialize a flag to identify valid PASID in the task Date: Fri, 17 Dec 2021 22:01:32 +0000 Message-Id: <20211217220136.2762116-8-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Peter Zijlstra Add a new single bit field to the task structure to track whether this task has initialized the IA32_PASID MSR to the mm's PASID. Initialize the field to zero when creating a new task with fork/clone. Signed-off-by: Peter Zijlstra Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change condition to more accurate CONFIG_IOMMU_SVA (Jacob) include/linux/sched.h | 3 +++ kernel/fork.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/include/linux/sched.h b/include/linux/sched.h index 78c351e35fec..41a0b5703f94 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -933,6 +933,9 @@ struct task_struct { /* Recursion prevention for eventfd_signal() */ unsigned in_eventfd_signal:1; #endif +#ifdef CONFIG_IOMMU_SVA + unsigned pasid_activated:1; +#endif =20 unsigned long atomic_flags; /* Flags requiring atomic access. */ =20 diff --git a/kernel/fork.c b/kernel/fork.c index 3adad225cc09..cd297926b6f2 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -967,6 +967,10 @@ static struct task_struct *dup_task_struct(struct task= _struct *orig, int node) tsk->use_memdelay =3D 0; #endif =20 +#ifdef CONFIG_IOMMU_SVA + tsk->pasid_activated =3D 0; +#endif + #ifdef CONFIG_MEMCG tsk->active_memcg =3D NULL; #endif --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8803C4332F for ; Fri, 17 Dec 2021 22:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231431AbhLQWCD (ORCPT ); Fri, 17 Dec 2021 17:02:03 -0500 Received: from mga11.intel.com ([192.55.52.93]:26498 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231143AbhLQWBv (ORCPT ); Fri, 17 Dec 2021 17:01:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778511; x=1671314511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OBpDZUm4EngfnhF5Yo9KgToppXO+yZbVrmisYzFVZ8w=; b=jeD+ELrgGEEQDye6MYXpKMtQkZwxTbWSf5Npnp0u3wKMKIsD/FS6q8Jc dGxfAvICcsV65ucNThSoE0CBwuqkjeMSU1/1gr8eIJPSIAhb7dSj3kLQV F8+VF/N0bZflYCSp3Stit/MS5TxNMQ7l47JnfafsZ8tcxEscrEFpsZkVF Dg6kHTtQQa/iTfOw9FHDeXCbIQ6kQhJ1JEtqZJOVaSFGo9JNe9H55ucW9 C1ulXO+SFDPzFsFemVBWQAfHIK9HdFTGH6BDe1QbuMGnVsDoBiuX1vkIC VLSjmohLur8YBMtZb8Fatr1DEa3SC7N8VOIS9OaR7zP/V0yyCUXJWqvao w==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381601" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381601" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928104" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:50 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 08/11] x86/traps: Demand-populate PASID MSR via #GP Date: Fri, 17 Dec 2021 22:01:33 +0000 Message-Id: <20211217220136.2762116-9-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All tasks start with PASID state disabled. This means that the first time they execute an ENQCMD instruction they will take a #GP fault. Modify the #GP fault handler to check if the "mm" for the task has already been allocated a PASID. If so, try to fix the #GP fault by loading the IA32_PASID MSR. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Directly write IA32_PASID MSR in fixup while local IRQ is still disabled (Thomas) - Move #ifdef over to CONFIG_IOMMU_SVA since it is what defines mm->pasid and ->pasid_activated (Dave Hansen). - Rename try_fixup_pasid() -> try_fixup_enqcmd_gp(). This code really is highly specific to ENQCMD, not PASIDs (Dave Hansen). - Add lockdep assert and comment about context (Dave Hansen). - Re-flow the if() mess (Dave Hansen). arch/x86/kernel/traps.c | 55 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c9d566dcf89a..7ef00dee35be 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -39,6 +39,7 @@ #include #include #include +#include =20 #include #include @@ -559,6 +560,57 @@ static bool fixup_iopl_exception(struct pt_regs *regs) return true; } =20 +/* + * The unprivileged ENQCMD instruction generates #GPs if the + * IA32_PASID MSR has not been populated. If possible, populate + * the MSR from a PASID previously allocated to the mm. + */ +static bool try_fixup_enqcmd_gp(void) +{ +#ifdef CONFIG_IOMMU_SVA + u32 pasid; + + /* + * MSR_IA32_PASID is managed using XSAVE. Directly + * writing to the MSR is only possible when fpregs + * are valid and the fpstate is not. This is + * guaranteed when handling a userspace exception + * in *before* interrupts are re-enabled. + */ + lockdep_assert_irqs_disabled(); + + /* + * Hardware without ENQCMD will not generate + * #GPs that can be fixed up here. + */ + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) + return false; + + pasid =3D current->mm->pasid; + + /* + * If the mm has not been allocated a + * PASID, the #GP can not be fixed up. + */ + if (!pasid_valid(pasid)) + return false; + + /* + * Did this thread already have its PASID activated? + * If so, the #GP must be from something else. + */ + if (current->pasid_activated) + return false; + + wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); + current->pasid_activated =3D 1; + + return true; +#else + return false; +#endif +} + DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) { char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] =3D GPFSTR; @@ -567,6 +619,9 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) unsigned long gp_addr; int ret; =20 + if (user_mode(regs) && try_fixup_enqcmd_gp()) + return; + cond_local_irq_enable(regs); =20 if (static_cpu_has(X86_FEATURE_UMIP)) { --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33EFAC4321E for ; Fri, 17 Dec 2021 22:02:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbhLQWCH (ORCPT ); Fri, 17 Dec 2021 17:02:07 -0500 Received: from mga11.intel.com ([192.55.52.93]:26506 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbhLQWBw (ORCPT ); Fri, 17 Dec 2021 17:01:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778512; x=1671314512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=38m/Q2AQH9Kv2z7BUSt3cLQo4zzkwKxvDeDlsUIPs6Y=; b=fZhWndzYNf+obEbGwvxXTTQ1by0lyNl6vp9IqV7WhX6x869DgVEDyO93 g01aTeWt60rBhO0AXiX1qdURf9MxyliqS+w0teVoRdhFno+y5Nxu60HlH fjyXAcxamWFR5phFcgsSXv6Ep0NZoo/lcuEJ2KkAZ7Y6cvjJJA0/5IUs9 JHPPMR7bKx06dlLlj4/7PpaY0zi3TzpcafhKVKd510Nr8Rhw+OuEXvPc9 jPUHkytwHYRUVlqb4rsqMeYjNgQqePRtS77Nihzo3E8Tb+Lt9rA7gwfBb DPgKdT4dCHwvI8+RMSFVXSA/mIkmEwApV2MEiyPGbM/XUBKGdnvRJQCvy A==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381602" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381602" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928107" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:51 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 09/11] x86/cpufeatures: Re-enable ENQCMD Date: Fri, 17 Dec 2021 22:01:34 +0000 Message-Id: <20211217220136.2762116-10-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since ENQCMD is handled by #GP fix up, it can be re-enabled. The ENQCMD feature can only be used if CONFIG_INTEL_IOMMU_SVM is set. Add X86_FEATURE_ENQCMD to the disabled features mask as appropriate so that cpu_feature_enabled() can be used to check the feature. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Update the commit message (Tony). arch/x86/include/asm/disabled-features.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/as= m/disabled-features.h index 8f28fafa98b3..1231d63f836d 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -56,8 +56,11 @@ # define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) #endif =20 -/* Force disable because it's broken beyond repair */ -#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) +#ifdef CONFIG_INTEL_IOMMU_SVM +# define DISABLE_ENQCMD 0 +#else +# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) +#endif =20 #ifdef CONFIG_X86_SGX # define DISABLE_SGX 0 --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E70B4C4321E for ; Fri, 17 Dec 2021 22:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231481AbhLQWCF (ORCPT ); Fri, 17 Dec 2021 17:02:05 -0500 Received: from mga11.intel.com ([192.55.52.93]:26506 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbhLQWBw (ORCPT ); Fri, 17 Dec 2021 17:01:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778512; x=1671314512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WUETfejsiNGR9gILAkgt74/RWnHGbmhPzWPMpp74bp0=; b=Il+bB43Ak33zpq3/eSK8DrhhP//vZ2BIH8zirx4LW6OqQGTh+gSDjI6g 0VKMk47Aic2bBFl0hKtb50opQf6Ovhoc9oKeObg1JSSPTqzPk4C8cygub nFFAM1u9dJVzre+m6GR1SIon3gHrYMjK9cJjiD6DbHlLwfnQ5FH8dtvZ+ +JgwQ7jFoxLzHGC6qSdfiMQg2uFZ72B7u00ACTwCX4M0KbJlRjn9prlan 2utZzMz7hZu4rUn239R+qLrI+R0lEsWwg7sR2kQBG+DApNuK33TTvn8i8 TrzjplY/h8oUY+oFUhRY9MTAPtALxtA2JpYRO23tHh2Wr6rH1K7i1LHB2 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381604" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381604" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928110" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:51 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 10/11] tools/objtool: Check for use of the ENQCMD instruction in the kernel Date: Fri, 17 Dec 2021 22:01:35 +0000 Message-Id: <20211217220136.2762116-11-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ENQCMD implicitly accesses the PASID_MSR to fill in the pasid field of the descriptor being submitted to an accelerator. But there is no precise (and stable across kernel changes) point at which the PASID_MSR is updated from the value for one task to the next. Kernel code that uses accelerators must always use the ENQCMDS instruction which does not access the PASID_MSR. Check for use of the ENQCMD instruction in the kernel and warn on its usage. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Simplify handling ENQCMD (PeterZ and Josh) tools/objtool/arch/x86/decode.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decod= e.c index 4d6d7fc13255..11ffa0e53f84 100644 --- a/tools/objtool/arch/x86/decode.c +++ b/tools/objtool/arch/x86/decode.c @@ -112,7 +112,7 @@ int arch_decode_instruction(struct objtool_file *file, = const struct section *sec const struct elf *elf =3D file->elf; struct insn insn; int x86_64, ret; - unsigned char op1, op2, + unsigned char op1, op2, op3, rex =3D 0, rex_b =3D 0, rex_r =3D 0, rex_w =3D 0, rex_x =3D 0, modrm =3D 0, modrm_mod =3D 0, modrm_rm =3D 0, modrm_reg =3D 0, sib =3D 0, /* sib_scale =3D 0, */ sib_index =3D 0, sib_base =3D 0; @@ -139,6 +139,7 @@ int arch_decode_instruction(struct objtool_file *file, = const struct section *sec =20 op1 =3D insn.opcode.bytes[0]; op2 =3D insn.opcode.bytes[1]; + op3 =3D insn.opcode.bytes[2]; =20 if (insn.rex_prefix.nbytes) { rex =3D insn.rex_prefix.bytes[0]; @@ -491,6 +492,14 @@ int arch_decode_instruction(struct objtool_file *file,= const struct section *sec /* nopl/nopw */ *type =3D INSN_NOP; =20 + } else if (op2 =3D=3D 0x38 && op3 =3D=3D 0xf8) { + if (insn.prefixes.nbytes =3D=3D 1 && + insn.prefixes.bytes[0] =3D=3D 0xf2) { + /* ENQCMD cannot be used in the kernel. */ + WARN("ENQCMD instruction at %s:%lx", sec->name, + offset); + } + } else if (op2 =3D=3D 0xa0 || op2 =3D=3D 0xa8) { =20 /* push fs/gs */ --=20 2.34.1 From nobody Wed Jul 1 17:38:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 223BBC433EF for ; Fri, 17 Dec 2021 22:02:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231522AbhLQWCG (ORCPT ); Fri, 17 Dec 2021 17:02:06 -0500 Received: from mga11.intel.com ([192.55.52.93]:26506 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231181AbhLQWBw (ORCPT ); Fri, 17 Dec 2021 17:01:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639778512; x=1671314512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jOdSxuEtbkAQOM8wsD7B/5P8akQ7YsOBzOXhYbomw+g=; b=jLdSpHPkPFRJOXBaJuVcQ/Pa3Vdia25j5Kfdk+imj/sWXyUhOCjgvpYo x/JQLOd4xHNp+4nfy9UKNjQSBSYFrsiNlmrHava8GmBAJJrgrSeRLiO50 bQBFI8Q6SCaZ0bIKjNz3PPw35AlPRrlFnVfx6H5FVX0iYrUNSnm9WzAoM z1U0+7OyxZ8+HLR7N+gdwMT6iLg9hgg+THpuEgKqaXpIYfmYx3QmjQ2ZB kZiiGtNIfhRoZQJfeo+0WxiMEd4BU2NLiAuTxqBZnTd48Zwr7sYULdzi/ ZWBy13OacXU8DyMu2PO1MZX9tFVUfkLOkR3g/AZrYKEQcXERwuH3c8ItD Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10201"; a="237381605" X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="237381605" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2021 14:01:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,214,1635231600"; d="scan'208";a="506928113" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2021 14:01:51 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Dave Hansen" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v2 11/11] docs: x86: Change documentation for SVA (Shared Virtual Addressing) Date: Fri, 17 Dec 2021 22:01:36 +0000 Message-Id: <20211217220136.2762116-12-fenghua.yu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217220136.2762116-1-fenghua.yu@intel.com> References: <20211217220136.2762116-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since allocating, freeing and fixing up PASID are changed, the documentation is updated to reflect the changes. Originally-by: Ashok Raj Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Update life cycle info (Tony and Thomas). - Update initial PASID value to INVALID_IOASID on fork(). Documentation/x86/sva.rst | 58 +++++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 12 deletions(-) diff --git a/Documentation/x86/sva.rst b/Documentation/x86/sva.rst index 076efd51ef1f..92341f26e525 100644 --- a/Documentation/x86/sva.rst +++ b/Documentation/x86/sva.rst @@ -104,18 +104,52 @@ The MSR must be configured on each logical CPU before= any application thread can interact with a device. Threads that belong to the same process share the same page tables, thus the same MSR value. =20 -PASID is cleared when a process is created. The PASID allocation and MSR -programming may occur long after a process and its threads have been creat= ed. -One thread must call iommu_sva_bind_device() to allocate the PASID for the -process. If a thread uses ENQCMD without the MSR first being populated, a = #GP -will be raised. The kernel will update the PASID MSR with the PASID for all -threads in the process. A single process PASID can be used simultaneously -with multiple devices since they all share the same address space. - -One thread can call iommu_sva_unbind_device() to free the allocated PASID. -The kernel will clear the PASID MSR for all threads belonging to the proce= ss. - -New threads inherit the MSR value from the parent. +PASID Life Cycle Management +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +PASID is initialized as INVALID_IOASID (-1) when a process is created. + +Only processes that access SVA-capable devices need to have a PASID +allocated. This allocation happens when a process opens/binds an SVA-capab= le +device but finds no PASID for this process. Subsequent binds of the same, = or +other devices will share the same PASID. + +Although the PASID is allocated to the process by opening a device, +it is not active in any of the threads of that process. It's loaded to the +IA32_PASID MSR lazily when a thread tries to submit a work descriptor +to a device using the ENQCMD. + +That first access will trigger a #GP fault because the IA32_PASID MSR +has not been initialized with the PASID value assigned to the process +when the device was opened. The Linux #GP handler notes that a PASID has +been allocated for the process, and so initializes the IA32_PASID MSR +and returns so that the ENQCMD instruction is re-executed. + +On fork(2) or exec(2) the PASID is removed from the process as it no +longer has the same address space that it had when the device was opened. + +On clone(2) the new task shares the same address space, so will be +able to use the PASID allocated to the process. The IA32_PASID is not +preemptively initialized as the PASID value might not be allocated yet or +the kernel does not know whether this thread is going to access the device +and the cleared IA32_PASID MSR reduces context switch overhead by xstate +init optimization. Since #GP faults have to be handled on any threads that +were created before the PASID was assigned to the mm of the process, newly +created threads might as well be treated in a consistent way. + +Due to complexity of freeing the PASID and clearing all IA32_PASID MSRs in +all threads in unbind, free the PASID lazily only on mm exit. Track the +PASID's reference count in the following way: + +- Initialize the PASID's reference to 1 when the PASID is first allocated + to the mm. The reference is held for the rest life time of the mm until + it's dropped to 0 and the PASID is freed on mm exit. + +If a process does a close(2) of the device file descriptor and munmap(2) +of the device MMIO portal, then the driver will unbind the device. The +PASID is still marked VALID in the PASID_MSR for any threads in the +process that accessed the device. But this is harmless as without the +MMIO portal they cannot submit new work to the device. =20 Relationships =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.34.1