From nobody Wed Jul 1 17:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 282B5C433F5 for ; Fri, 17 Dec 2021 19:57:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240765AbhLQT5p (ORCPT ); Fri, 17 Dec 2021 14:57:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240721AbhLQT5m (ORCPT ); Fri, 17 Dec 2021 14:57:42 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19F05C061574; Fri, 17 Dec 2021 11:57:42 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id i22so6003016wrb.13; Fri, 17 Dec 2021 11:57:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=apd7aS6mQEWyiCJ+igKGaGnuj7ZsZTnhdEXozJsLTpI=; b=nJehCbTVWBq6MA1FZurR7lCR633aGB4SWB2SwYofRJzk4ulMeghQXDZN3TnBO49ld2 OcGWxqaAo9JuSlBS8vvl9k4gQjcG+9K9Rg+4As6D94DvtD3ByKkhO3MI4qglYFToxtNE bbgEieryg3QUFq7kNa2smvGlzprzRsVhQC7tkK/preVAMSBKuTyCJgGWk+8KKLO5u/TE OhNZx5w2z7vt0ehUCCkQJGPfqp0qUAf9LEgLol94HdTr44RT9lHpmfXPADwrE96ijnFK VoVvFuLiv8XRM90bdTvKvWBiEoOh9Z5Bo7qY5AQ/q/piWceu2l8sMxXFrNwaEQK/fbZv suqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=apd7aS6mQEWyiCJ+igKGaGnuj7ZsZTnhdEXozJsLTpI=; b=Kn5p/SMxV3nbW7Dfh1YYQ+PAJaNPFwhjhsddg/i1IyUt8Au078D0s7cUW84NNXYKFO 7pEdKyW/99F2uiOrBdWu66y5HZ6yEOAWyUVrhl3seQLLMJM4SAGheQsqrZmsQiqTSMIg JpfVAYAAWYP2kIDi9f8Y9irpwUimJptusiqPhV8JZCn02DTZPp5qPLuLE0ShRP9ubKeN W4e7GIx/VSMTlPx6YfedpXdTyNjBcFv+UnhBNwekz0WWz0s2S9dfBi0Xwy3MNen8nKMB DvLumQ7TKVjPvPZA3XbVpE0w9WZ6w+Gv1N8LKeAJxFUDAT6GGBU8NVSziEcphvBPabxr Mgsg== X-Gm-Message-State: AOAM531S6S4cHryftvIU2ywPN6iJaIhlRixJrX5L7cc59E8qI/qZo5JU KUsnOhdE2TnxdmgcCcXj4WuYHGKhRs4= X-Google-Smtp-Source: ABdhPJwGwRmaUNvabaDcONqGBVHu/OP6PxTRJo3VOgHQp+NEcfSu7kSNu11y9EB37WtLzHSFDq/E2A== X-Received: by 2002:a5d:448e:: with SMTP id j14mr3505768wrq.42.1639771060314; Fri, 17 Dec 2021 11:57:40 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id h15sm13178698wmq.32.2021.12.17.11.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:39 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] clocksource: Add MStar MSC313e timer support Date: Fri, 17 Dec 2021 20:57:22 +0100 Message-Id: <20211217195727.8955-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these are free running 32-bit increasing counters and can generate interrupts. Based onto a maximum value register, each timer can either count from 0 to max, one time then stop (which generates interrupts) or can count from 0 to max and then roll. This commit adds basic support for these timers, the first timer block being used as clocksource/sched_clock and delay, while the others will be used as clockevents. Signed-off-by: Romain Perier Co-developed-by: Daniel Palmer Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + drivers/clocksource/Kconfig | 9 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-msc313e.c | 244 ++++++++++++++++++++++++++++ 4 files changed, 255 insertions(+) create mode 100644 drivers/clocksource/timer-msc313e.c diff --git a/MAINTAINERS b/MAINTAINERS index 43007f2d29e0..4dbc122c7937 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2291,6 +2291,7 @@ F: Documentation/devicetree/bindings/gpio/mstar,msc31= 3-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ +F: drivers/clocksource/timer-msc313e.c F: drivers/gpio/gpio-msc313.c F: drivers/rtc/rtc-msc313.c F: drivers/watchdog/msc313e_wdt.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index f65e31bab9ae..ba46d6860e2d 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -671,6 +671,15 @@ config MILBEAUT_TIMER help Enables the support for Milbeaut timer driver. =20 +config MSC313E_TIMER + bool "MSC313E timer driver" if COMPILE_TEST + select TIMER_OF + select CLKSRC_MMIO + help + Enables support for the MStar MSC313E timer driver. + This provides access to multiple interrupt generating + programmable 32-bit free running incrementing counters. + config INGENIC_TIMER bool "Clocksource/timer using the TCU in Ingenic JZ SoCs" default MACH_INGENIC diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index c17ee32a7151..fa5f624eadb6 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_CSKY_MP_TIMER) +=3D timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) +=3D timer-gx6605s.o obj-$(CONFIG_HYPERV_TIMER) +=3D hyperv_timer.o obj-$(CONFIG_MICROCHIP_PIT64B) +=3D timer-microchip-pit64b.o +obj-$(CONFIG_MSC313E_TIMER) +=3D timer-msc313e.o diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/time= r-msc313e.c new file mode 100644 index 000000000000..154e73444a0c --- /dev/null +++ b/drivers/clocksource/timer-msc313e.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MStar timer driver + * + * Copyright (C) 2021 Daniel Palmer + * Copyright (C) 2021 Romain Perier + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARM +#include +#endif + +#include "timer-of.h" + +#define TIMER_NAME "msc313e_timer" + +#define MSC313E_REG_CTRL 0x00 +#define MSC313E_REG_CTRL_TIMER_EN BIT(0) +#define MSC313E_REG_CTRL_TIMER_TRIG BIT(1) +#define MSC313E_REG_CTRL_TIMER_INT_EN BIT(8) +#define MSC313E_REG_TIMER_MAX_LOW 0x08 +#define MSC313E_REG_TIMER_MAX_HIGH 0x0c +#define MSC313E_REG_COUNTER_LOW 0x10 +#define MSC313E_REG_COUNTER_HIGH 0x14 + +#define TIMER_SYNC_TICKS 3 + +#ifdef CONFIG_ARM +struct msc313e_delay { + void __iomem *base; + struct delay_timer delay; +}; +static struct msc313e_delay msc313e_delay; +#endif + +static void __iomem *msc313e_clksrc; + +static void msc313e_timer_stop(void __iomem *base) +{ + writew(0, base + MSC313E_REG_CTRL); +} + +static void msc313e_timer_start(void __iomem *base, bool periodic) +{ + u16 reg; + + reg =3D readw(base + MSC313E_REG_CTRL); + if (periodic) + reg |=3D MSC313E_REG_CTRL_TIMER_EN; + else + reg |=3D MSC313E_REG_CTRL_TIMER_TRIG; + writew(reg | MSC313E_REG_CTRL_TIMER_INT_EN, base + MSC313E_REG_CTRL); +} + +static void msc313e_timer_setup(void __iomem *base, unsigned long delay) +{ + unsigned long flags; + + local_irq_save(flags); + writew(delay >> 16, base + MSC313E_REG_TIMER_MAX_HIGH); + writew(delay & 0xffff, base + MSC313E_REG_TIMER_MAX_LOW); + local_irq_restore(flags); +} + +static unsigned long msc313e_timer_current_value(void __iomem *base) +{ + unsigned long flags; + u16 l, h; + + local_irq_save(flags); + l =3D readw(base + MSC313E_REG_COUNTER_LOW); + h =3D readw(base + MSC313E_REG_COUNTER_HIGH); + local_irq_restore(flags); + + return (((u32)h) << 16 | l); +} + +static int msc313e_timer_clkevt_shutdown(struct clock_event_device *evt) +{ + struct timer_of *timer =3D to_timer_of(evt); + + msc313e_timer_stop(timer_of_base(timer)); + + return 0; +} + +static int msc313e_timer_clkevt_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *timer =3D to_timer_of(evt); + + msc313e_timer_stop(timer_of_base(timer)); + msc313e_timer_start(timer_of_base(timer), false); + + return 0; +} + +static int msc313e_timer_clkevt_set_periodic(struct clock_event_device *ev= t) +{ + struct timer_of *timer =3D to_timer_of(evt); + + msc313e_timer_stop(timer_of_base(timer)); + msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer)); + msc313e_timer_start(timer_of_base(timer), true); + + return 0; +} + +static int msc313e_timer_clkevt_next_event(unsigned long evt, struct clock= _event_device *clkevt) +{ + struct timer_of *timer =3D to_timer_of(clkevt); + + msc313e_timer_stop(timer_of_base(timer)); + msc313e_timer_setup(timer_of_base(timer), evt); + msc313e_timer_start(timer_of_base(timer), false); + + return 0; +} + +static irqreturn_t msc313e_timer_clkevt_irq(int irq, void *dev_id) +{ + struct clock_event_device *evt =3D dev_id; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static u64 msc313e_timer_clksrc_read(struct clocksource *cs) +{ + return msc313e_timer_current_value(msc313e_clksrc) & cs->mask; +} + +#ifdef CONFIG_ARM +static unsigned long msc313e_read_delay_timer_read(void) +{ + return msc313e_timer_current_value(msc313e_delay.base); +} +#endif + +static u64 msc313e_timer_sched_clock_read(void) +{ + return msc313e_timer_current_value(msc313e_clksrc); +} + +static struct clock_event_device msc313e_clkevt =3D { + .name =3D TIMER_NAME, + .rating =3D 300, + .features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown =3D msc313e_timer_clkevt_shutdown, + .set_state_periodic =3D msc313e_timer_clkevt_set_periodic, + .set_state_oneshot =3D msc313e_timer_clkevt_set_oneshot, + .tick_resume =3D msc313e_timer_clkevt_shutdown, + .set_next_event =3D msc313e_timer_clkevt_next_event, +}; + +static int __init msc313e_clkevt_init(struct device_node *np) +{ + int ret; + struct timer_of *to; + + to =3D kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags =3D TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->of_irq.handler =3D msc313e_timer_clkevt_irq; + ret =3D timer_of_init(np, to); + if (ret) + return ret; + + msc313e_clkevt.cpumask =3D cpu_possible_mask; + msc313e_clkevt.irq =3D to->of_irq.irq; + to->clkevt =3D msc313e_clkevt; + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), + TIMER_SYNC_TICKS, 0xffffffff); + return 0; +} + +static int __init msc313e_clksrc_init(struct device_node *np) +{ + struct timer_of to =3D { 0 }; + int ret; + u16 reg; + + to.flags =3D TIMER_OF_BASE | TIMER_OF_CLOCK; + ret =3D timer_of_init(np, &to); + if (ret) + return ret; + + msc313e_clksrc =3D timer_of_base(&to); + reg =3D readw(msc313e_clksrc + MSC313E_REG_CTRL); + reg |=3D MSC313E_REG_CTRL_TIMER_EN; + writew(reg, msc313e_clksrc + MSC313E_REG_CTRL); + +#ifdef CONFIG_ARM + msc313e_delay.base =3D timer_of_base(&to); + msc313e_delay.delay.read_current_timer =3D msc313e_read_delay_timer_read; + msc313e_delay.delay.freq =3D timer_of_rate(&to); + + register_current_timer_delay(&msc313e_delay.delay); +#endif + + sched_clock_register(msc313e_timer_sched_clock_read, 32, timer_of_rate(&t= o)); + return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rat= e(&to), 300, 32, + msc313e_timer_clksrc_read); +} + +static int __init msc313e_timer_init(struct device_node *np) +{ + int ret =3D 0; + static int num_called; + + switch (num_called) { + case 0: + ret =3D msc313e_clksrc_init(np); + if (ret) + return ret; + break; + + default: + ret =3D msc313e_clkevt_init(np); + if (ret) + return ret; + break; + } + + num_called++; + + return 0; +} + +TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); --=20 2.34.1 From nobody Wed Jul 1 17:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB953C433EF for ; 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Fri, 17 Dec 2021 11:57:40 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] clocksource: msc313e: Add support for ssd20xd-based platforms Date: Fri, 17 Dec 2021 20:57:23 +0100 Message-Id: <20211217195727.8955-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On SSD20X family SoCs the timers are connected to a 432MHz clock instead of 12MHz that all the previous chips used. There is no way to reduce or divide these clocks in the clktree yet as we do not know exactly where the 432MHz clock comes from but it is enabled at boot. The SSD20X timers have an input clock divider within the timer itself to configure the frequency. timer0 is preconfigured at power up to run at 12MHz so it is backwards compatible and doesn't need special handling right now. timer1 and timer2 run at 432Mhz at power up so are not backward compatible. This commit adds support for the input clock divider register and sets timer1 and timer2 to run at 48Mhz for clockevents. Signed-off-by: Romain Perier --- drivers/clocksource/timer-msc313e.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/time= r-msc313e.c index 154e73444a0c..54c54ca7c786 100644 --- a/drivers/clocksource/timer-msc313e.c +++ b/drivers/clocksource/timer-msc313e.c @@ -33,7 +33,9 @@ #define MSC313E_REG_TIMER_MAX_HIGH 0x0c #define MSC313E_REG_COUNTER_LOW 0x10 #define MSC313E_REG_COUNTER_HIGH 0x14 +#define MSC313E_REG_TIMER_DIVIDE 0x18 =20 +#define MSC313E_CLK_DIVIDER 9 #define TIMER_SYNC_TICKS 3 =20 #ifdef CONFIG_ARM @@ -179,6 +181,12 @@ static int __init msc313e_clkevt_init(struct device_no= de *np) if (ret) return ret; =20 + if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) { + to->of_clk.rate =3D clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period =3D DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DI= VIDE); + } + msc313e_clkevt.cpumask =3D cpu_possible_mask; msc313e_clkevt.irq =3D to->of_irq.irq; to->clkevt =3D msc313e_clkevt; @@ -242,3 +250,4 @@ static int __init msc313e_timer_init(struct device_node= *np) } =20 TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); +TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init); --=20 2.34.1 From nobody Wed Jul 1 17:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DBE7C433F5 for ; Fri, 17 Dec 2021 19:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240823AbhLQT5v (ORCPT ); Fri, 17 Dec 2021 14:57:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240773AbhLQT5o (ORCPT ); Fri, 17 Dec 2021 14:57:44 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1399AC061746; Fri, 17 Dec 2021 11:57:44 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id t26so6093034wrb.4; Fri, 17 Dec 2021 11:57:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y6q77+5UM8ZlyyCHC/ie2KjcIve/mAf7JTnLDOGgmIY=; b=Qt5BHOEBZcavrTAAJ+ZVSjoDvN+qCazFSMAAvFPPG9B5sVtc4K9wQ+nwzRyeztHT1J r9aFzl45q5oi3nDwZuNz7eAXGs0rCioFhBW+QMuBIynqWVd1vZANe2YIEXkwU6+bOK7m Ezz5XwFQkPgUhjTzpxs1KPEayKSKY8YzpN9Zss0barQPeyyTwxyCyKaKalt3igBS1j7J pu6s0+hUkD6Sz22ILGF3nFdmNZ0sv370Bwm0j0VGy+vglMV5hgkQOtdfoOOkhcoCGh6A IbAR+1ZRJc5/7Bke7WkFCMoX6XS3+ah/8DOFS/gz+yWKv17vR7qQxMxdSYPxCQLy/Zyb bnKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y6q77+5UM8ZlyyCHC/ie2KjcIve/mAf7JTnLDOGgmIY=; b=eISTXHKbY3jWDrf63aO8AixM8IMzIbmBoghbDh5Y2zaAiqNIuRKFfy7Dj77DiZjCzM AHCef6+esm/x7JO5dYYpcRv42hCzSuuIIaDSmwnfrA1N9+PUT/iQvXFNyHaLyBWlOPfN dXfL5SwR3H+iFyw10FLH2f80+I1fYJlGPQcaEUkJ9tmWV3md4Soz3/KbYSDu9ci8wHVn VRbugLdvLKEzAR0vFSWcf96dhhyOc3NgMWmNiZ8u94k0RBuXGwQjoGWbX2/hCddjmpiE q0Fcop7ob4t3H3TEVcg36VB129CU52Qr+gS7xIDvm/0Z/hGJo9HOHj893TToK8B6Chm/ Sa2Q== X-Gm-Message-State: AOAM533objY5ls/eMnaz22j0Qa2TePihFtBz99ubhzzLzPzM5YnyFiTU 29jh3DiAEDfRWcZx2tAC4XmR3tB3+y8= X-Google-Smtp-Source: ABdhPJzsgwE6dgUIhbo8IjDc9nszMSuySG0oe80qqQ9FAF6H7181TRhaf7OLKv75Zk/MWo+622wdww== X-Received: by 2002:a5d:5850:: with SMTP id i16mr3768157wrf.410.1639771062339; Fri, 17 Dec 2021 11:57:42 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id d15sm10781590wri.50.2021.12.17.11.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:41 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] ARM: mstar: Select MSC313E_TIMER Date: Fri, 17 Dec 2021 20:57:24 +0100 Message-Id: <20211217195727.8955-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the ARCH_MSTARV7 have timers that can act as clocksource or clockevents so select the corresponding driver. Signed-off-by: Romain Perier --- arch/arm/mach-mstar/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index cd300eeedc20..d079d567bb72 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -3,6 +3,7 @@ menuconfig ARCH_MSTARV7 depends on ARCH_MULTI_V7 select ARM_GIC select ARM_HEAVY_MB + select MSC313E_TIMER select MST_IRQ select MSTAR_MSC313_MPLL help --=20 2.34.1 From nobody Wed Jul 1 17:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C250CC433EF for ; Fri, 17 Dec 2021 19:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240852AbhLQT5z (ORCPT ); Fri, 17 Dec 2021 14:57:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240779AbhLQT5p (ORCPT ); Fri, 17 Dec 2021 14:57:45 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC8F6C06173E; Fri, 17 Dec 2021 11:57:44 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id j9so6174165wrc.0; Fri, 17 Dec 2021 11:57:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w4WnYopJ+MjFxrLG5jbdWepbHL1AIT2pQAOmcq4aOS0=; b=KWgq/hjsNb7oTDTvs0OdRsT1MMm3cRHX9ZlorpSz6CWiWlJhmuWYu+HfmZw7Wbwfsm SND6nOH8vhG/evtVi2C+9ODuEUTkkDLvQxVOF+pSWFqJinZxJbcdcZ6GTIhcs8yCh1Tl Ihv0HxEKKn0fYYR60AOZwJhlhzqIWMNGsG+7ODKbTPyxpqVWncE4j/u9Xs48aWw4sp1d lCpL6mv/Ghx3deihQtpMBYynOiPZmdTYBMlb/1pI8RH6qnRUGVTjuehm8nzGZ8RZM4TY Z1kVewZjowp0GM6NE+92Ddqfdp5elSZebHb0jdSkZNV9BItfxh/jQf5pDSRg4cBpjFM9 tivA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w4WnYopJ+MjFxrLG5jbdWepbHL1AIT2pQAOmcq4aOS0=; b=ODKmUre2w7jFGiqSIMbJMNFl0fs3xunAULCtz+v1DBVHWzgpN23efyrdSjH5K3e2nx QBsyAaaRlky8o929ty21AKZebJGzn3CzYk3jsk+tKGt7W27r8Fo9YubwjBqgPWNCLDwU HcUg95neaTmBTA2+v+L/0pIGwefkyjgiOm2EalRU6uPWqtvpxWt3KyJ2CRp9OqMel3y+ 9hcDtZqv5ZUNmYHmXsFAmcWQ9USlQjgJOJU2kEvXoULQ0BVeEW5q3ZocYf/Bed3DxczL ygGrpwdWM6HlFPby2DnSIWnwiOJwsfA540OgYlz8hZIZVJgdvtYdNFolKG7mS9dk5ThT VrwQ== X-Gm-Message-State: AOAM530gSll8T0s2/Ig7RCkJNDSgUporA+kt1+HWex6kxCw7JN/VZZrR EihZYYxWoAVYUnXe7Ekf1gw= X-Google-Smtp-Source: ABdhPJz40c2vF2seBwepqXHI4jkPlyJ6XkF5fWJBc0opI3YJhOFcBgsN1oqCPu+GQPFH59KHQWxjtQ== X-Received: by 2002:a05:6000:1a41:: with SMTP id t1mr3829849wry.261.1639771063324; Fri, 17 Dec 2021 11:57:43 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id y7sm7828848wrw.55.2021.12.17.11.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:42 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 4/6] dt-bindings: timer: Add Mstar MSC313e timer devicetree bindings documentation Date: Fri, 17 Dec 2021 20:57:25 +0100 Message-Id: <20211217195727.8955-5-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the documentation for the devicetree bindings of the Mstar MSC313e timer driver, found from MSC313e SoCs and newer. Signed-off-by: Romain Perier Reviewed-by: Rob Herring --- .../bindings/timer/mstar,msc313e-timer.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/mstar,msc313e-t= imer.yaml diff --git a/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.ya= ml b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml new file mode 100644 index 000000000000..03d5dba5d5b3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/mstar,msc313e-timer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mstar MSC313e Timer Device Tree Bindings + +maintainers: + - Daniel Palmer + - Romain Perier + +properties: + compatible: + enum: + - mstar,msc313e-timer + - sstar,ssd20xd-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + timer@6040 { + compatible =3D "mstar,msc313e-timer"; + reg =3D <0x6040 0x40>; + clocks =3D <&xtal_div2>; + interrupts-extended =3D <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; +... --=20 2.34.1 From nobody Wed Jul 1 17:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8BBFC433EF for ; Fri, 17 Dec 2021 19:57:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232807AbhLQT5x (ORCPT ); Fri, 17 Dec 2021 14:57:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240788AbhLQT5q (ORCPT ); Fri, 17 Dec 2021 14:57:46 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AB80C061401; Fri, 17 Dec 2021 11:57:46 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id j140-20020a1c2392000000b003399ae48f58so4783784wmj.5; Fri, 17 Dec 2021 11:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eU0XGPi4uBhPUtyGCEgXF/C3mA2MpO37zRIQErCawvo=; b=f9VKS4gPYA3Bst20TJUlMjQI5/yet1jmgxsDXqhLiDT1wAXa5vbUy+yT9pHpv+D9T7 RSbOMRYPqqV0KXJOstjbEa8DSH1ZHijqX+EUve2ebiEtiAUMtlr/kVvqVl/IyaUBDA4J JrTi715WFR7b5VHZTIexXlBh9aus6csf4oSHs9GV76cWI41D9wjIV3pIhsp1a+fAHFHb VFdj4Yjmf3JL+aT85WzUrqfA6wObE4SUBTJlibrbUo/mNn9qIAecOiuI+SVXnb2QK3sq iSHrjqSJ9jr6yOxrzJ3NfkW8QUJMqm57W9Wu34GO1hbTbAfTR0DIbEifUhR5i/Vp4yQB l2YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eU0XGPi4uBhPUtyGCEgXF/C3mA2MpO37zRIQErCawvo=; b=sLT94xt99HRUAVcldmQmyknVWGZEOM6kTEqHO2KuXnyv3at3Dx0mEK1xtIGDKzIB0F JSb7kQaIbqXnDLSojvRFZpMN1P0bxqiMFBV7WCJpn6t2TIurh7FkToNACpiguw4XFq/j aaRW8sav98ztshChV7pLFicm0FGtCjwxNtoeSVsrxdC1qfvCEKW2iFM2Ns8NkEpbXGZb SfXNn7lAqE37pb4+X8MEqRCwKwdKUzR6fCI88lEEEdF7OOMjO5bc4Q+2JTsU60C06YF8 xhZWHR8yRiORWtphCJGtaNSfQxuk2FS40uzVyp2+m3hJKVPkfjPnNE0Zfsur9I9z5QJR 3/zg== X-Gm-Message-State: AOAM531Kwdg5u1h7GwgkcLUgXXVPCH6BEZCBX7la0xcrCbYyRcolJEkl qoTLnxUU0DL9xCB+YaLRvApSpYJxn7ioZg== X-Google-Smtp-Source: ABdhPJxzAMjIxX2CXI+2wbGHfE/1VAILVFrQsoQogotGZM/HaypI7k2Q17zUtBJT70jYx40zjbJY/A== X-Received: by 2002:a1c:f418:: with SMTP id z24mr10925271wma.95.1639771064308; Fri, 17 Dec 2021 11:57:44 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id i17sm9340951wmq.48.2021.12.17.11.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:43 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] ARM: dts: mstar: Add timers device nodes Date: Fri, 17 Dec 2021 20:57:26 +0100 Message-Id: <20211217195727.8955-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the definition of the timers device node. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.d= tsi index 89ebfe4f29da..7ede4cec0af9 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -123,6 +123,26 @@ watchdog@6000 { clocks =3D <&xtal_div2>; }; =20 + timer@6040 { + compatible =3D "mstar,msc313e-timer"; + reg =3D <0x6040 0x40>; + clocks =3D <&xtal_div2>; + interrupts-extended =3D <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer1: timer@6080 { + compatible =3D "mstar,msc313e-timer"; + reg =3D <0x6080 0x40>; + clocks =3D <&xtal_div2>; + interrupts-extended =3D <&intc_fiq GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer2: timer@60c0 { + compatible =3D "mstar,msc313e-timer"; + reg =3D <0x60c0 0x40>; + clocks =3D <&xtal_div2>; + interrupts-extended =3D <&intc_fiq GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; =20 intc_fiq: interrupt-controller@201310 { compatible =3D "mstar,mst-intc"; --=20 2.34.1 From nobody Wed Jul 1 17:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 168A6C433FE for ; Fri, 17 Dec 2021 19:57:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240793AbhLQT54 (ORCPT ); Fri, 17 Dec 2021 14:57:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbhLQT5r (ORCPT ); Fri, 17 Dec 2021 14:57:47 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B7DC061574; Fri, 17 Dec 2021 11:57:47 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id j18so6130238wrd.2; Fri, 17 Dec 2021 11:57:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pdysGXdTy+3TZBw7R9cw+LisV1Ndm6W0415d+TGMhCY=; b=pxeagsDGNrQVitn44DRzQfGy8d+GGjGuKOTiIAMdIHeOrYgHIcpNBQg4F0wK5FTdL8 3Ae6wxj6PfDehFJrQ6kzOxVYC/0PIoUeRPU8QpCUGND7FawfV7/oxPwUVHBvgnUwLn+q d3CC0s6Jmp0k0ndPYoosFWXklvQIDUeaW0T7ZPHSiTEl3Nm2ANK/+emk+yqjuHoB6kHK VBGx8bw4g+ROTudwT2OKxuQ4Iv6+wDvJSIepjlNRc9Mp9sF5pnPJ/L66ob7ZL7Cz5VP/ BsPBXD6MCQ2DBjeX/AytWi3Iu/qdijQVBZlZouMAVx0/oMdPVyXFfawugm+JJGV2wDJz YynA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pdysGXdTy+3TZBw7R9cw+LisV1Ndm6W0415d+TGMhCY=; b=NebIsSSe7a3o8oD3q6GaNvtbOtQQ4KXPUYnQZVVbtqjbaBVKq9ps/sy14X1SW0cj8I gvRzZYk4aShr+ulyXIyt/trdd411Rl+9fpTaqROG3jCAaXnsfw7VlgFVeCB2rPTA8/jG R2+V5QTYOMnMLyHQSJtO60r/KBzjL4SQ2FSsZlceKsEoYE2J0MUd2KAAdY57PEVsNe81 TtHhdSC3dGIAvtnwzf3+VM9HX05TPg9bJSyDEw3bnxjVjnPdXOwRW5vNEJvJQOq9Q5YN QlwNK0tViL4aEs5k1mXCA0rn0CqGKpJ9mZqYmegSmwjrAr2fcaKhlt2bvo1zcYa08mmF 3hMw== X-Gm-Message-State: AOAM532/ZPaVhCAE9IJIzNow/RQdV6wtpiqt7W4BlsblXIhJHA3ylYxi 9XtujZVn4uppp7dSmv9DYhCg505+yjZB2A== X-Google-Smtp-Source: ABdhPJwYyBxcJ045RgxyVdQRDDQgg/UGebYXwCxLP6/MWl/YtWWo/VehH1bzR3fhgk0gmpvCasNKUw== X-Received: by 2002:adf:efc6:: with SMTP id i6mr3689981wrp.428.1639771065406; Fri, 17 Dec 2021 11:57:45 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id y15sm11667631wry.72.2021.12.17.11.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 11:57:45 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] ARM: dts: mstar: Switch to compatible "sstar,ssd20xd-timer" on infinity2m Date: Fri, 17 Dec 2021 20:57:27 +0100 Message-Id: <20211217195727.8955-7-romain.perier@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217195727.8955-1-romain.perier@gmail.com> References: <20211217195727.8955-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This defines the real oscillators as input of timer1 and timer2 and switch to "sstar,ssd20xd-timer". Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/ms= tar-infinity2m.dtsi index 6d4d1d224e96..080a18b9effb 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -6,6 +6,14 @@ =20 #include "mstar-infinity.dtsi" =20 +/ { + clk_timer: timer_clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <432000000>; + }; +}; + &cpus { cpu1: cpu@1 { device_type =3D "cpu"; @@ -20,3 +28,13 @@ smpctrl: smpctrl@204000 { status =3D "disabled"; }; }; + +&timer1 { + compatible =3D "sstar,ssd20xd-timer"; + clocks =3D <&clk_timer>; +}; + +&timer2 { + compatible =3D "sstar,ssd20xd-timer"; + clocks =3D <&clk_timer>; +}; --=20 2.34.1