From nobody Wed Jul 1 17:39:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3605EC433EF for ; Fri, 17 Dec 2021 15:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238565AbhLQPzx (ORCPT ); Fri, 17 Dec 2021 10:55:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235120AbhLQPzu (ORCPT ); Fri, 17 Dec 2021 10:55:50 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DB17C061401 for ; Fri, 17 Dec 2021 07:55:48 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id z5so9553897edd.3 for ; Fri, 17 Dec 2021 07:55:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7755/oSm9xb3xyECSk0fLF9ekbC+MSg548pl7mm+dvs=; b=PM52FyxxKrfr/YfvOpCGnn5QuSEdpLGLGAhIIZ+rf917QjULuP+7ypuzS7SziIy+LU 7DfuYuYmD3hwKC61MUpVCDa4Pr0ugi7yfEiGfWfok0H6kQLHM4XPOkGbjl9vL4zuFVri 0OK2jLHMthBDAFekKONF33uJjMzXKgpWdKbng= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7755/oSm9xb3xyECSk0fLF9ekbC+MSg548pl7mm+dvs=; b=uP7vWxbxU3aqCCYbqEwYGRXbkRvU+HWsXo0UkdYu7Um2V1JYIjJ/iUJt+PzAqE8o3M scwCgK92WZC1Ln7gLNcsE9XmhzDW8iaF6LtkpW81d+gHsTcm64FRE2h9gzQQcew9G7Y3 QUEH9X8SIC3bV7FKOUCbBzuH1NDQOgcy7+mYzNO8evTQ2TOFpy6PM0YaxD5dbFkZwelO PGAs1FL8w3ghkyJNUZJcHDcu2lSV/6mRMPwHsqBPdrM/l38ZBRNBi33Zby6XAdF6pFUR FasEa4YE1ZvFtHY4kS7pWrYIdxSchd2cZIS4RhfpsZOOUlED77olaqLlNcza8t429+gX 7K9g== X-Gm-Message-State: AOAM530lomtHDiqh2+jTyFPzcyDtj64lkji3h8oTXu0FPDsgIUHUgIDa PIiqWrcpxpsvsTIGrvRhw7XIPT7Ru/WwaiLK X-Google-Smtp-Source: ABdhPJyMTZOZAd1aoaZIc13FzAy0XfeTkk3umcmhxcsYykPFbkE0P11xR7Nw0c+6k+Tpb29X2PNzlg== X-Received: by 2002:a05:6402:42cf:: with SMTP id i15mr3431756edc.82.1639756547043; Fri, 17 Dec 2021 07:55:47 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (host-79-56-50-241.retail.telecomitalia.it. [79.56.50.241]) by smtp.gmail.com with ESMTPSA id i6sm772158edx.46.2021.12.17.07.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 07:55:46 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Michael Trimarchi , Dario Binacchi , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 1/4] clk: mxs: imx28: Reparent gpmi clk to ref_gpmi Date: Fri, 17 Dec 2021 16:55:09 +0100 Message-Id: <20211217155512.1877408-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> References: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Trimarchi ref_gpmi is connected that is sourced from pll0. This allow to get nand clk frequency to handle edo mode 5,4,3 Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- drivers/clk/mxs/clk-imx28.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index 62146ea4d5b8..9e0b9f8e5885 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -243,6 +243,9 @@ static void __init mx28_clocks_init(struct device_node = *np) =20 clk_register_clkdev(clks[enet_out], NULL, "enet_out"); =20 + /* GPMI set parent to ref_gpmi instead of osc */ + clk_set_parent(clks[gpmi_sel], clks[ref_gpmi]); + for (i =3D 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); } --=20 2.32.0 From nobody Wed Jul 1 17:39:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87C24C433F5 for ; Fri, 17 Dec 2021 15:55:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238571AbhLQPzy (ORCPT ); Fri, 17 Dec 2021 10:55:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237566AbhLQPzu (ORCPT ); Fri, 17 Dec 2021 10:55:50 -0500 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABC0CC061746 for ; Fri, 17 Dec 2021 07:55:49 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id x15so9601425edv.1 for ; Fri, 17 Dec 2021 07:55:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pCjPRfOE0ubdFKl1wroT8qZZ50obE6oG33Hg0XGM304=; b=GT7+ilekxSTS5dFNut7H6CiyF+s4HbxoxVMua+CSJLqW+fj8bgZ36r7laPoZzjTKVO /0ZsMq4hFsukMP44g8xdxWMyJ84oewN+Pqh49hxeu7h8jm/FApB0Emn134cSqYtoUf+Z PIca9tyY8AbC86kn8KUvHaTa5CHPRYorzTGPQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pCjPRfOE0ubdFKl1wroT8qZZ50obE6oG33Hg0XGM304=; b=tbOv+R+s41p8ijLbswx868McxYeVp9krgr8TgdSKatsAxmwSmB6z0pjfi6oiW/2Qaw fxMRL77pEGeBUX/Y4qSuwgr1I3Y1ran+w2XfgbMHmb9wwS2zN6EjuGVMyv0F7Tbmjk5D xoPx2/5s8YPK95jm7/1VKA3bqgoyyoXI/7tzttMQ7F0FlUIE3LzGd0e64FfRMmP8Xoto iKomUIjtkLrZYX6j6Jtxe4CfEhYZJP57P1pTuFcLM/TQZWy+VFkuotC7jQ91eON9QUUy A0I4sLkFfXkSMAk9Jkx8AyBHDizHhiFa63rcO/6ELKLDc+Nld7MdrCWM/cYPUyAFeq48 t8Pg== X-Gm-Message-State: AOAM532nsMzCVLhNt1qOhvmyNr+s9e0hRRbluK+H0oP7RLgMJ1CAdLdL ji8iVBLNHn0N53Lq6PtxuPUMPP0l4WQOKA== X-Google-Smtp-Source: ABdhPJwq9J1DWJQ8i4E0EiIDgAaMs/AhSQZcnTaJ1HC6l3gTEc24oM/ESRtaqP0UYIOPboiOppaXCg== X-Received: by 2002:a17:907:1c81:: with SMTP id nb1mr3125382ejc.9.1639756548087; Fri, 17 Dec 2021 07:55:48 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (host-79-56-50-241.retail.telecomitalia.it. [79.56.50.241]) by smtp.gmail.com with ESMTPSA id i6sm772158edx.46.2021.12.17.07.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 07:55:47 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Michael Trimarchi , Han Xu , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org Subject: [RFC PATCH 2/4] mtd: rawnand: gpmi: support fast edo timings for mx28 Date: Fri, 17 Dec 2021 16:55:10 +0100 Message-Id: <20211217155512.1877408-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> References: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the mx28 reference manual there are examples of how to set up the GPMI controller to support fast NAND EDO timing. This patch has been tested on a 2048/64 byte NAND (Micron MT29F2G08ABAEAH4). Kernel mtd tests: - mtd_nandbiterrs - mtd_nandecctest - mtd_oobtest - mtd_pagetest - mtd_readtest - mtd_speedtest - mtd_stresstest - mtd_subpagetest - mtd_torturetest [cycles_count =3D 10000000] run without errors. Before this patch (mode 0): --------------------------- eraseblock write speed is 2098 KiB/s eraseblock read speed is 2680 KiB/s page write speed is 1689 KiB/s page read speed is 2522 KiB/s 2 page write speed is 1899 KiB/s 2 page read speed is 2579 KiB/s erase speed is 128000 KiB/s 2x multi-block erase speed is 73142 KiB/s 4x multi-block erase speed is 204800 KiB/s 8x multi-block erase speed is 256000 KiB/s 16x multi-block erase speed is 256000 KiB/s 32x multi-block erase speed is 256000 KiB/s 64x multi-block erase speed is 256000 KiB/s After this patch (mode 5): ------------------------- eraseblock write speed is 3390 KiB/s eraseblock read speed is 5688 KiB/s page write speed is 2680 KiB/s page read speed is 4876 KiB/s 2 page write speed is 2909 KiB/s 2 page read speed is 5224 KiB/s erase speed is 170666 KiB/s 2x multi-block erase speed is 204800 KiB/s 4x multi-block erase speed is 256000 KiB/s 8x multi-block erase speed is 256000 KiB/s 16x multi-block erase speed is 256000 KiB/s 32x multi-block erase speed is 256000 KiB/s 64x multi-block erase speed is 256000 KiB/s Signed-off-by: Dario Binacchi Co-developed-by: Michael Trimarchi --- drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/= raw/gpmi-nand/gpmi-nand.c index 65bcd1c548d2..fd935e893daf 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -772,8 +772,8 @@ static int gpmi_setup_interface(struct nand_chip *chip,= int chipnr, if (IS_ERR(sdr)) return PTR_ERR(sdr); =20 - /* Only MX6 GPMI controller can reach EDO timings */ - if (sdr->tRC_min <=3D 25000 && !GPMI_IS_MX6(this)) + /* Only MX28/MX6 GPMI controller can reach EDO timings */ + if (sdr->tRC_min <=3D 25000 && !GPMI_IS_MX28(this) && !GPMI_IS_MX6(this)) return -ENOTSUPP; =20 /* Stop here if this call was just a check */ --=20 2.32.0 From nobody Wed Jul 1 17:39:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5A24C433FE for ; Fri, 17 Dec 2021 15:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238596AbhLQPz6 (ORCPT ); Fri, 17 Dec 2021 10:55:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238506AbhLQPzv (ORCPT ); Fri, 17 Dec 2021 10:55:51 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF28DC061574 for ; Fri, 17 Dec 2021 07:55:50 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id y12so9386800eda.12 for ; Fri, 17 Dec 2021 07:55:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GPyuWnLPH8PFNFJh17BU4dw6g8DK6MUXDTmu7+hfLlY=; b=gFDRtlH3e1/Jlp1cAjp2QqkKroRvrg65fXs2p8TfqllBfCqoiogpYwTR2o5QbEEuD/ OogD9ePzwhTd3y+dc4zEXuNYNse3FghP9+qtQXfNman3VDrKlL33nC10tLbMMRpOpJ+Q pj0s34n97SOV7qZy0zdvh0DyIOmt/GleRGk3E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GPyuWnLPH8PFNFJh17BU4dw6g8DK6MUXDTmu7+hfLlY=; b=p1yTuNavmQA3EehrG7EwW4C1asEAFAE7W3lA7TJ38vOHvxKGar95pG2eVUDQIgR1Us ddvScUNnrfLGnX0BMCX557nkDi7q0Cmu1eodPwlgSjZIITxy5HFZ6QotHbOe4rkpOuQY 4CGZZUJXzh4PRJMjofvKCdTwTHKakEx8aJ5vqV0J5SmTlw0288clr9OAgsedbJxRD8WV 2/n02QSiBQ6Xfo1kVO3v3nzxcMszTMb3hyo+AS5jKMnjYtQgJ6XjX04lhPwkhz6d2Kzq etKawOeMGktOLbH9quw4tY6s6MCYDnM1AG1NB42Hrgadnz7nYcR1FLzbMCZBaX8+4/Zu 0ZNA== X-Gm-Message-State: AOAM5320FH39Ao83WoYVCD8GIQD9hiVy2fKHkNaAmmDiedN/gXeIXyLq WSTl7itxolu4lCJaVlOnqXH+X1LCijOLLg== X-Google-Smtp-Source: ABdhPJypWJce5q+VYVZqPNebWyJZp9GWchWxQ7EUMp01LDmMnu4A8AyP1ZlWihYdRXcrf843n+1caw== X-Received: by 2002:aa7:c6c8:: with SMTP id b8mr3513024eds.164.1639756549196; Fri, 17 Dec 2021 07:55:49 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (host-79-56-50-241.retail.telecomitalia.it. [79.56.50.241]) by smtp.gmail.com with ESMTPSA id i6sm772158edx.46.2021.12.17.07.55.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 07:55:48 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Michael Trimarchi , Boris Brezillon , Han Xu , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org Subject: [RFC PATCH 3/4] mtd: rawnand: gpmi: fix controller timings setting Date: Fri, 17 Dec 2021 16:55:11 +0100 Message-Id: <20211217155512.1877408-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> References: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The controller registers are now set accordling to the real clock rate. Fixes: b1206122069a ("mtd: rawnand: gpmi: use core timings instead of an em= pirical derivation") Signed-off-by: Dario Binacchi Co-developed-by: Michael Trimarchi --- drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/= raw/gpmi-nand/gpmi-nand.c index fd935e893daf..0517b81bb24c 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -648,6 +648,7 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_d= ata *this, const struct nand_sdr_timings *sdr) { struct gpmi_nfc_hardware_timing *hw =3D &this->hw; + struct resources *r =3D &this->resources; unsigned int dll_threshold_ps =3D this->devdata->max_chain_delay; unsigned int period_ps, reference_period_ps; unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles; @@ -671,6 +672,8 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_d= ata *this, wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; } =20 + hw->clk_rate =3D clk_round_rate(r->clock[0], hw->clk_rate); + /* SDR core timings are given in picoseconds */ period_ps =3D div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); =20 --=20 2.32.0 From nobody Wed Jul 1 17:39:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C3C1C433FE for ; Fri, 17 Dec 2021 15:56:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238639AbhLQP4A (ORCPT ); Fri, 17 Dec 2021 10:56:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238539AbhLQPzw (ORCPT ); Fri, 17 Dec 2021 10:55:52 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF90BC061574 for ; Fri, 17 Dec 2021 07:55:51 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id g14so9454326edb.8 for ; Fri, 17 Dec 2021 07:55:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M2WbEnBbDQgsL2Z6AiQ6BSUsHGfqd+FRDLIjDGY984c=; b=XpLaJNf7l0burOcMud+Y/VNOXEkyFXWUEHIk8Y7s5tKNFIHAjMfOcaCWrx41B+Kc0m mvcNEknsWkwTV7KeKr7rfN5L/Le/BnZMTuNzUrRGAC00oA6BK3Zv3JW1YsEyyUvU3ILk Q/3JEnlteQoPxIYMBDHuhvjjDbOM29L3iJOOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M2WbEnBbDQgsL2Z6AiQ6BSUsHGfqd+FRDLIjDGY984c=; b=qvRnb8Ck+c6Cbvz6padMBvFJ1zDng02DjX07fgSbge99InLstbZkHCDdpwePvnBTzd PWgP/swVKhojjBc3WCbtKBG8p0Wkg6n1MW1ARRRW25GLGLNnHi3pp5/wI2xXm2mMe+tQ W5Zzcis3pG8ALdU+41AJS+AHzTpr5iMvD9dkfK8j9WZyU2NTywdtl2s+AIXtowTzzBW6 vYWYNgJgEqz6W1B5+VtzfVpgTDXMuvl+LqECdE/50zUO2EajbwYTbf0p9N1+zdaj1ohQ lJ/s+eh2EAO5ZVsN875rfjwtPpWfD++OsBfOXw91pSrXyJTJswRYfmLutPyxNhX4/3d9 ynUA== X-Gm-Message-State: AOAM533PIj3f5zC7nHWIeQ/zWThOaER/fNX+wZP9wfDPXIHPEPCW2E7u 7sk9O4dDDf0vHfzU2gBn7BtALKJQI3jMFg== X-Google-Smtp-Source: ABdhPJzcYU0Q7QsepmRT6KYkMrmqU1jUmvusl/ehkTaW1AoUEGp3p/Eox5oq238UDGwWXE0qaV/eiQ== X-Received: by 2002:a17:906:3586:: with SMTP id o6mr3065886ejb.186.1639756550286; Fri, 17 Dec 2021 07:55:50 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (host-79-56-50-241.retail.telecomitalia.it. [79.56.50.241]) by smtp.gmail.com with ESMTPSA id i6sm772158edx.46.2021.12.17.07.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 07:55:49 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Michael Trimarchi , Han Xu , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org Subject: [RFC PATCH 4/4] mtd: rawnand: gpmi: validate controller clock rate Date: Fri, 17 Dec 2021 16:55:12 +0100 Message-Id: <20211217155512.1877408-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> References: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" What to do when the real rate of the gpmi clock is not equal to the required one? The solutions proposed in [1] did not lead to a conclusion on how to validate the clock rate, so, inspired by the document [2], I consider the rate correct only if not greater than the rate of the previous edo. In fact, in chapter 4.16.2 (NV-DDR) of the document [2], it is written that "If the host selects timing mode n, then its clock period shall be faster than the clock period of timing mode n-1 and slower than or equal to the clock period of timing mode n.". I thought that it could therefore also be used in this case, without therefore having to define the valid rate ranges empirically. [1] https://lore.kernel.org/r/20210702065350.209646-5-ebiggers@kernel.org [2] http://www.onfi.org/-/media/client/onfi/specs/onfi_3_0_gold.pdf?la=3Den Signed-off-by: Dario Binacchi Co-developed-by: Michael Trimarchi --- drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 70 +++++++++++++++++----- 1 file changed, 54 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/= raw/gpmi-nand/gpmi-nand.c index 0517b81bb24c..3d37cd49abd5 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -570,6 +570,27 @@ static int bch_set_geometry(struct gpmi_nand_data *thi= s) return ret; } =20 +struct edo_mode { + u32 tRC_min; + long clk_rate; + u8 wrn_dly_sel; +}; + +static const struct edo_mode edo_modes[] =3D { + {.tRC_min =3D 30000, .clk_rate =3D 22000000, + .wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, + {.tRC_min =3D 30000, .clk_rate =3D 22000000, + .wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, + {.tRC_min =3D 30000, .clk_rate =3D 22000000, + .wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, + {.tRC_min =3D 30000, .clk_rate =3D 22000000, + .wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, + {.tRC_min =3D 25000, .clk_rate =3D 80000000, + .wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY}, + {.tRC_min =3D 20000, .clk_rate =3D 100000000, + .wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY}, +}; + /* * <1> Firstly, we should know what's the GPMI-clock means. * The GPMI-clock is the internal clock in the gpmi nand controller. @@ -644,8 +665,8 @@ static int bch_set_geometry(struct gpmi_nand_data *this) * RDN_DELAY =3D ----------------------- {3} * RP */ -static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, - const struct nand_sdr_timings *sdr) +static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this, + const struct nand_sdr_timings *sdr) { struct gpmi_nfc_hardware_timing *hw =3D &this->hw; struct resources *r =3D &this->resources; @@ -657,22 +678,35 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand= _data *this, int sample_delay_ps, sample_delay_factor; u16 busy_timeout_cycles; u8 wrn_dly_sel; + long clk_rate; + int i, emode =3D -1; =20 - if (sdr->tRC_min >=3D 30000) { - /* ONFI non-EDO modes [0-3] */ - hw->clk_rate =3D 22000000; - wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS; - } else if (sdr->tRC_min >=3D 25000) { - /* ONFI EDO mode 4 */ - hw->clk_rate =3D 80000000; - wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; - } else { - /* ONFI EDO mode 5 */ - hw->clk_rate =3D 100000000; - wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; + /* Search the required EDO mode */ + for (i =3D 0; i < ARRAY_SIZE(edo_modes); i++) { + if (sdr->tRC_min >=3D edo_modes[i].tRC_min) { + emode =3D i; + break; + } + } + + if (emode < 0) { + dev_err(this->dev, "tRC_min %d not supported\n", sdr->tRC_min); + return -ENOTSUPP; + } + + clk_rate =3D clk_round_rate(r->clock[0], edo_modes[emode].clk_rate); + if (emode > 0 && !(clk_rate <=3D edo_modes[emode].clk_rate && + clk_rate > edo_modes[emode - 1].clk_rate)) { + dev_err(this->dev, + "edo mode %d clock setting: expected %ld, got %ld\n", + emode, edo_modes[emode].clk_rate, clk_rate); + return -ENOTSUPP; } =20 - hw->clk_rate =3D clk_round_rate(r->clock[0], hw->clk_rate); + dev_dbg(this->dev, "edo mode %d @ %ld Hz\n", emode, clk_rate); + + hw->clk_rate =3D clk_rate; + wrn_dly_sel =3D edo_modes[emode].wrn_dly_sel; =20 /* SDR core timings are given in picoseconds */ period_ps =3D div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); @@ -714,6 +748,7 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_d= ata *this, hw->ctrl1n |=3D BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) | BM_GPMI_CTRL1_DLL_ENABLE | (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0); + return 0; } =20 static int gpmi_nfc_apply_timings(struct gpmi_nand_data *this) @@ -769,6 +804,7 @@ static int gpmi_setup_interface(struct nand_chip *chip,= int chipnr, { struct gpmi_nand_data *this =3D nand_get_controller_data(chip); const struct nand_sdr_timings *sdr; + int ret; =20 /* Retrieve required NAND timings */ sdr =3D nand_get_sdr_timings(conf); @@ -784,7 +820,9 @@ static int gpmi_setup_interface(struct nand_chip *chip,= int chipnr, return 0; =20 /* Do the actual derivation of the controller timings */ - gpmi_nfc_compute_timings(this, sdr); + ret =3D gpmi_nfc_compute_timings(this, sdr); + if (ret) + return ret; =20 this->hw.must_apply_timings =3D true; =20 --=20 2.32.0