From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB99CC433FE for ; Fri, 17 Dec 2021 01:30:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231818AbhLQBaN (ORCPT ); Thu, 16 Dec 2021 20:30:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231783AbhLQBaK (ORCPT ); Thu, 16 Dec 2021 20:30:10 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BD44C061401 for ; Thu, 16 Dec 2021 17:30:10 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id t3so1363051lfe.12 for ; Thu, 16 Dec 2021 17:30:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yuiR3XHwD32nQQSyEGMDlqMBszeUDsewPKrEObZDzmc=; b=XTVKSwrUT7kVpmugHodaQ3bRT6sG3k8/j/OVLmtWbN/Hdq0TLSrhl0v1QOL72oJ1nU 3cfGmpwfe8EIme5Gm8u7Uj56SJmOcWnjGgCjZ9eKYZ1tpWFhCsObOXUGyyTQ6Fj097TQ OqyF8K/4w/nq1RixjXpADe2H69xXDzIv0SwrQFfcXx3hqcGOR7uPUWE2dOR3q5ectcYH /cfBt+LBKsIRQK8P5fAjjypu55xyjYeaymYTe63H/9TdN902tUW/05Of/6aftFkvjBbP lRdbY/bJKDZtZCw5sEFAmI2QqRY3GD5cXP3x/70ChM4eVbJ3WQAiNpj47o5ZVcYUkxWZ i/EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yuiR3XHwD32nQQSyEGMDlqMBszeUDsewPKrEObZDzmc=; b=m7K6RTM3nALtKnt2vIJhx5JeuqMPCh7v8F0lF1OW79IqVnBfoZHt9dgoEWuJPz/rUU hyU6CATslRJk7J9/YcBPgH7YWVHc8hdk1YwAvxojM96+lyFdoDVOSjdMOOlV/BODJt9e HOTmnOuEWAdEM//oE8/2EEnP87zQ5SgKHVaEfkOJ1xreIc1h785MpyY71buCA4flMHel vzacDYJ171WSC44qwizkJelZBZ2tcQEpLrcEIeljQFXXaavVUuJVRGYjRgLutiBumEXi JrSoQ14dOeXa4Sr/2aAz4GA5yXTbDMfRIhv9sRyBVoedq2eQG+jCUZbJlA5k+aVs/qm4 0H+w== X-Gm-Message-State: AOAM530j6v8/IdhSVvE/aEc/JWOZfyy5jIbjUGYTNYEDSRb8ser3jRDy NKIBvnbkhM05zEr7PgJ2GpP3DA== X-Google-Smtp-Source: ABdhPJyrazrMYbsMpDAFM/nM9yDLrnqps9xzq3+sisgsdwVgDDx0J/FFyqDlQ11oOHhoSAYxqJkcZw== X-Received: by 2002:a05:6512:3b8a:: with SMTP id g10mr781424lfv.93.1639704608269; Thu, 16 Dec 2021 17:30:08 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id b7sm1131676lfb.224.2021.12.16.17.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 17:30:07 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/7] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks Date: Fri, 17 Dec 2021 03:29:59 +0200 Message-Id: <20211217013005.16646-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Acked-by: Chanwoo Choi Signed-off-by: Sam Protsenko --- Changes in v2: - Added R-b tag by Krzysztof Kozlowski - Added Ack tag by Rob Herring - Added Ack tag by Chanwoo Choi include/dt-bindings/clock/exynos850.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/cl= ock/exynos850.h index 8aa5e82af0d3..0b6a3c6a7c90 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -82,7 +82,10 @@ #define CLK_GOUT_I3C_PCLK 19 #define CLK_GOUT_I3C_SCLK 20 #define CLK_GOUT_SPEEDY_PCLK 21 -#define APM_NR_CLK 22 +#define CLK_GOUT_GPIO_ALIVE_PCLK 22 +#define CLK_GOUT_PMU_ALIVE_PCLK 23 +#define CLK_GOUT_SYSREG_APM_PCLK 24 +#define APM_NR_CLK 25 =20 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -99,7 +102,8 @@ #define CLK_GOUT_CMGP_USI0_PCLK 12 #define CLK_GOUT_CMGP_USI1_IPCLK 13 #define CLK_GOUT_CMGP_USI1_PCLK 14 -#define CMGP_NR_CLK 15 +#define CLK_GOUT_SYSREG_CMGP_PCLK 15 +#define CMGP_NR_CLK 16 =20 /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 @@ -167,7 +171,9 @@ #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 #define CLK_GOUT_SSS_ACLK 11 #define CLK_GOUT_SSS_PCLK 12 -#define CORE_NR_CLK 13 +#define CLK_GOUT_GPIO_CORE_PCLK 13 +#define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CORE_NR_CLK 15 =20 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 --=20 2.30.2 From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A057DC433F5 for ; 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Thu, 16 Dec 2021 17:30:09 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/7] clk: samsung: exynos850: Add missing sysreg clocks Date: Fri, 17 Dec 2021 03:30:00 +0200 Message-Id: <20211217013005.16646-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Reviewed-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Signed-off-by: Sam Protsenko --- Changes in v2: - Added R-b tag by Krzysztof Kozlowski - Added Ack tag by Chanwoo Choi drivers/clk/samsung/clk-exynos850.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 568ac97c8120..4799771d09bc 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -426,11 +426,14 @@ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-= cmu-top", #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 +#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc +#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 =20 static const unsigned long apm_clk_regs[] __initconst =3D { PLL_CON0_MUX_CLKCMU_APM_BUS_USER, @@ -445,11 +448,14 @@ static const unsigned long apm_clk_regs[] __initconst= =3D { CLK_CON_DIV_DIV_CLK_APM_I3C, CLK_CON_GAT_CLKCMU_CMGP_BUS, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, + CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, + CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, }; =20 /* List of parent clocks for Muxes in CMU_APM */ @@ -512,6 +518,14 @@ static const struct samsung_gate_clock apm_gate_clks[]= __initconst =3D { CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), + /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ + GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", + CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, + 0), + GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", + CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), }; =20 static const struct samsung_cmu_info apm_cmu_info __initconst =3D { @@ -541,6 +555,7 @@ static const struct samsung_cmu_info apm_cmu_info __ini= tconst =3D { #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c @@ -556,6 +571,7 @@ static const unsigned long cmgp_clk_regs[] __initconst = =3D { CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, @@ -610,6 +626,9 @@ static const struct samsung_gate_clock cmgp_gate_clks[]= __initconst =3D { GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), }; =20 static const struct samsung_cmu_info cmgp_cmu_info __initconst =3D { @@ -910,10 +929,12 @@ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850= -cmu-peri", #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 +#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c +#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 =20 static const unsigned long core_clk_regs[] __initconst =3D { PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, @@ -924,10 +945,12 @@ static const unsigned long core_clk_regs[] __initcons= t =3D { CLK_CON_DIV_DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, CLK_CON_GAT_GOUT_CORE_GIC_CLK, + CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, + CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, }; =20 /* List of parent clocks for Muxes in CMU_CORE */ @@ -972,6 +995,12 @@ static const struct samsung_gate_clock core_gate_clks[= ] __initconst =3D { CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), + /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ + GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", + "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), }; =20 static const struct samsung_cmu_info core_cmu_info __initconst =3D { --=20 2.30.2 From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E29ECC43217 for ; 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Thu, 16 Dec 2021 17:30:11 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 3/7] dt-bindings: Add vendor prefix for WinLink Date: Fri, 17 Dec 2021 03:30:01 +0200 Message-Id: <20211217013005.16646-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" WinLink Co., Ltd is a hardware design and manufacturing company based in South Korea. Official web-site: [1]. [1] http://win-link.net/ Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v2: - Added Ack tag by Rob Herring Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 4698213611db..25f94c723cbc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1328,6 +1328,8 @@ patternProperties: description: Wiligear, Ltd. "^winbond,.*": description: Winbond Electronics corp. + "^winlink,.*": + description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. "^wits,.*": --=20 2.30.2 From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5726EC433FE for ; Fri, 17 Dec 2021 01:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231878AbhLQBaS (ORCPT ); Thu, 16 Dec 2021 20:30:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231822AbhLQBaP (ORCPT ); Thu, 16 Dec 2021 20:30:15 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CBF5C06173F for ; Thu, 16 Dec 2021 17:30:14 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id bi37so1449611lfb.5 for ; Thu, 16 Dec 2021 17:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QM6f47ayHPQt/5IdQ/xMhOSTbh2OemqUyIwCi0r5BpE=; b=RgsTKdDzcBwtCxrfX4AqOv4ybgC5se3ZM3CHliwW1pHlvEb0unBiII0kD9nverEGEt ykPgkVB+/pv4Iqo4VnrSRcDgwzQxTAGEuJ0F72dyeOdDOO93m6gv7rtw5Fq3nlh6t6EY Io1ctoYvxa6g0Qpc503Nba7FwkZqYjzLz4feCNRbDaNgUjiIPWcu2tUySFXf3VTqELWu waw8aEu85sjfGpPzL5vfyo2E3j5fGdeD9UGvSwv9wxWSaY/oLsdX0whOAARl2MZOI/ja VgyKBPnm1X7S+3ykhovCSA4qrarozdv1WH6iWws62xLkIUNV0S5eqHQGP4FIp14myWDA RsUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QM6f47ayHPQt/5IdQ/xMhOSTbh2OemqUyIwCi0r5BpE=; b=yD4ucdlvs9knjjscxvrUURtt0CeGBCV1M7ayOB8cVV8S+rHbcAz/ojr5k6GomkiwKN XRjTuST3q4jDUxkiqFWEWjO2/fKBRJLU5JXIvlD+rtgxROnLbDpgZ7Q9mbk2KoXl959e W/l2se1cRbhPWGaYrdf+5RAZvaqfup8wMUIrwDNb6TF5IPfn4C8vL6xw5xmPbVn03gEk FvJ6O7CT/t54JcgKGtcfsc8MttUOq4K+lFfOMpbEPTq8b0QqvCDZjBg9Mg3/7aUlAnjL 7XjfD7hEvBjx55vgii0tJl3JdKt2vlYdVLl/ifBjQbuDTAxO8lhCpSk+i84TDAH63V3d 8yOw== X-Gm-Message-State: AOAM533Is+lEoQIsTFjKvgyG3ZGWNRGvb/Ve1Hw+BSIfLY6a2ygZa/LX vsqGALO4jTT5scri4KSBtfZ2nQ== X-Google-Smtp-Source: ABdhPJzjUfwEoYesZqEjPi0VMxKoi6uMmfpS1eDv461HjtDZO3NaH9w7JiiomyHszxF5NgDgY6xQuQ== X-Received: by 2002:ac2:5930:: with SMTP id v16mr748999lfi.327.1639704612792; Thu, 16 Dec 2021 17:30:12 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id z8sm1132468lfu.128.2021.12.16.17.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 17:30:12 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 4/7] dt-bindings: arm: samsung: Document E850-96 board binding Date: Fri, 17 Dec 2021 03:30:02 +0200 Message-Id: <20211217013005.16646-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding for the WinLink E850-96 board, which is based on Samsung Exynos850 SoC. Signed-off-by: Sam Protsenko --- Changes in v2: - Moved Exynos850/E850-96 binding before Exynos Auto V9 entry - Rebased on krzk/linux.git (for-next), to account for Exynos7885 changes .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.y= aml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index d88571202713..052cd94113d4 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -205,6 +205,12 @@ properties: - samsung,jackpotlte # Samsung Galaxy A8 (2018) - const: samsung,exynos7885 =20 + - description: Exynos850 based boards + items: + - enum: + - winlink,e850-96 # WinLink E850-96 + - const: samsung,exynos850 + - description: Exynos Auto v9 based boards items: - enum: --=20 2.30.2 From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20ECAC4332F for ; Fri, 17 Dec 2021 01:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231896AbhLQBaU (ORCPT ); Thu, 16 Dec 2021 20:30:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231855AbhLQBaQ (ORCPT ); Thu, 16 Dec 2021 20:30:16 -0500 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 042E6C06175E for ; Thu, 16 Dec 2021 17:30:16 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id p8so903015ljo.5 for ; Thu, 16 Dec 2021 17:30:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1gMoyGZFMOrtFD2i+WoXh7qozc6etdJzwaY+U9hXibg=; b=Q1bgyZKSBo51wkneapHn9To5VF7IeoH9ZAKXK3FtqsSvQVWoK4r1rvLYiFyvQJFcav T2A5OaU/TwayBCjcldondyZnYw8YV0eeuP11nSoMdhrnDwVUVCD+LAOEfx/mGy9CKGYq iubzfSBm+RbEB1LsNaCnuFuwypWXNJqlNfmZL4ysBbJw97MeyJlo6uogxv9KII4bpGD/ nwID//auOXpKtVCPuJSFSfAECIju2pikpUEsN8N24VekhriuMYiVROx1JSqAFv/2/VLx /mF7JsGaZSswYsmyVuGdssqrkI9XRAEgG5OdMvXNft672EGJMa4Nwq+7FExnity92/e4 kAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1gMoyGZFMOrtFD2i+WoXh7qozc6etdJzwaY+U9hXibg=; b=cFq21Z3QRD0/o5KBVqDNBBwNhPTH/guUMI767kowiTStESg11NbttOZ7cdh4JsYehR CLG4TjDvNszvNpkDAh+xsaqWKnbEq4qy22OJ/6j2cVQ7W+JEW4jXLJ0HGKnQcsOi9q31 ZPjf6C8jvEAnfnJXpxN+S5aqMazMOyYCVVV6cybDKR8HeR4jYyAL5LCUX4LirLaWj4d7 Ecqi79x02V3VRsEFRJWJxkSEj5Im5h5XXF9PlMa6d5yWzAXBC+u8OVhd84LtU7MgwxbL Uk/ae12D9PXDlWuPjrgWRVzJfhVTP1sDBmdgQMKtRWDbZPCeODczg6fIdR54PJ7qspDQ 3fAQ== X-Gm-Message-State: AOAM533uuWnvsJ8697jlwxYaYGLrGAXMNtZE21gXLyMmvYqTvxVrdP8m EYryxGObXMw/GOFnZt+r/AIViw== X-Google-Smtp-Source: ABdhPJwYGpaI3GK2jyICva2hvw6KK49b/X0iRkfEL7ZJ1jOxB5cBp5dJq4iwrfStYWcZEw39OYgwyQ== X-Received: by 2002:a2e:b6d4:: with SMTP id m20mr669927ljo.471.1639704614273; Thu, 16 Dec 2021 17:30:14 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id t7sm1129670lfl.260.2021.12.16.17.30.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 17:30:13 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 5/7] dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 Date: Fri, 17 Dec 2021 03:30:03 +0200 Message-Id: <20211217013005.16646-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All Exynos850 GPIO blocks can use EXYNOS5420_PIN_DRV* definitions, except GPIO_HSI block. Add pin drive strength definitions for GPIO_HSI block correspondingly. Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v2: - Added Ack tag by Rob Herring include/dt-bindings/pinctrl/samsung.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pi= nctrl/samsung.h index b1832506b923..950970634dfe 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -36,7 +36,10 @@ #define EXYNOS5260_PIN_DRV_LV4 2 #define EXYNOS5260_PIN_DRV_LV6 3 =20 -/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (e= xcept + * GPIO_HSI block) + */ #define EXYNOS5420_PIN_DRV_LV1 0 #define EXYNOS5420_PIN_DRV_LV2 1 #define EXYNOS5420_PIN_DRV_LV3 2 @@ -56,6 +59,14 @@ #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf =20 +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + #define EXYNOS_PIN_FUNC_INPUT 0 #define EXYNOS_PIN_FUNC_OUTPUT 1 #define EXYNOS_PIN_FUNC_2 2 --=20 2.30.2 From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D460FC4167E for ; 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Thu, 16 Dec 2021 17:30:15 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 6/7] arm64: dts: exynos: Add initial Exynos850 SoC support Date: Fri, 17 Dec 2021 03:30:04 +0200 Message-Id: <20211217013005.16646-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Samsung Exynos850 is ARMv8-based mobile-oriented SoC. This patch adds initial SoC support. It's not comprehensive yet, some more devices will be added later. Right now only crucial system components and most needed platform devices are defined. Crucial features (needed to boot Linux up to shell with serial console): * Octa cores (Cortex-A55), supporting PSCI v1.0 * ARM architected timer (armv8-timer) * Interrupt controller (GIC-400) * Pinctrl nodes for GPIO * Serial node Basic platform features: * Clock controller CMUs * OSCCLK clock * RTC clock * MCT timer * ARM PMU (Performance Monitor Unit) * Chip-id * RTC * Reset * Watchdog timers * eMMC * I2C * HSI2C * USI All those features were already enabled and tested on E850-96 board with minimal BusyBox rootfs. Signed-off-by: Sam Protsenko --- Changes in v2: - Merged spi*_cs_func_pins nodes (Chip Select pin) into spi*_pins nodes - Removed spi*_cs_pins nodes (GPIO configuration for SPI CS pins) - Sorted pinctrl_peri "pins" nodes by name - Removed USI aliases - Added TODO comment for RTC clock (needs to be implemented in PMIC) - Sorted cmu nodes by unit address - Sorted pinctrl nodes by unit address .../boot/dts/exynos/exynos850-pinctrl.dtsi | 713 +++++++++++++++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 753 ++++++++++++++++++ 2 files changed, 1466 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64= /boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..93fa05e642ed --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,713 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as de= vice + * tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_pins: i2c5-pins { + samsung,pins =3D "gpa3-5", "gpa3-6"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_pins: i2c6-pins { + samsung,pins =3D "gpa3-7", "gpa4-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI: UART_DEBUG_0 pins */ + uart0_pins: uart0-pins { + samsung,pins =3D "gpq0-0", "gpq0-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + /* USI: UART_DEBUG_1 pins */ + uart1_pins: uart1-pins { + samsung,pins =3D "gpa3-7", "gpa4-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + gpm5: gpm5 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_pins: hsi2c3-pins { + samsung,pins =3D "gpm0-0", "gpm1-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_single_pins: uart1-single-pins { + samsung,pins =3D "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_dual_pins: uart1-dual-pins { + samsung,pins =3D "gpm0-0", "gpm1-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + /* USI_CMGP0: SPI function */ + spi1_pins: spi1-pins { + samsung,pins =3D "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_pins: hsi2c4-pins { + samsung,pins =3D "gpm4-0", "gpm5-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_single_pins: uart2-single-pins { + samsung,pins =3D "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_dual_pins: uart2-dual-pins { + samsung,pins =3D "gpm4-0", "gpm5-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + /* USI_CMGP1: SPI function */ + spi2_pins: spi2-pins { + samsung,pins =3D "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; +}; + +&pinctrl_aud { + gpb0: gpb0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + aud_codec_mclk_pins: aud-codec-mclk-pins { + samsung,pins =3D "gpb0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins { + samsung,pins =3D "gpb0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_i2s0_pins: aud-i2s0-pins { + samsung,pins =3D "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_i2s0_idle_pins: aud-i2s0-idle-pins { + samsung,pins =3D "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_i2s1_pins: aud-i2s1-pins { + samsung,pins =3D "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_i2s1_idle_pins: aud-i2s1-idle-pins { + samsung,pins =3D "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_fm_pins: aud-fm-pins { + samsung,pins =3D "gpb1-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; + + aud_fm_idle_pins: aud-fm-idle-pins { + samsung,pins =3D "gpb1-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + sd2_clk_pins: sd2-clk-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_clk_fast_slew_rate_1x_pins: sd2-clk-fast-slew-rate-1x-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_clk_fast_slew_rate_1_5x_pins: sd2-clk-fast-slew-rate-1-5x-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_clk_fast_slew_rate_2x_pins: sd2-clk-fast-slew-rate-2x-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_clk_fast_slew_rate_2_5x_pins: sd2-clk-fast-slew-rate-2-5x-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_clk_fast_slew_rate_3x_pins: sd2-clk-fast-slew-rate-3x-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_clk_fast_slew_rate_4x_pins: sd2-clk-fast-slew-rate-4x-pins { + samsung,pins =3D "gpf2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_cmd_pins: sd2-cmd-pins { + samsung,pins =3D "gpf2-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_bus1_pins: sd2-bus1-pins { + samsung,pins =3D "gpf2-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_bus4_pins: sd2-bus4-pins { + samsung,pins =3D "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd2_pdn_pins: sd2-pdn-pins { + samsung,pins =3D "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; +}; + +&pinctrl_core { + gpf0: gpf0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + sd0_clk_pins: sd0-clk-pins { + samsung,pins =3D "gpf0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_clk_fast_slew_rate_1x_pins: sd0-clk-fast-slew-rate-1x-pins { + samsung,pins =3D "gpf0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_clk_fast_slew_rate_2x_pins: sd0-clk-fast-slew-rate-2x-pins { + samsung,pins =3D "gpf0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_clk_fast_slew_rate_3x_pins: sd0-clk-fast-slew-rate-3x-pins { + samsung,pins =3D "gpf0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_clk_fast_slew_rate_4x_pins: sd0-clk-fast-slew-rate-4x-pins { + samsung,pins =3D "gpf0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_cmd_pins: sd0-cmd-pins { + samsung,pins =3D "gpf0-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_rdqs_pins: sd0-rdqs-pins { + samsung,pins =3D "gpf0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_nreset_pins: sd0-nreset-pins { + samsung,pins =3D "gpf0-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_bus1_pins: sd0-bus1-pins { + samsung,pins =3D "gpf1-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_bus4_pins: sd0-bus4-pins { + samsung,pins =3D "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sd0_bus8_pins: sd0-bus8-pins { + samsung,pins =3D "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; +}; + +&pinctrl_peri { + gpc0: gpc0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp0: gpp0 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp2: gpp2 { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + sensor_mclk0_in_pins: sensor-mclk0-in-pins { + samsung,pins =3D "gpc0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk0_out_pins: sensor-mclk0-out-pins { + samsung,pins =3D "gpc0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk0_fn_pins: sensor-mclk0-fn-pins { + samsung,pins =3D "gpc0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk1_in_pins: sensor-mclk1-in-pins { + samsung,pins =3D "gpc0-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk1_out_pins: sensor-mclk1-out-pins { + samsung,pins =3D "gpc0-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk1_fn_pins: sensor-mclk1-fn-pins { + samsung,pins =3D "gpc0-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk2_in_pins: sensor-mclk2-in-pins { + samsung,pins =3D "gpc0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk2_out_pins: sensor-mclk2-out-pins { + samsung,pins =3D "gpc0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sensor_mclk2_fn_pins: sensor-mclk2-fn-pins { + samsung,pins =3D "gpc0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI: HSI2C0 */ + hsi2c0_pins: hsi2c0-pins { + samsung,pins =3D "gpc1-0", "gpc1-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI: HSI2C1 */ + hsi2c1_pins: hsi2c1-pins { + samsung,pins =3D "gpc1-2", "gpc1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI: HSI2C2 */ + hsi2c2_pins: hsi2c2-pins { + samsung,pins =3D "gpc1-4", "gpc1-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + /* USI: SPI */ + spi0_pins: spi0-pins { + samsung,pins =3D "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2c0_pins: i2c0-pins { + samsung,pins =3D "gpp0-0", "gpp0-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2c1_pins: i2c1-pins { + samsung,pins =3D "gpp0-2", "gpp0-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2c2_pins: i2c2-pins { + samsung,pins =3D "gpp0-4", "gpp0-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2c3_pins: i2c3-pins { + samsung,pins =3D "gpp1-0", "gpp1-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2c4_pins: i2c4-pins { + samsung,pins =3D "gpp1-2", "gpp1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + xclkout_pins: xclkout-pins { + samsung,pins =3D "gpq0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi new file mode 100644 index 000000000000..458f5bc22f59 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,753 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos850 based board files can include this file and provide + * values for board specific bindings. + */ + +#include +#include +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible =3D "samsung,exynos850"; + #address-cells =3D <2>; + #size-cells =3D <1>; + + interrupt-parent =3D <&gic>; + + aliases { + pinctrl0 =3D &pinctrl_alive; + pinctrl1 =3D &pinctrl_cmgp; + pinctrl2 =3D &pinctrl_aud; + pinctrl3 =3D &pinctrl_hsi; + pinctrl4 =3D &pinctrl_core; + pinctrl5 =3D &pinctrl_peri; + mmc0 =3D &mmc_0; + serial0 =3D &serial_0; + serial1 =3D &serial_1; + serial2 =3D &serial_2; + i2c0 =3D &i2c_0; + i2c1 =3D &i2c_1; + i2c2 =3D &i2c_2; + i2c3 =3D &i2c_3; + i2c4 =3D &i2c_4; + i2c5 =3D &i2c_5; + i2c6 =3D &i2c_6; + i2c7 =3D &hsi2c_0; + i2c8 =3D &hsi2c_1; + i2c9 =3D &hsi2c_2; + i2c10 =3D &hsi2c_3; + i2c11 =3D &hsi2c_4; + }; + + arm-pmu { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* Main system clock (XTCXO); external, must be 26 MHz */ + oscclk: clock-oscclk { + compatible =3D "fixed-clock"; + clock-output-names =3D "oscclk"; + #clock-cells =3D <0>; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible =3D "fixed-clock"; + clock-output-names =3D "rtcclk"; + #clock-cells =3D <0>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + core1 { + cpu =3D <&cpu5>; + }; + core2 { + cpu =3D <&cpu6>; + }; + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x1>; + enable-method =3D "psci"; + }; + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x2>; + enable-method =3D "psci"; + }; + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x3>; + enable-method =3D "psci"; + }; + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x101>; + enable-method =3D "psci"; + }; + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x102>; + enable-method =3D "psci"; + }; + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x103>; + enable-method =3D "psci"; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts =3D + , + , + , + ; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible =3D "samsung,exynos850-chipid"; + reg =3D <0x10000000 0x100>; + }; + + timer@10040000 { + compatible =3D "samsung,exynos4210-mct"; + reg =3D <0x10040000 0x800>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; + clock-names =3D "fin_pll", "mct"; + }; + + gic: interrupt-controller@12a01000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + reg =3D <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts =3D ; + }; + + pmu_system_controller: system-controller@11860000 { + compatible =3D "samsung,exynos850-pmu", "syscon"; + reg =3D <0x11860000 0x10000>; + clocks =3D <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; + + reboot: syscon-reboot { + compatible =3D "syscon-reboot"; + regmap =3D <&pmu_system_controller>; + offset =3D <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask =3D <0x2>; /* SWRESET_SYSTEM */ + value =3D <0x2>; /* reset value */ + }; + }; + + watchdog_cl0: watchdog@10050000 { + compatible =3D "samsung,exynos850-wdt"; + reg =3D <0x10050000 0x100>; + interrupts =3D ; + clocks =3D <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; + clock-names =3D "watchdog", "watchdog_src"; + samsung,syscon-phandle =3D <&pmu_system_controller>; + samsung,cluster-index =3D <0>; + status =3D "disabled"; + }; + + watchdog_cl1: watchdog@10060000 { + compatible =3D "samsung,exynos850-wdt"; + reg =3D <0x10060000 0x100>; + interrupts =3D ; + clocks =3D <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; + clock-names =3D "watchdog", "watchdog_src"; + samsung,syscon-phandle =3D <&pmu_system_controller>; + samsung,cluster-index =3D <1>; + status =3D "disabled"; + }; + + cmu_peri: clock-controller@10030000 { + compatible =3D "samsung,exynos850-cmu-peri"; + reg =3D <0x10030000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names =3D "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + + cmu_apm: clock-controller@11800000 { + compatible =3D "samsung,exynos850-cmu-apm"; + reg =3D <0x11800000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; + clock-names =3D "oscclk", "dout_clkcmu_apm_bus"; + }; + + cmu_cmgp: clock-controller@11c00000 { + compatible =3D "samsung,exynos850-cmu-cmgp"; + reg =3D <0x11c00000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; + clock-names =3D "oscclk", "gout_clkcmu_cmgp_bus"; + }; + + cmu_core: clock-controller@12000000 { + compatible =3D "samsung,exynos850-cmu-core"; + reg =3D <0x12000000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, + <&cmu_top CLK_DOUT_CORE_SSS>; + clock-names =3D "oscclk", "dout_core_bus", + "dout_core_cci", "dout_core_mmc_embd", + "dout_core_sss"; + }; + + cmu_top: clock-controller@120e0000 { + compatible =3D "samsung,exynos850-cmu-top"; + reg =3D <0x120e0000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>; + clock-names =3D "oscclk"; + }; + + cmu_dpu: clock-controller@13000000 { + compatible =3D "samsung,exynos850-cmu-dpu"; + reg =3D <0x13000000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_DPU>; + clock-names =3D "oscclk", "dout_dpu"; + }; + + cmu_hsi: clock-controller@13400000 { + compatible =3D "samsung,exynos850-cmu-hsi"; + reg =3D <0x13400000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names =3D "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible =3D "samsung,exynos850-pinctrl"; + reg =3D <0x11850000 0x1000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible =3D "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible =3D "samsung,exynos850-pinctrl"; + reg =3D <0x11c30000 0x1000>; + interrupts =3D , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible =3D "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_core: pinctrl@12070000 { + compatible =3D "samsung,exynos850-pinctrl"; + reg =3D <0x12070000 0x1000>; + interrupts =3D ; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible =3D "samsung,exynos850-pinctrl"; + reg =3D <0x13430000 0x1000>; + interrupts =3D ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible =3D "samsung,exynos850-pinctrl"; + reg =3D <0x139b0000 0x1000>; + interrupts =3D ; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible =3D "samsung,exynos850-pinctrl"; + reg =3D <0x14a60000 0x1000>; + }; + + rtc: rtc@11a30000 { + compatible =3D "samsung,s3c6410-rtc"; + reg =3D <0x11a30000 0x100>; + interrupts =3D , + ; + clocks =3D <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names =3D "rtc", "rtc_src"; + status =3D "disabled"; + }; + + mmc_0: mmc@12100000 { + compatible =3D "samsung,exynos7-dw-mshc-smu"; + reg =3D <0x12100000 0x2000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names =3D "biu", "ciu"; + fifo-depth =3D <0x40>; + status =3D "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13830000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13840000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13850000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13860000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13870000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ + i2c_5: i2c@13880000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13880000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + /* I2C_6 (also called MOTOR_I2C in TRM) */ + i2c_6: i2c@13890000 { + compatible =3D "samsung,s3c2440-i2c"; + reg =3D <0x13890000 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + clocks =3D <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names =3D "i2c"; + status =3D "disabled"; + }; + + sysreg_peri: syscon@10020000 { + compatible =3D "samsung,exynos850-sysreg", "syscon"; + reg =3D <0x10020000 0x10000>; + clocks =3D <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; + }; + + sysreg_cmgp: syscon@11c20000 { + compatible =3D "samsung,exynos850-sysreg", "syscon"; + reg =3D <0x11c20000 0x10000>; + clocks =3D <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; + }; + + usi_uart: usi@138200c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x138200c0 0x20>; + samsung,sysreg =3D <&sysreg_peri 0x1010>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + + serial_0: serial@13820000 { + compatible =3D "samsung,exynos850-uart"; + reg =3D <0x13820000 0xc0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + clocks =3D <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names =3D "uart", "clk_uart_baud0"; + status =3D "disabled"; + }; + }; + + usi_hsi2c_0: usi@138a00c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x138a00c0 0x20>; + samsung,sysreg =3D <&sysreg_peri 0x1020>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + + hsi2c_0: i2c@138a0000 { + compatible =3D "samsung,exynosautov9-hsi2c"; + reg =3D <0x138a0000 0xc0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hsi2c0_pins>; + clocks =3D <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + status =3D "disabled"; + }; + }; + + usi_hsi2c_1: usi@138b00c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x138b00c0 0x20>; + samsung,sysreg =3D <&sysreg_peri 0x1030>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + + hsi2c_1: i2c@138b0000 { + compatible =3D "samsung,exynosautov9-hsi2c"; + reg =3D <0x138b0000 0xc0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hsi2c1_pins>; + clocks =3D <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + status =3D "disabled"; + }; + }; + + usi_hsi2c_2: usi@138c00c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x138c00c0 0x20>; + samsung,sysreg =3D <&sysreg_peri 0x1040>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + + hsi2c_2: i2c@138c0000 { + compatible =3D "samsung,exynosautov9-hsi2c"; + reg =3D <0x138c0000 0xc0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hsi2c2_pins>; + clocks =3D <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + status =3D "disabled"; + }; + }; + + usi_spi_0: usi@139400c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x139400c0 0x20>; + samsung,sysreg =3D <&sysreg_peri 0x1050>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + }; + + usi_cmgp0: usi@11d000c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x11d000c0 0x20>; + samsung,sysreg =3D <&sysreg_cmgp 0x2000>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + + hsi2c_3: i2c@11d00000 { + compatible =3D "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d00000 0xc0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hsi2c3_pins>; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + status =3D "disabled"; + }; + + serial_1: serial@11d00000 { + compatible =3D "samsung,exynos850-uart"; + reg =3D <0x11d00000 0xc0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_single_pins>; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names =3D "uart", "clk_uart_baud0"; + status =3D "disabled"; + }; + }; + + usi_cmgp1: usi@11d200c0 { + compatible =3D "samsung,exynos850-usi"; + reg =3D <0x11d200c0 0x20>; + samsung,sysreg =3D <&sysreg_cmgp 0x2010>; + samsung,mode =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names =3D "pclk", "ipclk"; + status =3D "disabled"; + + hsi2c_4: i2c@11d20000 { + compatible =3D "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d20000 0xc0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hsi2c4_pins>; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + status =3D "disabled"; + }; + + serial_2: serial@11d20000 { + compatible =3D "samsung,exynos850-uart"; + reg =3D <0x11d20000 0xc0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_single_pins>; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names =3D "uart", "clk_uart_baud0"; + status =3D "disabled"; + }; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi" --=20 2.30.2 From nobody Wed Jul 1 18:37:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FC55C433F5 for ; Fri, 17 Dec 2021 01:30:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231934AbhLQBa1 (ORCPT ); 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Thu, 16 Dec 2021 17:30:18 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , Hao Fang , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 7/7] arm64: dts: exynos: Add initial E850-96 board support Date: Fri, 17 Dec 2021 03:30:05 +0200 Message-Id: <20211217013005.16646-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211217013005.16646-1-semen.protsenko@linaro.org> References: <20211217013005.16646-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" E850-96 is a 96boards development board manufactured by WinLink. It incorporates Samsung Exynos850 SoC, and is compatible with 96boards mezzanine boards [1], as it follows 96boards standards. This patch adds minimal support for E850-96 board. Next features are enabled in board dts file and verified with minimal BusyBox rootfs: * User buttons * LEDs * Serial console * Watchdog timers * RTC * eMMC [1] https://www.96boards.org/products/mezzanine/ Signed-off-by: Sam Protsenko --- Changes in v2: - Removed board_id and board_rev properties - Removed BOARD_ID and BOARD_REV constants - Put dtb in alphabetical order in Makefile - Added "color" and "function" properties to LED nodes - Sorted all phandle overrides by phandle name - Removed 'broken-cd' property in eMMC node - Added memory node arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/exynos850-e850-96.dts | 175 ++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-e850-96.dts diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exyn= os/Makefile index b41e86df0a84..be9df8e85c59 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_EXYNOS) +=3D \ exynos5433-tm2.dtb \ exynos5433-tm2e.dtb \ exynos7-espresso.dtb \ + exynos850-e850-96.dtb \ exynosautov9-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/= boot/dts/exynos/exynos850-e850-96.dts new file mode 100644 index 000000000000..952a47c417d4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include +#include +#include + +/ { + model =3D "WinLink E850-96 board"; + compatible =3D "winlink,e850-96", "samsung,exynos850"; + + chosen { + stdout-path =3D &serial_0; + }; + + /* + * 4 GiB eMCP: + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label =3D "Volume Down"; + linux,code =3D ; + gpios =3D <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label =3D "yellow:user1"; + gpios =3D <&gpg2 2 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + linux,default-trigger =3D "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label =3D "yellow:user2"; + gpios =3D <&gpg2 3 GPIO_ACTIVE_HIGH>; + color =3D ; + linux,default-trigger =3D "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label =3D "white:user3"; + gpios =3D <&gpg2 4 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_SD; + linux,default-trigger =3D "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label =3D "yellow:wlan"; + gpios =3D <&gpg2 6 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_WLAN; + linux,default-trigger =3D "phy0tx"; + default-state =3D "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label =3D "blue:bt"; + gpios =3D <&gpg2 7 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_BLUETOOTH; + linux,default-trigger =3D "hci0rx"; + default-state =3D "off"; + }; + }; +}; + +&mmc_0 { + status =3D "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay =3D <200>; + clock-frequency =3D <800000000>; + bus-width =3D <8>; + samsung,dw-mshc-ciu-div =3D <3>; + samsung,dw-mshc-sdr-timing =3D <0 4>; + samsung,dw-mshc-ddr-timing =3D <2 4>; + samsung,dw-mshc-hs400-timing =3D <0 2>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency =3D <26000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&rtcclk { + clock-frequency =3D <32768>; +}; + +&serial_0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status =3D "okay"; +}; + +&watchdog_cl0 { + status =3D "okay"; +}; + +&watchdog_cl1 { + status =3D "okay"; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins =3D "gpa1-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + key_volup_pins: key-volup-pins { + samsung,pins =3D "gpa0-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; +}; --=20 2.30.2