From nobody Sun Sep 22 13:27:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9DFFC433F5 for ; Thu, 16 Dec 2021 09:46:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235615AbhLPJqH (ORCPT ); Thu, 16 Dec 2021 04:46:07 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:42722 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235586AbhLPJqC (ORCPT ); Thu, 16 Dec 2021 04:46:02 -0500 X-UUID: 8f1c67299711407097aa6afea30eebc9-20211216 X-UUID: 8f1c67299711407097aa6afea30eebc9-20211216 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2043667629; Thu, 16 Dec 2021 17:45:56 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 17:45:55 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Dec 2021 17:45:54 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 17:45:53 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , AngeloGioacchino Del Regno , "Steve Cho" , , , , , , , Subject: [PATCH v16, 01/19] media: mtk-vcodec: Get numbers of register bases from DT Date: Thu, 16 Dec 2021 17:45:34 +0800 Message-ID: <20211216094552.19104-2-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216094552.19104-1-yunfei.dong@mediatek.com> References: <20211216094552.19104-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Different platforms may have different numbers of register bases. Gets the numbers of register bases from dts (sizeof(u32) * 4 bytes for each). Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih --- .../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 37 ++++++++++++++----- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drive= rs/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index 40c39e1e596b..e1a82e233971 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -75,6 +75,30 @@ static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, v= oid *priv) return IRQ_HANDLED; } =20 +static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_dev *dev) +{ + struct platform_device *pdev =3D dev->plat_dev; + int reg_num, i; + + /* Sizeof(u32) * 4 bytes for each register base. */ + reg_num =3D of_property_count_elems_of_size(pdev->dev.of_node, "reg", + sizeof(u32) * 4); + if (reg_num <=3D 0 || reg_num > NUM_MAX_VDEC_REG_BASE) { + dev_err(&pdev->dev, "Invalid register property size: %d\n", reg_num); + return -EINVAL; + } + + for (i =3D 0; i < reg_num; i++) { + dev->reg_base[i] =3D devm_platform_ioremap_resource(pdev, i); + if (IS_ERR(dev->reg_base[i])) + return PTR_ERR(dev->reg_base[i]); + + mtk_v4l2_debug(2, "reg[%d] base=3D%p", i, dev->reg_base[i]); + } + + return 0; +} + static int fops_vcodec_open(struct file *file) { struct mtk_vcodec_dev *dev =3D video_drvdata(file); @@ -203,7 +227,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) struct resource *res; phandle rproc_phandle; enum mtk_vcodec_fw_type fw_type; - int i, ret; + int ret; =20 dev =3D devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); if (!dev) @@ -235,14 +259,9 @@ static int mtk_vcodec_probe(struct platform_device *pd= ev) goto err_dec_pm; } =20 - for (i =3D 0; i < NUM_MAX_VDEC_REG_BASE; i++) { - dev->reg_base[i] =3D devm_platform_ioremap_resource(pdev, i); - if (IS_ERR((__force void *)dev->reg_base[i])) { - ret =3D PTR_ERR((__force void *)dev->reg_base[i]); - goto err_res; - } - mtk_v4l2_debug(2, "reg[%d] base=3D%p", i, dev->reg_base[i]); - } + ret =3D mtk_vcodec_get_reg_bases(dev); + if (ret) + goto err_res; =20 res =3D platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (res =3D=3D NULL) { --=20 2.25.1