From nobody Sun Sep 22 13:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BB5C4332F for ; Thu, 16 Dec 2021 05:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233800AbhLPFxo (ORCPT ); Thu, 16 Dec 2021 00:53:44 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:53036 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231216AbhLPFxj (ORCPT ); Thu, 16 Dec 2021 00:53:39 -0500 X-UUID: caf82160551d4495af144b8943f7e0fc-20211216 X-UUID: caf82160551d4495af144b8943f7e0fc-20211216 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 583237697; Thu, 16 Dec 2021 13:53:35 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 13:53:33 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:32 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 3/6] arm64: dts: mt2712: update ethernet device node Date: Thu, 16 Dec 2021 13:53:25 +0800 Message-ID: <20211216055328.15953-4-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since there are some changes in ethernet driver: update ethernet device node in dts to accommodate to it. 1. stmmac_probe_config_dt() in stmmac_platform.c will initialize specified parameters according to compatible string "snps,dwmac-4.20a", then, dwmac-mediatek.c can skip the initialization if add compatible string "snps,dwmac-4.20a" in eth device node. 2. commit 882007ed7832 added rmii internal support, we should add corresponding clocks/clocks-names in eth device node. 3. add "snps,reset-delays-us =3D <0 10000 10000>;" to ensure reset delay can meet PHY requirement. Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 14 +++++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/= dts/mediatek/mt2712-evb.dts index 7d369fdd3117..11aa135aa0f3 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -110,6 +110,7 @@ ð { phy-handle =3D <ðernet_phy0>; mediatek,tx-delay-ps =3D <1530>; snps,reset-gpio =3D <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us =3D <0 10000 10000>; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <ð_default>; pinctrl-1 =3D <ð_sleep>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dt= s/mediatek/mt2712e.dtsi index a9cca9c146fd..9e850e04fffb 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -726,7 +726,7 @@ queue2 { }; =20 eth: ethernet@1101c000 { - compatible =3D "mediatek,mt2712-gmac"; + compatible =3D "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; reg =3D <0 0x1101c000 0 0x1300>; interrupts =3D ; interrupt-names =3D "macirq"; @@ -734,15 +734,19 @@ eth: ethernet@1101c000 { clock-names =3D "axi", "apb", "mac_main", - "ptp_ref"; + "ptp_ref", + "rmii_internal"; clocks =3D <&pericfg CLK_PERI_GMAC>, <&pericfg CLK_PERI_GMAC_PCLK>, <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clocks =3D <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clock-parents =3D <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>; + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; power-domains =3D <&scpsys MT2712_POWER_DOMAIN_AUDIO>; mediatek,pericfg =3D <&pericfg>; snps,axi-config =3D <&stmmac_axi_setup>; --=20 2.25.1