From nobody Mon Nov 11 15:15:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBCAFC433FE for ; Thu, 16 Dec 2021 05:53:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231534AbhLPFxh (ORCPT ); Thu, 16 Dec 2021 00:53:37 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:41082 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231216AbhLPFxe (ORCPT ); Thu, 16 Dec 2021 00:53:34 -0500 X-UUID: 101fca8982ee46e7aec884725b21e306-20211216 X-UUID: 101fca8982ee46e7aec884725b21e306-20211216 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 826440103; Thu, 16 Dec 2021 13:53:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 16 Dec 2021 13:53:31 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:29 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 1/6] stmmac: dwmac-mediatek: add platform level clocks management Date: Thu, 16 Dec 2021 13:53:23 +0800 Message-ID: <20211216055328.15953-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch implements clks_config callback for dwmac-mediatek platform, which could support platform level clocks management. Signed-off-by: Biao Huang Acked-by: AngeloGioacchino Del Regno --- .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 58c0feaa8131..0ff57c268dca 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include =20 @@ -359,9 +358,6 @@ static int mediatek_dwmac_init(struct platform_device *= pdev, void *priv) return ret; } =20 - pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - return 0; } =20 @@ -370,11 +366,25 @@ static void mediatek_dwmac_exit(struct platform_devic= e *pdev, void *priv) struct mediatek_dwmac_plat_data *plat =3D priv; =20 clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks); - - pm_runtime_put_sync(&pdev->dev); - pm_runtime_disable(&pdev->dev); } =20 +static int mediatek_dwmac_clks_config(void *priv, bool enabled) +{ + struct mediatek_dwmac_plat_data *plat =3D priv; + int ret =3D 0; + + if (enabled) { + ret =3D clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks); + if (ret) { + dev_err(plat->dev, "failed to enable clks, err =3D %d\n", ret); + return ret; + } + } else { + clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks); + } + + return ret; +} static int mediatek_dwmac_probe(struct platform_device *pdev) { struct mediatek_dwmac_plat_data *priv_plat; @@ -420,6 +430,7 @@ static int mediatek_dwmac_probe(struct platform_device = *pdev) plat_dat->bsp_priv =3D priv_plat; plat_dat->init =3D mediatek_dwmac_init; plat_dat->exit =3D mediatek_dwmac_exit; + plat_dat->clks_config =3D mediatek_dwmac_clks_config; mediatek_dwmac_init(pdev, priv_plat); =20 ret =3D stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); --=20 2.25.1 From nobody Mon Nov 11 15:15:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70549C433EF for ; Thu, 16 Dec 2021 05:53:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231819AbhLPFxm (ORCPT ); Thu, 16 Dec 2021 00:53:42 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:41162 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231473AbhLPFxh (ORCPT ); Thu, 16 Dec 2021 00:53:37 -0500 X-UUID: 8d15d11666744ee785e24c5826ab5572-20211216 X-UUID: 8d15d11666744ee785e24c5826ab5572-20211216 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1238631814; Thu, 16 Dec 2021 13:53:33 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 13:53:32 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:31 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 2/6] stmmac: dwmac-mediatek: Reuse more common features Date: Thu, 16 Dec 2021 13:53:24 +0800 Message-ID: <20211216055328.15953-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch makes dwmac-mediatek reuse more features supported by stmmac_platform.c. Signed-off-by: Biao Huang Acked-by: AngeloGioacchino Del Regno --- .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 32 +++++++++---------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 0ff57c268dca..8747aa4403e8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -334,22 +334,20 @@ static int mediatek_dwmac_init(struct platform_device= *pdev, void *priv) const struct mediatek_dwmac_variant *variant =3D plat->variant; int ret; =20 - ret =3D dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bi= t_mask)); - if (ret) { - dev_err(plat->dev, "No suitable DMA available, err =3D %d\n", ret); - return ret; - } - - ret =3D variant->dwmac_set_phy_interface(plat); - if (ret) { - dev_err(plat->dev, "failed to set phy interface, err =3D %d\n", ret); - return ret; + if (variant->dwmac_set_phy_interface) { + ret =3D variant->dwmac_set_phy_interface(plat); + if (ret) { + dev_err(plat->dev, "failed to set phy interface, err =3D %d\n", ret); + return ret; + } } =20 - ret =3D variant->dwmac_set_delay(plat); - if (ret) { - dev_err(plat->dev, "failed to set delay value, err =3D %d\n", ret); - return ret; + if (variant->dwmac_set_delay) { + ret =3D variant->dwmac_set_delay(plat); + if (ret) { + dev_err(plat->dev, "failed to set delay value, err =3D %d\n", ret); + return ret; + } } =20 ret =3D clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks); @@ -422,15 +420,15 @@ static int mediatek_dwmac_probe(struct platform_devic= e *pdev) return PTR_ERR(plat_dat); =20 plat_dat->interface =3D priv_plat->phy_mode; - plat_dat->has_gmac4 =3D 1; - plat_dat->has_gmac =3D 0; - plat_dat->pmt =3D 0; + plat_dat->use_phy_wol =3D 1; plat_dat->riwt_off =3D 1; plat_dat->maxmtu =3D ETH_DATA_LEN; + plat_dat->addr64 =3D priv_plat->variant->dma_bit_mask; plat_dat->bsp_priv =3D priv_plat; plat_dat->init =3D mediatek_dwmac_init; plat_dat->exit =3D mediatek_dwmac_exit; plat_dat->clks_config =3D mediatek_dwmac_clks_config; + mediatek_dwmac_init(pdev, priv_plat); =20 ret =3D stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); --=20 2.25.1 From nobody Mon Nov 11 15:15:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BB5C4332F for ; Thu, 16 Dec 2021 05:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233800AbhLPFxo (ORCPT ); Thu, 16 Dec 2021 00:53:44 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:53036 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231216AbhLPFxj (ORCPT ); Thu, 16 Dec 2021 00:53:39 -0500 X-UUID: caf82160551d4495af144b8943f7e0fc-20211216 X-UUID: caf82160551d4495af144b8943f7e0fc-20211216 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 583237697; Thu, 16 Dec 2021 13:53:35 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 13:53:33 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:32 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 3/6] arm64: dts: mt2712: update ethernet device node Date: Thu, 16 Dec 2021 13:53:25 +0800 Message-ID: <20211216055328.15953-4-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since there are some changes in ethernet driver: update ethernet device node in dts to accommodate to it. 1. stmmac_probe_config_dt() in stmmac_platform.c will initialize specified parameters according to compatible string "snps,dwmac-4.20a", then, dwmac-mediatek.c can skip the initialization if add compatible string "snps,dwmac-4.20a" in eth device node. 2. commit 882007ed7832 added rmii internal support, we should add corresponding clocks/clocks-names in eth device node. 3. add "snps,reset-delays-us =3D <0 10000 10000>;" to ensure reset delay can meet PHY requirement. Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 14 +++++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/= dts/mediatek/mt2712-evb.dts index 7d369fdd3117..11aa135aa0f3 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -110,6 +110,7 @@ ð { phy-handle =3D <ðernet_phy0>; mediatek,tx-delay-ps =3D <1530>; snps,reset-gpio =3D <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us =3D <0 10000 10000>; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <ð_default>; pinctrl-1 =3D <ð_sleep>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dt= s/mediatek/mt2712e.dtsi index a9cca9c146fd..9e850e04fffb 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -726,7 +726,7 @@ queue2 { }; =20 eth: ethernet@1101c000 { - compatible =3D "mediatek,mt2712-gmac"; + compatible =3D "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; reg =3D <0 0x1101c000 0 0x1300>; interrupts =3D ; interrupt-names =3D "macirq"; @@ -734,15 +734,19 @@ eth: ethernet@1101c000 { clock-names =3D "axi", "apb", "mac_main", - "ptp_ref"; + "ptp_ref", + "rmii_internal"; clocks =3D <&pericfg CLK_PERI_GMAC>, <&pericfg CLK_PERI_GMAC_PCLK>, <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clocks =3D <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clock-parents =3D <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>; + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; power-domains =3D <&scpsys MT2712_POWER_DOMAIN_AUDIO>; mediatek,pericfg =3D <&pericfg>; snps,axi-config =3D <&stmmac_axi_setup>; --=20 2.25.1 From nobody Mon Nov 11 15:15:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEF2CC43219 for ; Thu, 16 Dec 2021 05:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233833AbhLPFxp (ORCPT ); Thu, 16 Dec 2021 00:53:45 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:53084 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231558AbhLPFxk (ORCPT ); Thu, 16 Dec 2021 00:53:40 -0500 X-UUID: 4ffb45faf87248a288737d91a51ad5c7-20211216 X-UUID: 4ffb45faf87248a288737d91a51ad5c7-20211216 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2089692171; Thu, 16 Dec 2021 13:53:36 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 16 Dec 2021 13:53:34 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:33 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 4/6] net: dt-bindings: dwmac: Convert mediatek-dwmac to DT schema Date: Thu, 16 Dec 2021 13:53:26 +0800 Message-ID: <20211216055328.15953-5-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert mediatek-dwmac to DT schema, and delete old mediatek-dwmac.txt. And there are some changes in .yaml than .txt, others almost keep the same: 1. compatible "const: snps,dwmac-4.20". 2. delete "snps,reset-active-low;" in example, since driver remove this property long ago. 3. add "snps,reset-delay-us =3D <0 10000 10000>" in example. 4. the example is for rgmii interface, keep related properties only. Signed-off-by: Biao Huang --- .../bindings/net/mediatek-dwmac.txt | 91 ---------- .../bindings/net/mediatek-dwmac.yaml | 155 ++++++++++++++++++ 2 files changed, 155 insertions(+), 91 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.ya= ml diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Doc= umentation/devicetree/bindings/net/mediatek-dwmac.txt deleted file mode 100644 index afbcaebf062e..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt +++ /dev/null @@ -1,91 +0,0 @@ -MediaTek DWMAC glue layer controller - -This file documents platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -The device node has following properties. - -Required properties: -- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC -- reg: Address and length of the register set for the device -- interrupts: Should contain the MAC interrupts -- interrupt-names: Should contain a list of interrupt names corresponding = to - the interrupts in the interrupts property, if available. - Should be "macirq" for the main MAC IRQ -- clocks: Must contain a phandle for each entry in clock-names. -- clock-names: The name of the clock listed in the clocks property. These = are - "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC. -- mac-address: See ethernet.txt in the same directory -- phy-mode: See ethernet.txt in the same directory -- mediatek,pericfg: A phandle to the syscon node that control ethernet - interface and timing delay. - -Optional properties: -- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. - It should be defined for RGMII/MII interface. - It should be defined for RMII interface when the reference clock is from = MT2712 SoC. -- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. - It should be defined for RGMII/MII interface. - It should be defined for RMII interface. -Both delay properties need to be a multiple of 170 for RGMII interface, -or will round down. Range 0~31*170. -Both delay properties need to be a multiple of 550 for MII/RMII interface, -or will round down. Range 0~31*550. - -- mediatek,rmii-rxc: boolean property, if present indicates that the RMII - reference clock, which is from external PHYs, is connected to RXC pin - on MT2712 SoC. - Otherwise, is connected to TXC pin. -- mediatek,rmii-clk-from-mac: boolean property, if present indicates that - MT2712 SoC provides the RMII reference clock, which outputs to TXC pin on= ly. -- mediatek,txc-inverse: boolean property, if present indicates that - 1. tx clock will be inversed in MII/RGMII case, - 2. tx clock inside MAC will be inversed relative to reference clock - which is from external PHYs in RMII case, and it rarely happen. - 3. the reference clock, which outputs to TXC pin will be inversed in RMII= case - when the reference clock is from MT2712 SoC. -- mediatek,rxc-inverse: boolean property, if present indicates that - 1. rx clock will be inversed in MII/RGMII case. - 2. reference clock will be inversed when arrived at MAC in RMII case, when - the reference clock is from external PHYs. - 3. the inside clock, which be sent to MAC, will be inversed in RMII case = when - the reference clock is from MT2712 SoC. -- assigned-clocks: mac_main and ptp_ref clocks -- assigned-clock-parents: parent clocks of the assigned clocks - -Example: - eth: ethernet@1101c000 { - compatible =3D "mediatek,mt2712-gmac"; - reg =3D <0 0x1101c000 0 0x1300>; - interrupts =3D ; - interrupt-names =3D "macirq"; - phy-mode =3D"rgmii-rxid"; - mac-address =3D [00 55 7b b5 7d f7]; - clock-names =3D "axi", - "apb", - "mac_main", - "ptp_ref", - "rmii_internal"; - clocks =3D <&pericfg CLK_PERI_GMAC>, - <&pericfg CLK_PERI_GMAC_PCLK>, - <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; - assigned-clocks =3D <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; - assigned-clock-parents =3D <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>, - <&topckgen CLK_TOP_ETHERPLL_50M>; - power-domains =3D <&scpsys MT2712_POWER_DOMAIN_AUDIO>; - mediatek,pericfg =3D <&pericfg>; - mediatek,tx-delay-ps =3D <1530>; - mediatek,rx-delay-ps =3D <1530>; - mediatek,rmii-rxc; - mediatek,txc-inverse; - mediatek,rxc-inverse; - snps,txpbl =3D <1>; - snps,rxpbl =3D <1>; - snps,reset-gpio =3D <&pio 87 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - }; diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Do= cumentation/devicetree/bindings/net/mediatek-dwmac.yaml new file mode 100644 index 000000000000..8ad6e19661b8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DWMAC glue layer controller + +maintainers: + - Biao Huang + +description: + This file documents platform glue layer for stmmac. + +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - mediatek,mt2712-gmac + required: + - compatible + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + items: + - enum: + - mediatek,mt2712-gmac + - const: snps,dwmac-4.20a + + clocks: + items: + - description: AXI clock + - description: APB clock + - description: MAC Main clock + - description: PTP clock + - description: RMII reference clock provided by MAC + + clock-names: + items: + - const: axi + - const: apb + - const: mac_main + - const: ptp_ref + - const: rmii_internal + + mediatek,pericfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the syscon node that control ethernet + interface and timing delay. + + mediatek,tx-delay-ps: + description: + The internal TX clock delay (provided by this driver) in nanoseconds. + For MT2712 RGMII interface, Allowed value need to be a multiple of 1= 70, + or will round down. Range 0~31*170. + For MT2712 RMII/MII interface, Allowed value need to be a multiple o= f 550, + or will round down. Range 0~31*550. + + mediatek,rx-delay-ps: + description: + The internal RX clock delay (provided by this driver) in nanoseconds. + For MT2712 RGMII interface, Allowed value need to be a multiple of 1= 70, + or will round down. Range 0~31*170. + For MT2712 RMII/MII interface, Allowed value need to be a multiple o= f 550, + or will round down. Range 0~31*550. + + mediatek,rmii-rxc: + type: boolean + description: + If present, indicates that the RMII reference clock, which is from e= xternal + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. + + mediatek,rmii-clk-from-mac: + type: boolean + description: + If present, indicates that MAC provides the RMII reference clock, wh= ich + outputs to TXC pin only. + + mediatek,txc-inverse: + type: boolean + description: + If present, indicates that + 1. tx clock will be inversed in MII/RGMII case, + 2. tx clock inside MAC will be inversed relative to reference clock + which is from external PHYs in RMII case, and it rarely happen. + 3. the reference clock, which outputs to TXC pin will be inversed in= RMII case + when the reference clock is from MAC. + + mediatek,rxc-inverse: + type: boolean + description: + If present, indicates that + 1. rx clock will be inversed in MII/RGMII case. + 2. reference clock will be inversed when arrived at MAC in RMII case= , when + the reference clock is from external PHYs. + 3. the inside clock, which be sent to MAC, will be inversed in RMII = case when + the reference clock is from MAC. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - phy-mode + - mediatek,pericfg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + eth: ethernet@1101c000 { + compatible =3D "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; + reg =3D <0x1101c000 0x1300>; + interrupts =3D ; + interrupt-names =3D "macirq"; + phy-mode =3D"rgmii-rxid"; + mac-address =3D [00 55 7b b5 7d f7]; + clock-names =3D "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks =3D <&pericfg CLK_PERI_GMAC>, + <&pericfg CLK_PERI_GMAC_PCLK>, + <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; + assigned-clocks =3D <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ETHERPLL_125M>, + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; + power-domains =3D <&scpsys MT2712_POWER_DOMAIN_AUDIO>; + mediatek,pericfg =3D <&pericfg>; + mediatek,tx-delay-ps =3D <1530>; + snps,txpbl =3D <1>; + snps,rxpbl =3D <1>; + snps,reset-gpio =3D <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us =3D <0 10000 10000>; + }; --=20 2.25.1 From nobody Mon Nov 11 15:15:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50CE0C4321E for ; Thu, 16 Dec 2021 05:53:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233865AbhLPFxr (ORCPT ); Thu, 16 Dec 2021 00:53:47 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:41286 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231607AbhLPFxk (ORCPT ); Thu, 16 Dec 2021 00:53:40 -0500 X-UUID: 5763d44d4f30469fa132f2362060cbb7-20211216 X-UUID: 5763d44d4f30469fa132f2362060cbb7-20211216 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 576991927; Thu, 16 Dec 2021 13:53:37 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 13:53:36 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:34 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 5/6] stmmac: dwmac-mediatek: add support for mt8195 Date: Thu, 16 Dec 2021 13:53:27 +0800 Message-ID: <20211216055328.15953-6-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet support for MediaTek SoCs from the mt8195 family. Signed-off-by: Biao Huang Acked-by: AngeloGioacchino Del Regno --- .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 253 +++++++++++++++++- 1 file changed, 252 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 8747aa4403e8..bbb94aeee104 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -39,6 +39,33 @@ #define ETH_FINE_DLY_GTXC BIT(1) #define ETH_FINE_DLY_RXC BIT(0) =20 +/* Peri Configuration register for mt8195 */ +#define MT8195_PERI_ETH_CTRL0 0xFD0 +#define MT8195_RMII_CLK_SRC_INTERNAL BIT(28) +#define MT8195_RMII_CLK_SRC_RXC BIT(27) +#define MT8195_ETH_INTF_SEL GENMASK(26, 24) +#define MT8195_RGMII_TXC_PHASE_CTRL BIT(22) +#define MT8195_EXT_PHY_MODE BIT(21) +#define MT8195_DLY_GTXC_INV BIT(12) +#define MT8195_DLY_GTXC_ENABLE BIT(5) +#define MT8195_DLY_GTXC_STAGES GENMASK(4, 0) + +#define MT8195_PERI_ETH_CTRL1 0xFD4 +#define MT8195_DLY_RXC_INV BIT(25) +#define MT8195_DLY_RXC_ENABLE BIT(18) +#define MT8195_DLY_RXC_STAGES GENMASK(17, 13) +#define MT8195_DLY_TXC_INV BIT(12) +#define MT8195_DLY_TXC_ENABLE BIT(5) +#define MT8195_DLY_TXC_STAGES GENMASK(4, 0) + +#define MT8195_PERI_ETH_CTRL2 0xFD8 +#define MT8195_DLY_RMII_RXC_INV BIT(25) +#define MT8195_DLY_RMII_RXC_ENABLE BIT(18) +#define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13) +#define MT8195_DLY_RMII_TXC_INV BIT(12) +#define MT8195_DLY_RMII_TXC_ENABLE BIT(5) +#define MT8195_DLY_RMII_TXC_STAGES GENMASK(4, 0) + struct mac_delay_struct { u32 tx_delay; u32 rx_delay; @@ -57,11 +84,13 @@ struct mediatek_dwmac_plat_data { int num_clks_to_config; bool rmii_clk_from_mac; bool rmii_rxc; + bool mac_wol; }; =20 struct mediatek_dwmac_variant { int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat); int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat); + void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed); =20 /* clock ids to be requested */ const char * const *clk_list; @@ -77,6 +106,10 @@ static const char * const mt2712_dwmac_clk_l[] =3D { "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" }; =20 +static const char * const mt8195_dwmac_clk_l[] =3D { + "axi", "apb", "mac_cg", "mac_main", "ptp_ref", "rmii_internal" +}; + static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat) { int rmii_clk_from_mac =3D plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL= : 0; @@ -267,6 +300,204 @@ static const struct mediatek_dwmac_variant mt2712_gma= c_variant =3D { .tx_delay_max =3D 17600, }; =20 +static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat) +{ + int rmii_clk_from_mac =3D plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_I= NTERNAL : 0; + int rmii_rxc =3D plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0; + u32 intf_val =3D 0; + + /* The clock labeled as "rmii_internal" in mt8195_dwmac_clk_l is needed + * only in RMII(when MAC provides the reference clock), and useless for + * RGMII/MII/RMII(when PHY provides the reference clock). + * num_clks_to_config indicates the real number of clocks should be + * configured, equals to (plat->variant->num_clks - 1) in default for all= the case, + * then +1 for rmii_clk_from_mac case. + */ + plat->num_clks_to_config =3D plat->variant->num_clks - 1; + + /* select phy interface in top control domain */ + switch (plat->phy_mode) { + case PHY_INTERFACE_MODE_MII: + intf_val |=3D FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII); + break; + case PHY_INTERFACE_MODE_RMII: + if (plat->rmii_clk_from_mac) + plat->num_clks_to_config++; + intf_val |=3D (rmii_rxc | rmii_clk_from_mac); + intf_val |=3D FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + intf_val |=3D FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII); + break; + default: + dev_err(plat->dev, "phy interface not supported\n"); + return -EINVAL; + } + + /* MT8195 only support external PHY */ + intf_val |=3D MT8195_EXT_PHY_MODE; + + regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); + + return 0; +} + +static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) +{ + struct mac_delay_struct *mac_delay =3D &plat->mac_delay; + + /* 290ps per stage */ + mac_delay->tx_delay /=3D 290; + mac_delay->rx_delay /=3D 290; +} + +static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) +{ + struct mac_delay_struct *mac_delay =3D &plat->mac_delay; + + /* 290ps per stage */ + mac_delay->tx_delay *=3D 290; + mac_delay->rx_delay *=3D 290; +} + +static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) +{ + struct mac_delay_struct *mac_delay =3D &plat->mac_delay; + u32 gtxc_delay_val =3D 0, delay_val =3D 0, rmii_delay_val =3D 0; + + mt8195_delay_ps2stage(plat); + + switch (plat->phy_mode) { + case PHY_INTERFACE_MODE_MII: + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv); + + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); + break; + case PHY_INTERFACE_MODE_RMII: + if (plat->rmii_clk_from_mac) { + /* case 1: mac provides the rmii reference clock, + * and the clock output to TXC pin. + * The egress timing can be adjusted by RMII_TXC delay macro circuit. + * The ingress timing can be adjusted by RMII_RXC delay macro circuit. + */ + rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE, + !!mac_delay->tx_delay); + rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES, + mac_delay->tx_delay); + rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_TXC_INV, + mac_delay->tx_inv); + + rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE, + !!mac_delay->rx_delay); + rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_RXC_STAGES, + mac_delay->rx_delay); + rmii_delay_val |=3D FIELD_PREP(MT8195_DLY_RMII_RXC_INV, + mac_delay->rx_inv); + } else { + /* case 2: the rmii reference clock is from external phy, + * and the property "rmii_rxc" indicates which pin(TXC/RXC) + * the reference clk is connected to. The reference clock is a + * received signal, so rx_delay/rx_inv are used to indicate + * the reference clock timing adjustment + */ + if (plat->rmii_rxc) { + /* the rmii reference clock from outside is connected + * to RXC pin, the reference clock will be adjusted + * by RXC delay macro circuit. + */ + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, + !!mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, + mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_INV, + mac_delay->rx_inv); + } else { + /* the rmii reference clock from outside is connected + * to TXC pin, the reference clock will be adjusted + * by TXC delay macro circuit. + */ + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_ENABLE, + !!mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_STAGES, + mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_TXC_INV, + mac_delay->rx_inv); + } + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_d= elay); + gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_del= ay); + gtxc_delay_val |=3D FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv); + + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); + delay_val |=3D FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); + + break; + default: + dev_err(plat->dev, "phy interface not supported\n"); + return -EINVAL; + } + + regmap_update_bits(plat->peri_regmap, + MT8195_PERI_ETH_CTRL0, + MT8195_RGMII_TXC_PHASE_CTRL | + MT8195_DLY_GTXC_INV | + MT8195_DLY_GTXC_ENABLE | + MT8195_DLY_GTXC_STAGES, + gtxc_delay_val); + regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); + regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); + + mt8195_delay_stage2ps(plat); + + return 0; +} + +static void mt8195_fix_mac_speed(void *priv, unsigned int speed) +{ + struct mediatek_dwmac_plat_data *priv_plat =3D priv; + + if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) { + /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL, + * when link speed is 1Gbps with RGMII interface, + * Fall back to delay macro circuit for 10/100Mbps link speed. + */ + if (speed =3D=3D SPEED_1000) + regmap_update_bits(priv_plat->peri_regmap, + MT8195_PERI_ETH_CTRL0, + MT8195_RGMII_TXC_PHASE_CTRL | + MT8195_DLY_GTXC_ENABLE | + MT8195_DLY_GTXC_INV | + MT8195_DLY_GTXC_STAGES, + MT8195_RGMII_TXC_PHASE_CTRL); + else + mt8195_set_delay(priv_plat); + } +} + +static const struct mediatek_dwmac_variant mt8195_gmac_variant =3D { + .dwmac_set_phy_interface =3D mt8195_set_interface, + .dwmac_set_delay =3D mt8195_set_delay, + .dwmac_fix_mac_speed =3D mt8195_fix_mac_speed, + .clk_list =3D mt8195_dwmac_clk_l, + .num_clks =3D ARRAY_SIZE(mt8195_dwmac_clk_l), + .dma_bit_mask =3D 35, + .rx_delay_max =3D 9280, + .tx_delay_max =3D 9280, +}; + static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay =3D &plat->mac_delay; @@ -307,6 +538,7 @@ static int mediatek_dwmac_config_dt(struct mediatek_dwm= ac_plat_data *plat) mac_delay->rx_inv =3D of_property_read_bool(plat->np, "mediatek,rxc-inver= se"); plat->rmii_rxc =3D of_property_read_bool(plat->np, "mediatek,rmii-rxc"); plat->rmii_clk_from_mac =3D of_property_read_bool(plat->np, "mediatek,rmi= i-clk-from-mac"); + plat->mac_wol =3D of_property_read_bool(plat->np, "mediatek,mac-wol"); =20 return 0; } @@ -383,6 +615,7 @@ static int mediatek_dwmac_clks_config(void *priv, bool = enabled) =20 return ret; } + static int mediatek_dwmac_probe(struct platform_device *pdev) { struct mediatek_dwmac_plat_data *priv_plat; @@ -420,7 +653,7 @@ static int mediatek_dwmac_probe(struct platform_device = *pdev) return PTR_ERR(plat_dat); =20 plat_dat->interface =3D priv_plat->phy_mode; - plat_dat->use_phy_wol =3D 1; + plat_dat->use_phy_wol =3D priv_plat->mac_wol ? 0 : 1; plat_dat->riwt_off =3D 1; plat_dat->maxmtu =3D ETH_DATA_LEN; plat_dat->addr64 =3D priv_plat->variant->dma_bit_mask; @@ -428,7 +661,23 @@ static int mediatek_dwmac_probe(struct platform_device= *pdev) plat_dat->init =3D mediatek_dwmac_init; plat_dat->exit =3D mediatek_dwmac_exit; plat_dat->clks_config =3D mediatek_dwmac_clks_config; + if (priv_plat->variant->dwmac_fix_mac_speed) + plat_dat->fix_mac_speed =3D priv_plat->variant->dwmac_fix_mac_speed; + plat_dat->safety_feat_cfg =3D devm_kzalloc(&pdev->dev, + sizeof(*plat_dat->safety_feat_cfg), + GFP_KERNEL); + if (!plat_dat->safety_feat_cfg) + return -ENOMEM; =20 + plat_dat->safety_feat_cfg->tsoee =3D 1; + plat_dat->safety_feat_cfg->mrxpee =3D 0; + plat_dat->safety_feat_cfg->mestee =3D 1; + plat_dat->safety_feat_cfg->mrxee =3D 1; + plat_dat->safety_feat_cfg->mtxee =3D 1; + plat_dat->safety_feat_cfg->epsi =3D 0; + plat_dat->safety_feat_cfg->edpp =3D 1; + plat_dat->safety_feat_cfg->prtyen =3D 1; + plat_dat->safety_feat_cfg->tmouten =3D 1; mediatek_dwmac_init(pdev, priv_plat); =20 ret =3D stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); @@ -443,6 +692,8 @@ static int mediatek_dwmac_probe(struct platform_device = *pdev) static const struct of_device_id mediatek_dwmac_match[] =3D { { .compatible =3D "mediatek,mt2712-gmac", .data =3D &mt2712_gmac_variant }, + { .compatible =3D "mediatek,mt8195-gmac", + .data =3D &mt8195_gmac_variant }, { } }; =20 --=20 2.25.1 From nobody Mon Nov 11 15:15:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D65FC433F5 for ; Thu, 16 Dec 2021 05:53:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231558AbhLPFxx (ORCPT ); Thu, 16 Dec 2021 00:53:53 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:53150 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231682AbhLPFxm (ORCPT ); Thu, 16 Dec 2021 00:53:42 -0500 X-UUID: 76fa4987f77848d68c39d489cd265db8-20211216 X-UUID: 76fa4987f77848d68c39d489cd265db8-20211216 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1177963592; Thu, 16 Dec 2021 13:53:39 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 13:53:37 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:36 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 6/6] net: dt-bindings: dwmac: add support for mt8195 Date: Thu, 16 Dec 2021 13:53:28 +0800 Message-ID: <20211216055328.15953-7-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding document for the ethernet on mt8195. Signed-off-by: Biao Huang --- .../bindings/net/mediatek-dwmac.yaml | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Do= cumentation/devicetree/bindings/net/mediatek-dwmac.yaml index 8ad6e19661b8..a12f822a9ded 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -19,6 +19,7 @@ select: contains: enum: - mediatek,mt2712-gmac + - mediatek,mt8195-gmac required: - compatible =20 @@ -27,26 +28,36 @@ allOf: =20 properties: compatible: - items: - - enum: - - mediatek,mt2712-gmac - - const: snps,dwmac-4.20a + oneOf: + - items: + - enum: + - mediatek,mt2712-gmac + - const: snps,dwmac-4.20a + - items: + - enum: + - mediatek,mt8195-gmac + - const: snps,dwmac-5.10a =20 clocks: + minItems: 5 items: - description: AXI clock - description: APB clock - description: MAC Main clock - description: PTP clock - description: RMII reference clock provided by MAC + - description: MAC clock gate =20 clock-names: + minItems: 5 + maxItems: 6 items: - const: axi - const: apb - const: mac_main - const: ptp_ref - const: rmii_internal + - const: mac_cg =20 mediatek,pericfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -61,6 +72,8 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple o= f 550, or will round down. Range 0~31*550. + For MT8195 RGMII/RMII/MII interface, Allowed value need to be a mult= iple of 290, + or will round down. Range 0~31*290. =20 mediatek,rx-delay-ps: description: @@ -69,6 +82,8 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple o= f 550, or will round down. Range 0~31*550. + For MT8195 RGMII/RMII/MII interface, Allowed value need to be a mult= iple + of 290, or will round down. Range 0~31*290. =20 mediatek,rmii-rxc: type: boolean @@ -102,6 +117,12 @@ properties: 3. the inside clock, which be sent to MAC, will be inversed in RMII = case when the reference clock is from MAC. =20 + mediatek,mac-wol: + type: boolean + description: + If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WO= L will be enabled. + Otherwise, PHY WOL is perferred. + required: - compatible - reg --=20 2.25.1