From nobody Sun Sep 22 13:36:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4820C433EF for ; Fri, 10 Dec 2021 17:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244933AbhLJR4f (ORCPT ); Fri, 10 Dec 2021 12:56:35 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:44656 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S244808AbhLJR4O (ORCPT ); Fri, 10 Dec 2021 12:56:14 -0500 X-UUID: fe157854d93f49da8b203f4f07e58695-20211211 X-UUID: fe157854d93f49da8b203f4f07e58695-20211211 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2043753425; Sat, 11 Dec 2021 01:52:36 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:52:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:52:35 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen , Yong Wu CC: , , , Flora Fu , JB Tsai Subject: [PATCH 06/12] soc: mediatek: apu: Add MT8195 APU power driver Date: Sat, 11 Dec 2021 01:52:17 +0800 Message-ID: <20211210175223.31131-7-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210175223.31131-1-flora.fu@mediatek.com> References: <20211210175223.31131-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add APU power driver for MT8195 to support for subsys clock and regulator controller. Signed-off-by: Flora Fu --- drivers/soc/mediatek/apusys/apu-pwr.c | 34 ++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/apusys/apu-pwr.c b/drivers/soc/mediatek/a= pusys/apu-pwr.c index e8e54a767aff..73e08b442558 100644 --- a/drivers/soc/mediatek/apusys/apu-pwr.c +++ b/drivers/soc/mediatek/apusys/apu-pwr.c @@ -578,10 +578,25 @@ static struct apupwr_plat_data mt8192_apu_power_data = =3D { .ops =3D &mt8192_pwr_ops, }; =20 +static const struct apupwr_plat_reg mt8195_pwr_reg =3D { + .opp_user =3D 0x40, + .opp_thermal =3D 0x44, + .opp_curr =3D 0x48, + .opp_mask =3D 0xF, +}; + +static struct apupwr_plat_data mt8195_apu_power_data =3D { + .dvfs_user =3D MDLA1, + .plat_regs =3D &mt8195_pwr_reg, +}; + static const struct of_device_id apu_power_of_match[] =3D { { .compatible =3D "mediatek,mt8192-apu-power", .data =3D &mt8192_apu_power_data + }, { + .compatible =3D "mediatek,mt8195-apu-power", + .data =3D &mt8195_apu_power_data }, { /* Terminator */ }, @@ -597,13 +612,30 @@ static struct platform_driver apu_power_driver =3D { }, }; =20 +static const struct of_device_id apu_combo_iommu[] =3D { + { .compatible =3D "mediatek,apu_combo_iommu0"}, + { .compatible =3D "mediatek,apu_combo_iommu1"}, + {}, +}; +MODULE_DEVICE_TABLE(of, apu_combo_iommu); + +static struct platform_driver apu_combo_iommu_driver =3D { + .driver =3D { + .name =3D "apu_combo_iommu", + .of_match_table =3D of_match_ptr(apu_combo_iommu), + }, +}; + static int __init apu_power_drv_init(void) { - return platform_driver_register(&apu_power_driver); + platform_driver_register(&apu_power_driver); + platform_driver_register(&apu_combo_iommu_driver); + return 0; } =20 static void __exit apu_power_drv_exit(void) { + platform_driver_unregister(&apu_combo_iommu_driver); platform_driver_unregister(&apu_power_driver); } =20 --=20 2.18.0