From nobody Sun Sep 22 11:29:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FAE4C433EF for ; Fri, 10 Dec 2021 17:37:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241663AbhLJRlc (ORCPT ); Fri, 10 Dec 2021 12:41:32 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:55978 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S241539AbhLJRl3 (ORCPT ); Fri, 10 Dec 2021 12:41:29 -0500 X-UUID: 3bf8c5b7870c4b4685f65dcd4d5be4e9-20211211 X-UUID: 3bf8c5b7870c4b4685f65dcd4d5be4e9-20211211 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1747369831; Sat, 11 Dec 2021 01:37:51 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 11 Dec 2021 01:37:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:50 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 1/6] dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain Date: Sat, 11 Dec 2021 01:37:38 +0800 Message-ID: <20211210173743.30906-2-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the MT8195 APU power domain bindings. Signed-off-by: Flora Fu --- .../devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm= .yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml index e1b7d4030dc9..66547f899014 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -21,6 +21,7 @@ properties: items: - enum: - mediatek,mt8192-apu-pm + - mediatek,mt8195-apu-pm - const: syscon =20 reg: --=20 2.18.0 From nobody Sun Sep 22 11:29:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E74F5C4332F for ; Fri, 10 Dec 2021 17:37:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241789AbhLJRle (ORCPT ); Fri, 10 Dec 2021 12:41:34 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:33572 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S241632AbhLJRlc (ORCPT ); Fri, 10 Dec 2021 12:41:32 -0500 X-UUID: 345ac04542ae4d06be5dd0e0f4413c7a-20211211 X-UUID: 345ac04542ae4d06be5dd0e0f4413c7a-20211211 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 56710195; Sat, 11 Dec 2021 01:37:53 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Sat, 11 Dec 2021 01:37:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:51 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 2/6] dt-bindings: arm: mediatek: Add MT8195 APU bindings Date: Sat, 11 Dec 2021 01:37:39 +0800 Message-ID: <20211210173743.30906-3-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the MT8195 APU bindings. Signed-off-by: Flora Fu --- .../devicetree/bindings/arm/mediatek/mediatek,apusys.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys= .yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml index 7643c66dfaa2..fe96618ecb71 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml @@ -20,6 +20,9 @@ properties: - enum: - mediatek,mt8192-apu-conn - mediatek,mt8192-apu-vcore + - mediatek,mt8195-apu-conn + - mediatek,mt8195-apu-conn1 + - mediatek,mt8195-apu-vcore - const: syscon =20 reg: --=20 2.18.0 From nobody Sun Sep 22 11:29:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FE91C433FE for ; Fri, 10 Dec 2021 17:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244474AbhLJRlk (ORCPT ); Fri, 10 Dec 2021 12:41:40 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:33584 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S241557AbhLJRld (ORCPT ); Fri, 10 Dec 2021 12:41:33 -0500 X-UUID: d5c6992135e744048f94af3ea3afd25f-20211211 X-UUID: d5c6992135e744048f94af3ea3afd25f-20211211 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 384329904; Sat, 11 Dec 2021 01:37:54 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:53 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:52 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 3/6] soc: mediatek: apu: Add MT8195 apu power domain Date: Sat, 11 Dec 2021 01:37:40 +0800 Message-ID: <20211210173743.30906-4-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8195 apu power domain settings. The clock and pll controller shall be accessed through SMC call and the power domain shall be enable before access MT8195 APU. Signed-off-by: Flora Fu --- drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 +++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c b/drivers/soc/mediate= k/apusys/mtk-apu-pm.c index 10dd30052c46..7be5acb75d78 100644 --- a/drivers/soc/mediatek/apusys/mtk-apu-pm.c +++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -18,9 +19,12 @@ #include #include #include +#include =20 #define APU_PD_IPUIF_HW_CG BIT(0) #define APU_PD_RPC_AUTO_BUCK BIT(1) +#define APU_PD_ACC BIT(2) +#define APU_PD_SEC_PWR BIT(3) #define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x)) =20 #define MTK_POLL_DELAY_US 10 @@ -44,6 +48,11 @@ static const struct reg_sequence mt8192_rpc_sw_type[] = =3D { { MT8192_RPC_SW_TYPE(6), 0x3 }, }; =20 +#define MTK_SIP_APUPWR_BUS_PROT_CG_ON 0x02U +#define MTK_SIP_APUPWR_BULK_PLL 0x03U +#define MTK_SIP_APUPWR_ACC_INIT_ALL 0x04U +#define MTK_SIP_APUPWR_ACC_TOP 0x05U + struct apu_top_domain { u32 spm_ext_buck_iso; u32 spm_ext_buck_iso_mask; @@ -81,6 +90,23 @@ static struct apu_top_domain mt8192_top_reg =3D { .num_rpc_sw =3D ARRAY_SIZE(mt8192_rpc_sw_type), }; =20 +static struct apu_top_domain mt8195_top_reg =3D { + .spm_ext_buck_iso =3D 0x3EC, + .spm_ext_buck_iso_mask =3D 0x21, + .spm_cross_wake_m01 =3D 0x670, + .wake_apu =3D BIT(0), + .spm_other_pwr =3D 0x198, + .pwr_status =3D BIT(4), + .conn_clr =3D 0x8, + .conn1_clr =3D 0x8, + .vcore_clr =3D 0x8, + .rpc_top_con =3D 0x0, + .rpc_top_con_init_mask =3D 0x9E, + .rpc_top_sel =3D 0x4, + .rpc_top_intf_pwr_rdy =3D 0x44, + .pwr_rdy =3D BIT(0), +}; + struct apusys { struct device *dev; struct regmap *scpsys; @@ -125,6 +151,7 @@ static int apu_top_init_hw(struct apu_domain *pd) { struct apusys *apusys =3D pd->apusys; int ret; + struct arm_smccc_res res; =20 if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { ret =3D clk_prepare_enable(pd->clk_top_conn); @@ -148,6 +175,15 @@ static int apu_top_init_hw(struct apu_domain *pd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret =3D res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + } ret =3D clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -181,6 +217,18 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } =20 + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_INIT_ALL, + 0, 0, 0, 0, 0, 0, &res); + ret =3D res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc init all fail: %lu\n", res.a0); + goto err_clk; + } + } + } + if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { clk_disable_unprepare(pd->clk_top_conn); ret =3D clk_set_parent(pd->clk_top_ipu_if, pd->clk_off); @@ -189,6 +237,9 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } =20 @@ -199,6 +250,9 @@ static int apu_top_init_hw(struct apu_domain *pd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } =20 @@ -214,16 +268,31 @@ static const struct apu_domain_data apu_domain_data_m= t8192[] =3D { } }; =20 +static const struct apu_domain_data apu_domain_data_mt8195[] =3D { + { + .domain_idx =3D 0, + .name =3D "apu-top", + .caps =3D APU_PD_RPC_AUTO_BUCK | APU_PD_ACC | APU_PD_SEC_PWR, + .topd =3D &mt8195_top_reg, + } +}; + static const struct apu_pm_data mt8192_apu_pm_data =3D { .domains_data =3D apu_domain_data_mt8192, .num_domains =3D ARRAY_SIZE(apu_domain_data_mt8192), }; =20 +static const struct apu_pm_data mt8195_apu_pm_data =3D { + .domains_data =3D apu_domain_data_mt8195, + .num_domains =3D ARRAY_SIZE(apu_domain_data_mt8195), +}; + static int apu_top_power_on(struct generic_pm_domain *genpd) { struct apu_domain *pd =3D to_apu_domain(genpd); struct apusys *apusys =3D pd->apusys; int ret, tmp; + struct arm_smccc_res res; =20 if (apusys->vsram_supply) { ret =3D regulator_enable(apusys->vsram_supply); @@ -269,6 +338,25 @@ static int apu_top_power_on(struct generic_pm_domain *= genpd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret =3D res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 1, 0, 0, 0, 0, 0, &res); + ret =3D res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + goto err_clk; + } + } + } ret =3D clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -301,6 +389,15 @@ static int apu_top_power_on(struct generic_pm_domain *= genpd) goto err_clk; } =20 + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BUS_PROT_CG_ON, + 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + dev_err(apusys->dev, "apu bus_prot smc fail: %lu\n", res.a0); + goto err_clk; + } + } + if (apusys->vcore) { ret =3D regmap_write(apusys->vcore, pd->data->topd->vcore_clr, CG_CLR); @@ -329,6 +426,9 @@ static int apu_top_power_on(struct generic_pm_domain *g= enpd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } if (pd->domain_supply) @@ -345,6 +445,7 @@ static int apu_top_power_off(struct generic_pm_domain *= genpd) struct apu_domain *pd =3D to_apu_domain(genpd); struct apusys *apusys =3D pd->apusys; int ret, tmp; + struct arm_smccc_res res; =20 if (apusys->vcore) { ret =3D regmap_write(apusys->vcore, @@ -405,6 +506,25 @@ static int apu_top_power_off(struct generic_pm_domain = *genpd) return ret; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 0, 0, 0, 0, 0, 0, &res); + ret =3D res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + return ret; + } + } + + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); + ret =3D res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + return ret; + } + } clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } =20 @@ -610,6 +730,10 @@ static const struct of_device_id apu_pm_of_match[] =3D= { .compatible =3D "mediatek,mt8192-apu-pm", .data =3D &mt8192_apu_pm_data, }, + { + .compatible =3D "mediatek,mt8195-apu-pm", + .data =3D &mt8195_apu_pm_data, + }, { } }; =20 --=20 2.18.0 From nobody Sun Sep 22 11:29:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4528C433F5 for ; Fri, 10 Dec 2021 17:38:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241755AbhLJRln (ORCPT ); Fri, 10 Dec 2021 12:41:43 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:33658 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S241792AbhLJRlf (ORCPT ); Fri, 10 Dec 2021 12:41:35 -0500 X-UUID: 1fadfb714e45486ba51cf2a6cd11e462-20211211 X-UUID: 1fadfb714e45486ba51cf2a6cd11e462-20211211 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1994580294; Sat, 11 Dec 2021 01:37:55 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 11 Dec 2021 01:37:54 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:54 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 4/6] arm64: dts: mt8195: Add APU nodes Date: Sat, 11 Dec 2021 01:37:41 +0800 Message-ID: <20211210173743.30906-5-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add APU nodes to MT8195. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 4980b8329b54..828ac8a6b95f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1360,6 +1360,21 @@ #clock-cells =3D <1>; }; =20 + apu_conn: syscon@19020000 { + compatible =3D "mediatek,mt8195-apu-conn", "syscon"; + reg =3D <0 0x19020000 0 0x1000>; + }; + + apu_conn1: syscon@19024000 { + compatible =3D "mediatek,mt8195-apu-conn1", "syscon"; + reg =3D <0 0x19024000 0 0x1000>; + }; + + apu_vcore: syscon@19029000 { + compatible =3D "mediatek,mt8195-apu-vcore", "syscon"; + reg =3D <0 0x19029000 0 0x1000>; + }; + apusys_pll: clock-controller@190f3000 { compatible =3D "mediatek,mt8195-apusys_pll"; reg =3D <0 0x190f3000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 11:29:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D35C433F5 for ; Fri, 10 Dec 2021 17:38:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244507AbhLJRlp (ORCPT ); Fri, 10 Dec 2021 12:41:45 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:56128 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S241809AbhLJRlf (ORCPT ); Fri, 10 Dec 2021 12:41:35 -0500 X-UUID: 9952b82b904e4ac3a34e11f688d58810-20211211 X-UUID: 9952b82b904e4ac3a34e11f688d58810-20211211 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1240690002; Sat, 11 Dec 2021 01:37:56 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:55 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , Flora Fu , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 5/6] arm64: dts: mt8195: Add APU power domain node Date: Sat, 11 Dec 2021 01:37:42 +0800 Message-ID: <20211210173743.30906-6-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add APU power domain node to MT8195. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 828ac8a6b95f..6e60c4a38495 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1375,6 +1375,22 @@ reg =3D <0 0x19029000 0 0x1000>; }; =20 + apuspm: power-domain@190f0000 { + compatible =3D "mediatek,mt8195-apu-pm", "syscon"; + reg =3D <0 0x190f0000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + mediatek,scpsys =3D <&scpsys>; + mediatek,apu-conn =3D <&apu_conn>; + mediatek,apu-conn1 =3D <&apu_conn1>; + mediatek,apu-vcore =3D <&apu_vcore>; + apu_top: power-domain@0 { + reg =3D <0>; + #power-domain-cells =3D <0>; + }; + }; + apusys_pll: clock-controller@190f3000 { compatible =3D "mediatek,mt8195-apusys_pll"; reg =3D <0 0x190f3000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 11:29:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45668C433F5 for ; Fri, 10 Dec 2021 17:38:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244643AbhLJRls (ORCPT ); Fri, 10 Dec 2021 12:41:48 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:33678 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S241846AbhLJRlg (ORCPT ); Fri, 10 Dec 2021 12:41:36 -0500 X-UUID: b427bda0126949c08137e9d434dd7c7a-20211211 X-UUID: b427bda0126949c08137e9d434dd7c7a-20211211 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 539543431; Sat, 11 Dec 2021 01:37:57 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:56 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , Flora Fu , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 6/6] arm64: dts: mt8195: Set up apu power domain regulators Date: Sat, 11 Dec 2021 01:37:43 +0800 Message-ID: <20211210173743.30906-7-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set up apu power domain related regulators. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8195-evb.dts index c9f23742cb6f..6333cab7929f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include "mt6359.dtsi" =20 / { model =3D "MediaTek MT8195 evaluation board"; @@ -36,6 +37,13 @@ status =3D "okay"; }; =20 +&apuspm { + vsram-supply =3D <&mt6359_vsram_md_ldo_reg>; + apu_top: power-domain@0 { + domain-supply =3D <&mt6359_vproc1_buck_reg>; + }; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0_pin>; --=20 2.18.0