From nobody Sun Sep 22 13:16:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4889EC433F5 for ; Fri, 10 Dec 2021 17:27:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244500AbhLJRai (ORCPT ); Fri, 10 Dec 2021 12:30:38 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:43080 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S244502AbhLJRaY (ORCPT ); Fri, 10 Dec 2021 12:30:24 -0500 X-UUID: f6184c85e41d4b64b8936494185a5018-20211211 X-UUID: f6184c85e41d4b64b8936494185a5018-20211211 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 26101188; Sat, 11 Dec 2021 01:26:46 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:26:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:26:44 +0800 From: Flora Fu To: Matthias Brugger , Liam Girdwood , Mark Brown , Sumit Semwal , Yong Wu , Pi-Cheng Chen CC: , , , , , , Flora Fu , JB Tsai Subject: [PATCH 07/17] iommu/mediatek: Support APU iommu and config data for mt8192 Date: Sat, 11 Dec 2021 01:25:55 +0800 Message-ID: <20211210172605.30618-8-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210172605.30618-1-flora.fu@mediatek.com> References: <20211210172605.30618-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APU IOMMU is a new iommu HW. it uses a new pagetable. Add support for mt8192 apu iommu. Signed-off-by: Yong Wu Signed-off-by: Flora Fu --- drivers/iommu/mtk_iommu.c | 45 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8377f3c37283..4bc7c76062e6 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -133,6 +133,7 @@ /* 2 bits: iommu type */ #define MTK_IOMMU_TYPE_MM (0x0 << 13) #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) +#define MTK_IOMMU_TYPE_APU (0x2 << 13) #define MTK_IOMMU_TYPE_MASK (0x3 << 13) #define IFA_IOMMU_PCIe_SUPPORT BIT(15) =20 @@ -185,6 +186,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_dat= a *data, unsigned int ban #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL =20 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ +static LIST_HEAD(apulist); /* List the apu iommu HWs */ =20 #define for_each_m4u(data, head) list_for_each_entry(data, head, list) =20 @@ -209,6 +211,13 @@ static const struct mtk_iommu_iova_region mt8192_multi= _dom[] =3D { #endif }; =20 +static const struct mtk_iommu_iova_region mt8192_multi_dom_apu[] =3D { + { .iova_base =3D 0x0, .size =3D SZ_4G}, /* APU DATA */ + { .iova_base =3D 0x4000000ULL, .size =3D 0x4000000}, /* APU VLM */ + { .iova_base =3D 0x10000000ULL, .size =3D 0x10000000}, /* APU VPU */ + { .iova_base =3D 0x70000000ULL, .size =3D 0x12600000}, /* APU REG */ +}; + /* If 2 M4U share a domain(use the same hwlist), Put the corresponding inf= o in first data.*/ static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hw= list) { @@ -638,24 +647,45 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iomm= u_domain *domain, =20 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) { + unsigned int flag =3D DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data; + struct mtk_iommu_data *data, *curdata; + struct device_link *link; =20 if (!fwspec || fwspec->ops !=3D &mtk_iommu_ops) return ERR_PTR(-ENODEV); /* Not a iommu client device */ =20 data =3D dev_iommu_priv_get(dev); =20 + if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_APU)) { + /* + * The APU IOMMU HWs must work together. The consumer device + * must connect with all the apu iommu HWs at the same time. + */ + for_each_m4u(curdata, data->hw_list) { + link =3D device_link_add(dev, curdata->dev, flag); + if (!link) + dev_err(dev, "Unable to link %s\n", dev_name(curdata->dev)); + } + } return &data->iommu; } =20 static void mtk_iommu_release_device(struct device *dev) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct mtk_iommu_data *data; =20 if (!fwspec || fwspec->ops !=3D &mtk_iommu_ops) return; =20 + data =3D dev_iommu_priv_get(dev); + if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_APU)) { + struct list_head *head =3D data->hw_list; + + for_each_m4u(data, head) + device_link_remove(dev, data->dev); + } iommu_fwspec_free(dev); } =20 @@ -1270,6 +1300,18 @@ static const struct mtk_iommu_plat_data mt8192_data = =3D { {0, 14, 16}, {0, 13, 18, 17}}, }; =20 +static const struct mtk_iommu_plat_data mt8192_data_apu =3D { + .m4u_plat =3D M4U_MT8192, + .flags =3D DCM_DISABLE | MTK_IOMMU_TYPE_APU | + SHARE_PGTABLE, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .hw_list =3D &apulist, + .bank_nr =3D 1, + .bank_enable =3D {true}, + .iova_region =3D mt8192_multi_dom_apu, + .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom_apu), +}; + static const struct mtk_iommu_plat_data mt8195_data_infra =3D { .m4u_plat =3D M4U_MT8195, .flags =3D WR_THROT_EN | DCM_DISABLE | @@ -1325,6 +1367,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = =3D { { .compatible =3D "mediatek,mt8173-m4u", .data =3D &mt8173_data}, { .compatible =3D "mediatek,mt8183-m4u", .data =3D &mt8183_data}, { .compatible =3D "mediatek,mt8192-m4u", .data =3D &mt8192_data}, + { .compatible =3D "mediatek,mt8192-iommu-apu", .data =3D &mt8192_data_a= pu}, { .compatible =3D "mediatek,mt8195-iommu-infra", .data =3D &mt8195_data_i= nfra}, { .compatible =3D "mediatek,mt8195-iommu-vdo", .data =3D &mt8195_data_v= do}, { .compatible =3D "mediatek,mt8195-iommu-vpp", .data =3D &mt8195_data_v= pp}, --=20 2.18.0