From nobody Sun Sep 22 13:28:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34615C433FE for ; Fri, 10 Dec 2021 17:01:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244282AbhLJRFT (ORCPT ); Fri, 10 Dec 2021 12:05:19 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:44200 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243175AbhLJRFR (ORCPT ); Fri, 10 Dec 2021 12:05:17 -0500 X-UUID: 39ce057fdca049fc9df23942860072a7-20211211 X-UUID: 39ce057fdca049fc9df23942860072a7-20211211 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 102867124; Sat, 11 Dec 2021 01:01:39 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 11 Dec 2021 01:01:38 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:01:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:01:38 +0800 From: Flora Fu To: Matthias Brugger , Liam Girdwood , Mark Brown CC: , , , Flora Fu , "Yong Wu" , JB Tsai , Pi-Cheng Chen , Chun-Jie Chen Subject: [PATCH v4 2/8] clk: mediatek: mt8192: Add APU clocks support Date: Sat, 11 Dec 2021 01:01:07 +0800 Message-ID: <20211210170113.30063-3-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210170113.30063-1-flora.fu@mediatek.com> References: <20211210170113.30063-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add APU clocks support on MT8192. Signed-off-by: Flora Fu Acked-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8192.c | 91 +++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index cbc7c6dbe0f4..8bc4e85780c6 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -244,6 +244,65 @@ static const char * const ccu_parents[] =3D { "univpll_d6_d2" }; =20 +static const char * const dsp_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp1_parents[] =3D { + "clk26m", + "npupll_ck", + "mainpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3", + "apupll_ck" +}; + +static const char * const dsp1_npupll_parents[] =3D { + "dsp1_sel", + "npupll_ck" +}; + +static const char * const dsp2_parents[] =3D { + "clk26m", + "npupll_ck", + "mainpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3", + "apupll_ck" +}; + +static const char * const dsp2_npupll_parents[] =3D { + "dsp2_sel", + "npupll_ck" +}; + +static const char * const dsp5_parents[] =3D { + "clk26m", + "apupll_ck", + "univpll_d4_d2", + "mainpll_d4", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp5_apupll_parents[] =3D { + "dsp5_sel", + "apupll_ck" +}; + static const char * const dsp7_parents[] =3D { "clk26m", "mainpll_d4_d2", @@ -255,6 +314,17 @@ static const char * const dsp7_parents[] =3D { "mmpll_d4" }; =20 +static const char * const ipu_if_parents[] =3D { + "clk26m", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d4_d2", + "univpll_d5", + "mainpll_d4", + "tvdpll_ck", + "univpll_d4" +}; + static const char * const mfg_ref_parents[] =3D { "clk26m", "clk26m", @@ -734,9 +804,26 @@ static const struct mtk_mux top_mtk_muxes[] =3D { cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", + dsp_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x004, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel", + dsp1_parents, 0x040, 0x044, 0x048, 8, 3, 15, 0x004, 13), + MUX_CLR_SET_UPD(CLK_TOP_DSP1_NPUPLL_SEL, "dsp1_npupll_sel", + dsp1_npupll_parents, 0x040, 0x044, 0x048, 11, 1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel", + dsp2_parents, 0x040, 0x044, 0x048, 16, 3, 23, 0x004, 14), + MUX_CLR_SET_UPD(CLK_TOP_DSP2_NPUPLL_SEL, "dsp2_npupll_sel", + dsp2_npupll_parents, 0x040, 0x044, 0x048, 19, 1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel", + dsp5_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x004, 15), + MUX_CLR_SET_UPD(CLK_TOP_DSP5_APUPLL_SEL, "dsp5_apupll_sel", + dsp5_apupll_parents, 0x040, 0x044, 0x048, 27, 1, -1, -1), /* CLK_CFG_4 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel", + ipu_if_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x004, 17), MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", @@ -1175,6 +1262,10 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), + PLL_B(CLK_APMIXED_APUPLL, "apupll", 0x03a0, 0x03ac, 0xff000001, + HAVE_RST_BAR, BIT(23), 22, 0x03a4, 24, 0, 0, 0, 0x03a4, 0), + PLL_B(CLK_APMIXED_NPUPLL, "npupll", 0x03b4, 0x03c0, 0x00000001, + 0, 0, 22, 0x03b8, 24, 0, 0, 0, 0x03b8, 0), }; =20 static struct clk_onecell_data *top_clk_data; --=20 2.18.0