From nobody Sun Sep 22 13:30:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5623C433F5 for ; Fri, 10 Dec 2021 17:01:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244256AbhLJRFQ (ORCPT ); Fri, 10 Dec 2021 12:05:16 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:49592 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243175AbhLJRFP (ORCPT ); Fri, 10 Dec 2021 12:05:15 -0500 X-UUID: 5addcadb20e44646b36c829221c84d4b-20211211 X-UUID: 5addcadb20e44646b36c829221c84d4b-20211211 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 77089250; Sat, 11 Dec 2021 01:01:37 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 11 Dec 2021 01:01:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:01:36 +0800 From: Flora Fu To: Matthias Brugger , Liam Girdwood , Mark Brown CC: , , , Flora Fu , "Yong Wu" , JB Tsai , Pi-Cheng Chen , Chun-Jie Chen Subject: [PATCH v4 1/8] dt-bindings: clock: Add MT8192 APU clock bindings Date: Sat, 11 Dec 2021 01:01:06 +0800 Message-ID: <20211210170113.30063-2-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210170113.30063-1-flora.fu@mediatek.com> References: <20211210170113.30063-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock bindings for APU on MT8192. Signed-off-by: Flora Fu Acked-by: Rob Herring Acked-by: Stephen Boyd --- include/dt-bindings/clock/mt8192-clk.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/c= lock/mt8192-clk.h index 5ab68f15a256..d5ac7b6c1d5c 100644 --- a/include/dt-bindings/clock/mt8192-clk.h +++ b/include/dt-bindings/clock/mt8192-clk.h @@ -164,7 +164,15 @@ #define CLK_TOP_APLL12_DIV9 152 #define CLK_TOP_SSUSB_TOP_REF 153 #define CLK_TOP_SSUSB_PHY_REF 154 -#define CLK_TOP_NR_CLK 155 +#define CLK_TOP_DSP_SEL 155 +#define CLK_TOP_DSP1_SEL 156 +#define CLK_TOP_DSP1_NPUPLL_SEL 157 +#define CLK_TOP_DSP2_SEL 158 +#define CLK_TOP_DSP2_NPUPLL_SEL 159 +#define CLK_TOP_DSP5_SEL 160 +#define CLK_TOP_DSP5_APUPLL_SEL 161 +#define CLK_TOP_IPU_IF_SEL 162 +#define CLK_TOP_NR_CLK 163 =20 /* INFRACFG */ =20 @@ -309,7 +317,9 @@ #define CLK_APMIXED_APLL1 8 #define CLK_APMIXED_APLL2 9 #define CLK_APMIXED_MIPID26M 10 -#define CLK_APMIXED_NR_CLK 11 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_NPUPLL 12 +#define CLK_APMIXED_NR_CLK 13 =20 /* SCP_ADSP */ =20 --=20 2.18.0