From nobody Sun Sep 22 13:37:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EFC3C433F5 for ; Fri, 3 Dec 2021 06:35:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378719AbhLCGjU (ORCPT ); Fri, 3 Dec 2021 01:39:20 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:57060 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1378629AbhLCGiB (ORCPT ); Fri, 3 Dec 2021 01:38:01 -0500 X-UUID: 8c455eb788584fb1b77b4fbee9cdd2c7-20211203 X-UUID: 8c455eb788584fb1b77b4fbee9cdd2c7-20211203 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1766284034; Fri, 03 Dec 2021 14:34:36 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 3 Dec 2021 14:34:34 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 3 Dec 2021 14:34:33 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH v4 6/7] arm64: dts: mt8195: add ethernet device node Date: Fri, 3 Dec 2021 14:34:17 +0800 Message-ID: <20211203063418.14892-7-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211203063418.14892-1-biao.huang@mediatek.com> References: <20211203063418.14892-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds device node for mt8195 ethernet. Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 92 +++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++ 2 files changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8195-evb.dts index 5cce9a5d3163..d90308f80229 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,8 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include +#include =20 / { model =3D "MediaTek MT8195 evaluation board"; @@ -32,6 +34,96 @@ reserved_memory: reserved-memory { }; }; =20 +ð { + phy-mode =3D"rgmii-rxid"; + phy-handle =3D <ð_phy0>; + snps,reset-gpio =3D <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us =3D <0 10000 10000>; + mediatek,tx-delay-ps =3D <2030>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default>; + pinctrl-1 =3D <ð_sleep>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + eth_phy0: eth_phy0@1 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + }; + }; +}; + +&pio { + eth_default: eth_default { + txd_pins { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + cc_pins { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + rxd_pins { + pinmux =3D , + , + , + ; + }; + mdio_pins { + pinmux =3D , + ; + input-enable; + }; + power_pins { + pinmux =3D , + ; + output-high; + }; + }; + + eth_sleep: eth_sleep { + txd_pins { + pinmux =3D , + , + , + ; + }; + cc_pins { + pinmux =3D , + , + , + ; + }; + rxd_pins { + pinmux =3D , + , + , + ; + }; + mdio_pins { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + power_pins { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + }; +}; + &uart0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index a59c0e9d1fc2..f30a60dca5ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -823,6 +823,76 @@ spis1: spi@1101e000 { status =3D "disabled"; }; =20 + eth: ethernet@11021000 { + compatible =3D "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg =3D <0 0x11021000 0 0x4000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + mac-address =3D [00 55 7b b5 7d f7]; + clock-names =3D "axi", + "apb", + "mac_cg", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clocks =3D <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg =3D <&infracfg_ao>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + clk_csr =3D <0>; + status =3D "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0x7>; + snps,rd_osr_lmt =3D <0x7>; + snps,blen =3D <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,priority =3D <0x0>; + }; + }; + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <3>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x0>; + }; + queue1 { + snps,weight =3D <0x11>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + queue2 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + }; + }; + mmc0: mmc@11230000 { compatible =3D "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; reg =3D <0 0x11230000 0 0x10000>, --=20 2.25.1