From nobody Sun Sep 22 15:28:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66A24C46467 for ; Mon, 29 Nov 2021 03:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377060AbhK2Drm (ORCPT ); Sun, 28 Nov 2021 22:47:42 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:44548 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1349220AbhK2Dpd (ORCPT ); Sun, 28 Nov 2021 22:45:33 -0500 X-UUID: b08153cee0504cf79ed967fe27e43c1c-20211129 X-UUID: b08153cee0504cf79ed967fe27e43c1c-20211129 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 536925466; Mon, 29 Nov 2021 11:42:11 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 29 Nov 2021 11:42:10 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 29 Nov 2021 11:42:09 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 29 Nov 2021 11:42:08 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Dafna Hirschfeld , Benjamin Gaignard , Daniel Vetter , dri-devel , Irui Wang , , , , , , , Subject: [PATCH v11, 04/19] media: mtk-vcodec: export decoder pm functions Date: Mon, 29 Nov 2021 11:41:46 +0800 Message-ID: <20211129034201.5767-5-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211129034201.5767-1-yunfei.dong@mediatek.com> References: <20211129034201.5767-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Register each hardware as platform device, need to call pm functions to open/close power and clock from module mtk-vcodec-dec, export these functions. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/driver= s/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c index 20bd157a855c..221cf60e9fbf 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c @@ -77,12 +77,14 @@ int mtk_vcodec_init_dec_pm(struct platform_device *pdev, put_device(pm->larbvdec); return ret; } +EXPORT_SYMBOL_GPL(mtk_vcodec_init_dec_pm); =20 void mtk_vcodec_release_dec_pm(struct mtk_vcodec_pm *pm) { pm_runtime_disable(pm->dev); put_device(pm->larbvdec); } +EXPORT_SYMBOL_GPL(mtk_vcodec_release_dec_pm); =20 int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) { @@ -94,6 +96,7 @@ int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) =20 return ret; } +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_on); =20 void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm) { @@ -103,6 +106,7 @@ void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm) if (ret) mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); } +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_off); =20 void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) { @@ -129,6 +133,7 @@ void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) for (i -=3D 1; i >=3D 0; i--) clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); } +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_on); =20 void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm) { @@ -139,3 +144,4 @@ void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm) for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); } +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_off); --=20 2.25.1