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charset="utf-8" From: Ajit Kumar Pandey Add IPC module for generic ACP block and exposed ops callback for to synchronize SOF IPC message between host and DSP Signed-off-by: Balakishore Pati Signed-off-by: Ajit Kumar Pandey Reviewed-by: Bard Liao Reviewed-by: Kai Vehmanen Signed-off-by: Daniel Baluta --- sound/soc/sof/amd/Makefile | 2 +- sound/soc/sof/amd/acp-dsp-offset.h | 2 + sound/soc/sof/amd/acp-ipc.c | 187 +++++++++++++++++++++++++++++ sound/soc/sof/amd/acp.c | 44 ++++++- sound/soc/sof/amd/acp.h | 15 +++ sound/soc/sof/amd/renoir.c | 8 ++ 6 files changed, 256 insertions(+), 2 deletions(-) create mode 100644 sound/soc/sof/amd/acp-ipc.c diff --git a/sound/soc/sof/amd/Makefile b/sound/soc/sof/amd/Makefile index 031fb9493876..29928b16002f 100644 --- a/sound/soc/sof/amd/Makefile +++ b/sound/soc/sof/amd/Makefile @@ -4,7 +4,7 @@ # # Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. =20 -snd-sof-amd-acp-objs :=3D acp.o acp-loader.o +snd-sof-amd-acp-objs :=3D acp.o acp-loader.o acp-ipc.o snd-sof-amd-renoir-objs :=3D renoir.o =20 obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) +=3D snd-sof-amd-acp.o diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp= -offset.h index f4bc7e9abafb..3a1c848020ca 100644 --- a/sound/soc/sof/amd/acp-dsp-offset.h +++ b/sound/soc/sof/amd/acp-dsp-offset.h @@ -53,6 +53,8 @@ =20 /* Registers from ACP_INTR block */ #define ACP_DSP_SW_INTR_CNTL 0x1814 +#define ACP_DSP_SW_INTR_STAT 0x1818 +#define ACP_SW_INTR_TRIG 0x181C #define ACP_ERROR_STATUS 0x18C4 =20 /* Registers from ACP_SHA block */ diff --git a/sound/soc/sof/amd/acp-ipc.c b/sound/soc/sof/amd/acp-ipc.c new file mode 100644 index 000000000000..e132223b4c66 --- /dev/null +++ b/sound/soc/sof/amd/acp-ipc.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +// +// This file is provided under a dual BSD/GPLv2 license. When using or +// redistributing this file, you may do so under either license. +// +// Copyright(c) 2021 Advanced Micro Devices, Inc. +// +// Authors: Balakishore Pati +// Ajit Kumar Pandey + +/* ACP-specific SOF IPC code */ + +#include +#include "../ops.h" +#include "acp.h" +#include "acp-dsp-offset.h" + +void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message= , size_t bytes) +{ + memcpy_to_scratch(sdev, offset, message, bytes); +} +EXPORT_SYMBOL_NS(acp_mailbox_write, SND_SOC_SOF_AMD_COMMON); + +void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message,= size_t bytes) +{ + memcpy_from_scratch(sdev, offset, message, bytes); +} +EXPORT_SYMBOL_NS(acp_mailbox_read, SND_SOC_SOF_AMD_COMMON); + +static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata) +{ + struct snd_sof_dev *sdev =3D adata->dev; + u32 swintr_trigger; + + swintr_trigger =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW_INTR_TRIG); + swintr_trigger |=3D 0x01; + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW_INTR_TRIG, swintr_trigger); +} + +static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev) +{ + unsigned int host_msg =3D offsetof(struct scratch_ipc_conf, sof_host_msg_= write); + + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1); +} + +static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev) +{ + unsigned int dsp_msg =3D offsetof(struct scratch_ipc_conf, sof_dsp_msg_wr= ite); + + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0); +} + +static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev) +{ + unsigned int dsp_ack =3D offsetof(struct scratch_ipc_conf, sof_dsp_ack_wr= ite); + + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0); +} + +int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg = *msg) +{ + struct acp_dev_data *adata =3D sdev->pdata->hw_pdata; + unsigned int offset =3D offsetof(struct scratch_ipc_conf, sof_in_box); + + acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size); + acp_ipc_host_msg_set(sdev); + + /* Trigger host to dsp interrupt for the msg */ + acpbus_trigger_host_to_dsp_swintr(adata); + return 0; +} +EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, SND_SOC_SOF_AMD_COMMON); + +static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev) +{ + struct snd_sof_ipc_msg *msg =3D sdev->msg; + struct sof_ipc_reply reply; + struct sof_ipc_cmd_hdr *hdr; + unsigned int offset =3D offsetof(struct scratch_ipc_conf, sof_in_box); + int ret =3D 0; + + /* + * Sometimes, there is unexpected reply ipc arriving. The reply + * ipc belongs to none of the ipcs sent from driver. + * In this case, the driver must ignore the ipc. + */ + if (!msg) { + dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); + return; + } + hdr =3D msg->msg_data; + if (hdr->cmd =3D=3D (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) || + hdr->cmd =3D=3D (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) { + /* + * memory windows are powered off before sending IPC reply, + * so we can't read the mailbox for CTX_SAVE and PM_GATE + * replies. + */ + reply.error =3D 0; + reply.hdr.cmd =3D SOF_IPC_GLB_REPLY; + reply.hdr.size =3D sizeof(reply); + memcpy(msg->reply_data, &reply, sizeof(reply)); + goto out; + } + /* get IPC reply from DSP in the mailbox */ + acp_mailbox_read(sdev, offset, &reply, sizeof(reply)); + if (reply.error < 0) { + memcpy(msg->reply_data, &reply, sizeof(reply)); + ret =3D reply.error; + } else { + /* reply correct size ? */ + if (reply.hdr.size !=3D msg->reply_size && + !(reply.hdr.cmd & SOF_IPC_GLB_PROBE)) { + dev_err(sdev->dev, "reply expected %zu got %u bytes\n", + msg->reply_size, reply.hdr.size); + ret =3D -EINVAL; + } + /* read the message */ + if (msg->reply_size > 0) + acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size); + } +out: + msg->reply_error =3D ret; +} + +irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context) +{ + struct snd_sof_dev *sdev =3D context; + unsigned int dsp_msg_write =3D offsetof(struct scratch_ipc_conf, sof_dsp_= msg_write); + unsigned int dsp_ack_write =3D offsetof(struct scratch_ipc_conf, sof_dsp_= ack_write); + bool ipc_irq =3D false; + int dsp_msg, dsp_ack; + + dsp_msg =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_m= sg_write); + if (dsp_msg) { + snd_sof_ipc_msgs_rx(sdev); + acp_dsp_ipc_host_done(sdev); + ipc_irq =3D true; + } + + dsp_ack =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_a= ck_write); + if (dsp_ack) { + spin_lock_irq(&sdev->ipc_lock); + /* handle immediate reply from DSP core */ + acp_dsp_ipc_get_reply(sdev); + snd_sof_ipc_reply(sdev, 0); + /* set the done bit */ + acp_dsp_ipc_dsp_done(sdev); + spin_unlock_irq(&sdev->ipc_lock); + ipc_irq =3D true; + } + + if (!ipc_irq) + dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_NS(acp_sof_ipc_irq_thread, SND_SOC_SOF_AMD_COMMON); + +int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substrea= m *substream, + void *p, size_t sz) +{ + unsigned int offset =3D offsetof(struct scratch_ipc_conf, sof_out_box); + + if (!substream || !sdev->stream_box.size) + acp_mailbox_read(sdev, offset, p, sz); + + return 0; +} +EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, SND_SOC_SOF_AMD_COMMON); + +int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substr= eam *substream, + const struct sof_ipc_pcm_params_reply *reply) +{ + /* TODO: Implement stream hw params to validate stream offset */ + return 0; +} +EXPORT_SYMBOL_NS(acp_sof_ipc_pcm_params, SND_SOC_SOF_AMD_COMMON); + +int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) +{ + return ACP_SCRATCH_MEMORY_ADDRESS; +} +EXPORT_SYMBOL_NS(acp_sof_ipc_get_mailbox_offset, SND_SOC_SOF_AMD_COMMON); + +MODULE_DESCRIPTION("AMD ACP sof-ipc driver"); diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 3778f781f16a..43a57d15e3ca 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -233,6 +233,34 @@ static int acp_memory_init(struct snd_sof_dev *sdev) return 0; } =20 +static irqreturn_t acp_irq_thread(int irq, void *context) +{ + struct snd_sof_dev *sdev =3D context; + unsigned int val; + + val =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT); + if (val & ACP_DSP_TO_HOST_IRQ) { + sof_ops(sdev)->irq_thread(irq, sdev); + val |=3D ACP_DSP_TO_HOST_IRQ; + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT, val); + return IRQ_HANDLED; + } + + return IRQ_NONE; +}; + +static irqreturn_t acp_irq_handler(int irq, void *dev_id) +{ + struct snd_sof_dev *sdev =3D dev_id; + unsigned int val; + + val =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT); + if (val) + return IRQ_WAKE_THREAD; + + return IRQ_NONE; +} + static int acp_power_on(struct snd_sof_dev *sdev) { unsigned int val; @@ -318,9 +346,20 @@ int amd_sof_acp_probe(struct snd_sof_dev *sdev) =20 sdev->pdata->hw_pdata =3D adata; =20 + sdev->ipc_irq =3D pci->irq; + ret =3D request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thre= ad, + IRQF_SHARED, "AudioDSP", sdev); + if (ret < 0) { + dev_err(sdev->dev, "failed to register IRQ %d\n", + sdev->ipc_irq); + return ret; + } + ret =3D acp_init(sdev); - if (ret < 0) + if (ret < 0) { + free_irq(sdev->ipc_irq, sdev); return ret; + } =20 acp_memory_init(sdev); =20 @@ -330,6 +369,9 @@ EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COM= MON); =20 int amd_sof_acp_remove(struct snd_sof_dev *sdev) { + if (sdev->ipc_irq) + free_irq(sdev->ipc_irq, sdev); + return acp_reset(sdev); } EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON); diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index e755a31374c6..ac8340119125 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -48,6 +48,8 @@ #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 #define ACP_DRAM_PAGE_COUNT 128 =20 +#define ACP_DSP_TO_HOST_IRQ 0x04 + struct acp_atu_grp_pte { u32 low; u32 high; @@ -150,5 +152,18 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum= snd_sof_fw_blk_type blk_t int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type = blk_type, u32 offset, void *dest, size_t size); =20 +/* IPC callbacks */ +irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); +int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substrea= m *substream, + void *p, size_t sz); +int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, + struct snd_sof_ipc_msg *msg); +int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); +int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); +int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substr= eam *substream, + const struct sof_ipc_pcm_params_reply *reply); +void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message= , size_t bytes); +void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message,= size_t bytes); + extern const struct snd_sof_dsp_ops sof_renoir_ops; #endif diff --git a/sound/soc/sof/amd/renoir.c b/sound/soc/sof/amd/renoir.c index bca80784b322..9d95ea66f867 100644 --- a/sound/soc/sof/amd/renoir.c +++ b/sound/soc/sof/amd/renoir.c @@ -41,6 +41,14 @@ const struct snd_sof_dsp_ops sof_renoir_ops =3D { =20 /* DSP core boot */ .run =3D acp_sof_dsp_run, + + /*IPC */ + .send_msg =3D acp_sof_ipc_send_msg, + .ipc_msg_data =3D acp_sof_ipc_msg_data, + .ipc_pcm_params =3D acp_sof_ipc_pcm_params, + .get_mailbox_offset =3D acp_sof_ipc_get_mailbox_offset, + .irq_thread =3D acp_sof_ipc_irq_thread, + .fw_ready =3D sof_fw_ready, }; EXPORT_SYMBOL(sof_renoir_ops); =20 --=20 2.27.0