From nobody Sun Sep 22 15:25:55 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D4E4C4332F for ; Fri, 12 Nov 2021 10:57:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2830E60F39 for ; Fri, 12 Nov 2021 10:57:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234960AbhKLK75 (ORCPT ); Fri, 12 Nov 2021 05:59:57 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:42250 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234948AbhKLK7w (ORCPT ); Fri, 12 Nov 2021 05:59:52 -0500 X-UUID: 6a4aab7e9f6f46ff9c7fa6a55942109c-20211112 X-UUID: 6a4aab7e9f6f46ff9c7fa6a55942109c-20211112 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 816629391; Fri, 12 Nov 2021 18:56:57 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 12 Nov 2021 18:56:56 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 12 Nov 2021 18:56:54 +0800 From: Yong Wu To: Matthias Brugger , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , David Airlie , "Mauro Carvalho Chehab" CC: Evan Green , Robin Murphy , Tomasz Figa , Will Deacon , , , , , , , , , Matthias Kaehlcke , , , , , , Daniel Vetter , Chun-Kuang Hu , Philipp Zabel , Tiffany Lin , "Dafna Hirschfeld" , Hsin-Yi Wang , Eizan Miyamoto , , Frank Wunderlich , , , , Yongqiang Niu , CK Hu Subject: [PATCH v9 08/15] drm/mediatek: Add pm runtime support for ovl and rdma Date: Fri, 12 Nov 2021 18:55:02 +0800 Message-ID: <20211112105509.12010-9-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211112105509.12010-1-yong.wu@mediatek.com> References: <20211112105509.12010-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongqiang Niu Prepare for smi cleaning up "mediatek,larb". Display use the dispsys device to call pm_rumtime_get_sync before. This patch add pm_runtime_xx with ovl and rdma device whose nodes has "iommus" property, then display could help pm_runtime_get for smi via ovl or rdma device. CC: CK Hu Signed-off-by: Yongqiang Niu Signed-off-by: Yong Wu (Yong: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync) Acked-by: Chun-Kuang Hu Tested-by: Frank Wunderlich # BPI-R2/MT7623 --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 +++++++- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 9 ++++++++- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 13 ++++++++++++- 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 5326989d5206..716eac6831f2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #include "mtk_disp_drv.h" @@ -414,9 +415,13 @@ static int mtk_disp_ovl_probe(struct platform_device *= pdev) return ret; } =20 + pm_runtime_enable(dev); + ret =3D component_add(dev, &mtk_disp_ovl_component_ops); - if (ret) + if (ret) { + pm_runtime_disable(dev); dev_err(dev, "Failed to add component: %d\n", ret); + } =20 return ret; } @@ -424,6 +429,7 @@ static int mtk_disp_ovl_probe(struct platform_device *p= dev) static int mtk_disp_ovl_remove(struct platform_device *pdev) { component_del(&pdev->dev, &mtk_disp_ovl_component_ops); + pm_runtime_disable(&pdev->dev); =20 return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/med= iatek/mtk_disp_rdma.c index 75d7f45579e2..251f034acb09 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "mtk_disp_drv.h" @@ -327,9 +328,13 @@ static int mtk_disp_rdma_probe(struct platform_device = *pdev) =20 platform_set_drvdata(pdev, priv); =20 + pm_runtime_enable(dev); + ret =3D component_add(dev, &mtk_disp_rdma_component_ops); - if (ret) + if (ret) { + pm_runtime_disable(dev); dev_err(dev, "Failed to add component: %d\n", ret); + } =20 return ret; } @@ -338,6 +343,8 @@ static int mtk_disp_rdma_remove(struct platform_device = *pdev) { component_del(&pdev->dev, &mtk_disp_rdma_component_ops); =20 + pm_runtime_disable(&pdev->dev); + return 0; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index 5f81489fc60c..455ea23c6130 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -649,9 +649,17 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc= *crtc, return; } =20 + ret =3D pm_runtime_resume_and_get(comp->dev); + if (ret < 0) { + mtk_smi_larb_put(comp->larb_dev); + DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); + return; + } + ret =3D mtk_crtc_ddp_hw_init(mtk_crtc); if (ret) { mtk_smi_larb_put(comp->larb_dev); + pm_runtime_put(comp->dev); return; } =20 @@ -664,7 +672,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc= *crtc, { struct mtk_drm_crtc *mtk_crtc =3D to_mtk_crtc(crtc); struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; - int i; + int i, ret; =20 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); if (!mtk_crtc->enabled) @@ -688,6 +696,9 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc= *crtc, drm_crtc_vblank_off(crtc); mtk_crtc_ddp_hw_fini(mtk_crtc); mtk_smi_larb_put(comp->larb_dev); + ret =3D pm_runtime_put(comp->dev); + if (ret < 0) + DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); =20 mtk_crtc->enabled =3D false; } --=20 2.18.0