From nobody Sun Sep 22 15:31:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4E1BC433EF for ; Wed, 3 Nov 2021 08:10:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCFD8610E5 for ; Wed, 3 Nov 2021 08:10:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232004AbhKCINN (ORCPT ); Wed, 3 Nov 2021 04:13:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:41292 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231393AbhKCING (ORCPT ); Wed, 3 Nov 2021 04:13:06 -0400 X-UUID: 41549cc9da484f8bbe409b2c2d4047b7-20211103 X-UUID: 41549cc9da484f8bbe409b2c2d4047b7-20211103 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2129851890; Wed, 03 Nov 2021 16:10:24 +0800 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 3 Nov 2021 16:10:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs10n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 3 Nov 2021 16:10:23 +0800 From: James Lo To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , James Lo , , , , , , Subject: [RESEND, v13 3/4] spmi: mediatek: Add support for MT6873/8192 Date: Wed, 3 Nov 2021 16:10:20 +0800 Message-ID: <20211103081021.9917-4-james.lo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211103081021.9917-1-james.lo@mediatek.com> References: <20211103081021.9917-1-james.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add spmi support for MT6873/8192. Signed-off-by: Hsin-Hsiung Wang Acked-By: AngeloGioacchino Del Regno --- drivers/spmi/Kconfig | 11 + drivers/spmi/Makefile | 1 + drivers/spmi/spmi-mtk-pmif.c | 454 +++++++++++++++++++++++++++++++++++ 3 files changed, 466 insertions(+) create mode 100644 drivers/spmi/spmi-mtk-pmif.c diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index 2874b6c26028..737802046314 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -34,4 +34,15 @@ config SPMI_MSM_PMIC_ARB This is required for communicating with Qualcomm PMICs and other devices that have the SPMI interface. =20 +config SPMI_MTK_PMIF + tristate "Mediatek SPMI Controller (PMIC Arbiter)" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + If you say yes to this option, support will be included for the + built-in SPMI PMIC Arbiter interface on Mediatek family + processors. + + This is required for communicating with Mediatek PMICs and + other devices that have the SPMI interface. + endif diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile index 6e092e6f290c..9d974424c8c1 100644 --- a/drivers/spmi/Makefile +++ b/drivers/spmi/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SPMI) +=3D spmi.o =20 obj-$(CONFIG_SPMI_HISI3670) +=3D hisi-spmi-controller.o obj-$(CONFIG_SPMI_MSM_PMIC_ARB) +=3D spmi-pmic-arb.o +obj-$(CONFIG_SPMI_MTK_PMIF) +=3D spmi-mtk-pmif.o diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c new file mode 100644 index 000000000000..3283d0a5903c --- /dev/null +++ b/drivers/spmi/spmi-mtk-pmif.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2021 MediaTek Inc. + +#include +#include +#include +#include +#include +#include +#include + +#define SWINF_IDLE 0x00 +#define SWINF_WFVLDCLR 0x06 + +#define GET_SWINF(x) (((x) >> 1) & 0x7) + +#define PMIF_CMD_REG_0 0 +#define PMIF_CMD_REG 1 +#define PMIF_CMD_EXT_REG 2 +#define PMIF_CMD_EXT_REG_LONG 3 + +#define PMIF_DELAY_US 10 +#define PMIF_TIMEOUT_US (10 * 1000) + +#define PMIF_CHAN_OFFSET 0x5 + +#define PMIF_MAX_CLKS 3 + +#define SPMI_OP_ST_BUSY 1 + +struct ch_reg { + u32 ch_sta; + u32 wdata; + u32 rdata; + u32 ch_send; + u32 ch_rdy; +}; + +struct pmif_data { + const u32 *regs; + const u32 *spmimst_regs; + u32 soc_chan; +}; + +struct pmif { + void __iomem *base; + void __iomem *spmimst_base; + struct ch_reg chan; + struct clk_bulk_data clks[PMIF_MAX_CLKS]; + size_t nclks; + const struct pmif_data *data; +}; + +static const char * const pmif_clock_names[] =3D { + "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux", +}; + +enum pmif_regs { + PMIF_INIT_DONE, + PMIF_INF_EN, + PMIF_ARB_EN, + PMIF_CMDISSUE_EN, + PMIF_TIMER_CTRL, + PMIF_SPI_MODE_CTRL, + PMIF_IRQ_EVENT_EN_0, + PMIF_IRQ_FLAG_0, + PMIF_IRQ_CLR_0, + PMIF_IRQ_EVENT_EN_1, + PMIF_IRQ_FLAG_1, + PMIF_IRQ_CLR_1, + PMIF_IRQ_EVENT_EN_2, + PMIF_IRQ_FLAG_2, + PMIF_IRQ_CLR_2, + PMIF_IRQ_EVENT_EN_3, + PMIF_IRQ_FLAG_3, + PMIF_IRQ_CLR_3, + PMIF_IRQ_EVENT_EN_4, + PMIF_IRQ_FLAG_4, + PMIF_IRQ_CLR_4, + PMIF_WDT_EVENT_EN_0, + PMIF_WDT_FLAG_0, + PMIF_WDT_EVENT_EN_1, + PMIF_WDT_FLAG_1, + PMIF_SWINF_0_STA, + PMIF_SWINF_0_WDATA_31_0, + PMIF_SWINF_0_RDATA_31_0, + PMIF_SWINF_0_ACC, + PMIF_SWINF_0_VLD_CLR, + PMIF_SWINF_1_STA, + PMIF_SWINF_1_WDATA_31_0, + PMIF_SWINF_1_RDATA_31_0, + PMIF_SWINF_1_ACC, + PMIF_SWINF_1_VLD_CLR, + PMIF_SWINF_2_STA, + PMIF_SWINF_2_WDATA_31_0, + PMIF_SWINF_2_RDATA_31_0, + PMIF_SWINF_2_ACC, + PMIF_SWINF_2_VLD_CLR, + PMIF_SWINF_3_STA, + PMIF_SWINF_3_WDATA_31_0, + PMIF_SWINF_3_RDATA_31_0, + PMIF_SWINF_3_ACC, + PMIF_SWINF_3_VLD_CLR, +}; + +static const u32 mt6873_regs[] =3D { + [PMIF_INIT_DONE] =3D 0x0000, + [PMIF_INF_EN] =3D 0x0024, + [PMIF_ARB_EN] =3D 0x0150, + [PMIF_CMDISSUE_EN] =3D 0x03B4, + [PMIF_TIMER_CTRL] =3D 0x03E0, + [PMIF_SPI_MODE_CTRL] =3D 0x0400, + [PMIF_IRQ_EVENT_EN_0] =3D 0x0418, + [PMIF_IRQ_FLAG_0] =3D 0x0420, + [PMIF_IRQ_CLR_0] =3D 0x0424, + [PMIF_IRQ_EVENT_EN_1] =3D 0x0428, + [PMIF_IRQ_FLAG_1] =3D 0x0430, + [PMIF_IRQ_CLR_1] =3D 0x0434, + [PMIF_IRQ_EVENT_EN_2] =3D 0x0438, + [PMIF_IRQ_FLAG_2] =3D 0x0440, + [PMIF_IRQ_CLR_2] =3D 0x0444, + [PMIF_IRQ_EVENT_EN_3] =3D 0x0448, + [PMIF_IRQ_FLAG_3] =3D 0x0450, + [PMIF_IRQ_CLR_3] =3D 0x0454, + [PMIF_IRQ_EVENT_EN_4] =3D 0x0458, + [PMIF_IRQ_FLAG_4] =3D 0x0460, + [PMIF_IRQ_CLR_4] =3D 0x0464, + [PMIF_WDT_EVENT_EN_0] =3D 0x046C, + [PMIF_WDT_FLAG_0] =3D 0x0470, + [PMIF_WDT_EVENT_EN_1] =3D 0x0474, + [PMIF_WDT_FLAG_1] =3D 0x0478, + [PMIF_SWINF_0_ACC] =3D 0x0C00, + [PMIF_SWINF_0_WDATA_31_0] =3D 0x0C04, + [PMIF_SWINF_0_RDATA_31_0] =3D 0x0C14, + [PMIF_SWINF_0_VLD_CLR] =3D 0x0C24, + [PMIF_SWINF_0_STA] =3D 0x0C28, + [PMIF_SWINF_1_ACC] =3D 0x0C40, + [PMIF_SWINF_1_WDATA_31_0] =3D 0x0C44, + [PMIF_SWINF_1_RDATA_31_0] =3D 0x0C54, + [PMIF_SWINF_1_VLD_CLR] =3D 0x0C64, + [PMIF_SWINF_1_STA] =3D 0x0C68, + [PMIF_SWINF_2_ACC] =3D 0x0C80, + [PMIF_SWINF_2_WDATA_31_0] =3D 0x0C84, + [PMIF_SWINF_2_RDATA_31_0] =3D 0x0C94, + [PMIF_SWINF_2_VLD_CLR] =3D 0x0CA4, + [PMIF_SWINF_2_STA] =3D 0x0CA8, + [PMIF_SWINF_3_ACC] =3D 0x0CC0, + [PMIF_SWINF_3_WDATA_31_0] =3D 0x0CC4, + [PMIF_SWINF_3_RDATA_31_0] =3D 0x0CD4, + [PMIF_SWINF_3_VLD_CLR] =3D 0x0CE4, + [PMIF_SWINF_3_STA] =3D 0x0CE8, +}; + +enum spmi_regs { + SPMI_OP_ST_CTRL, + SPMI_GRP_ID_EN, + SPMI_OP_ST_STA, + SPMI_MST_SAMPL, + SPMI_MST_REQ_EN, + SPMI_REC_CTRL, + SPMI_REC0, + SPMI_REC1, + SPMI_REC2, + SPMI_REC3, + SPMI_REC4, + SPMI_MST_DBG, +}; + +static const u32 mt6873_spmi_regs[] =3D { + [SPMI_OP_ST_CTRL] =3D 0x0000, + [SPMI_GRP_ID_EN] =3D 0x0004, + [SPMI_OP_ST_STA] =3D 0x0008, + [SPMI_MST_SAMPL] =3D 0x000c, + [SPMI_MST_REQ_EN] =3D 0x0010, + [SPMI_REC_CTRL] =3D 0x0040, + [SPMI_REC0] =3D 0x0044, + [SPMI_REC1] =3D 0x0048, + [SPMI_REC2] =3D 0x004c, + [SPMI_REC3] =3D 0x0050, + [SPMI_REC4] =3D 0x0054, + [SPMI_MST_DBG] =3D 0x00fc, +}; + +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg) +{ + return readl(arb->base + arb->data->regs[reg]); +} + +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg) +{ + writel(val, arb->base + arb->data->regs[reg]); +} + +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg) +{ + writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]); +} + +static bool pmif_is_fsm_vldclr(struct pmif *arb) +{ + u32 reg_rdata; + + reg_rdata =3D pmif_readl(arb, arb->chan.ch_sta); + + return GET_SWINF(reg_rdata) =3D=3D SWINF_WFVLDCLR; +} + +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) +{ + struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + u32 rdata, cmd; + int ret; + + /* Check the opcode */ + if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) + return -EINVAL; + + cmd =3D opc - SPMI_CMD_RESET; + + mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); + ret =3D readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_= regs[SPMI_OP_ST_STA], + rdata, (rdata & SPMI_OP_ST_BUSY) =3D=3D SPMI_OP_ST_BUSY, + PMIF_DELAY_US, PMIF_TIMEOUT_US); + if (ret < 0) + dev_err(&ctrl->dev, "timeout, err =3D %d\n", ret); + + return ret; +} + +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, + u16 addr, u8 *buf, size_t len) +{ + struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + struct ch_reg *inf_reg; + int ret; + u32 data, cmd; + + /* Check for argument validation. */ + if (sid & ~0xf) { + dev_err(&ctrl->dev, "exceed the max slv id\n"); + return -EINVAL; + } + + if (len > 4) { + dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu request= ed", len); + + return -EINVAL; + } + + if (opc >=3D 0x60 && opc <=3D 0x7f) + opc =3D PMIF_CMD_REG; + else if ((opc >=3D 0x20 && opc <=3D 0x2f) || (opc >=3D 0x38 && opc <=3D 0= x3f)) + opc =3D PMIF_CMD_EXT_REG_LONG; + else + return -EINVAL; + + /* Wait for Software Interface FSM state to be IDLE. */ + inf_reg =3D &arb->chan; + ret =3D readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch= _sta], + data, GET_SWINF(data) =3D=3D SWINF_IDLE, + PMIF_DELAY_US, PMIF_TIMEOUT_US); + if (ret < 0) { + /* set channel ready if the data has transferred */ + if (pmif_is_fsm_vldclr(arb)) + pmif_writel(arb, 1, inf_reg->ch_rdy); + dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); + return ret; + } + + /* Send the command. */ + cmd =3D (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; + pmif_writel(arb, cmd, inf_reg->ch_send); + + /* + * Wait for Software Interface FSM state to be WFVLDCLR, + * read the data and clear the valid flag. + */ + ret =3D readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch= _sta], + data, GET_SWINF(data) =3D=3D SWINF_WFVLDCLR, + PMIF_DELAY_US, PMIF_TIMEOUT_US); + if (ret < 0) { + dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n"); + return ret; + } + + data =3D pmif_readl(arb, inf_reg->rdata); + memcpy(buf, &data, len); + pmif_writel(arb, 1, inf_reg->ch_rdy); + + return 0; +} + +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 si= d, + u16 addr, const u8 *buf, size_t len) +{ + struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + struct ch_reg *inf_reg; + int ret; + u32 data, cmd; + + if (len > 4) { + dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu request= ed", len); + + return -EINVAL; + } + + /* Check the opcode */ + if (opc >=3D 0x40 && opc <=3D 0x5F) + opc =3D PMIF_CMD_REG; + else if ((opc <=3D 0xF) || (opc >=3D 0x30 && opc <=3D 0x37)) + opc =3D PMIF_CMD_EXT_REG_LONG; + else if (opc >=3D 0x80) + opc =3D PMIF_CMD_REG_0; + else + return -EINVAL; + + /* Wait for Software Interface FSM state to be IDLE. */ + inf_reg =3D &arb->chan; + ret =3D readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch= _sta], + data, GET_SWINF(data) =3D=3D SWINF_IDLE, + PMIF_DELAY_US, PMIF_TIMEOUT_US); + if (ret < 0) { + /* set channel ready if the data has transferred */ + if (pmif_is_fsm_vldclr(arb)) + pmif_writel(arb, 1, inf_reg->ch_rdy); + dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); + return ret; + } + + /* Set the write data. */ + memcpy(&data, buf, len); + pmif_writel(arb, data, inf_reg->wdata); + + /* Send the command. */ + cmd =3D (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr; + pmif_writel(arb, cmd, inf_reg->ch_send); + + return 0; +} + +static const struct pmif_data mt6873_pmif_arb =3D { + .regs =3D mt6873_regs, + .spmimst_regs =3D mt6873_spmi_regs, + .soc_chan =3D 2, +}; + +static int mtk_spmi_probe(struct platform_device *pdev) +{ + struct pmif *arb; + struct spmi_controller *ctrl; + int err, i; + u32 chan_offset; + + ctrl =3D spmi_controller_alloc(&pdev->dev, sizeof(*arb)); + if (!ctrl) + return -ENOMEM; + + arb =3D spmi_controller_get_drvdata(ctrl); + arb->data =3D device_get_match_data(&pdev->dev); + if (!arb->data) { + err =3D -EINVAL; + dev_err(&pdev->dev, "Cannot get drv_data\n"); + goto err_put_ctrl; + } + + arb->base =3D devm_platform_ioremap_resource_byname(pdev, "pmif"); + if (IS_ERR(arb->base)) { + err =3D PTR_ERR(arb->base); + goto err_put_ctrl; + } + + arb->spmimst_base =3D devm_platform_ioremap_resource_byname(pdev, "spmims= t"); + if (IS_ERR(arb->spmimst_base)) { + err =3D PTR_ERR(arb->spmimst_base); + goto err_put_ctrl; + } + + arb->nclks =3D ARRAY_SIZE(pmif_clock_names); + for (i =3D 0; i < arb->nclks; i++) + arb->clks[i].id =3D pmif_clock_names[i]; + + err =3D devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks); + if (err) { + dev_err(&pdev->dev, "Failed to get clocks: %d\n", err); + goto err_put_ctrl; + } + + err =3D clk_bulk_prepare_enable(arb->nclks, arb->clks); + if (err) { + dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err); + goto err_put_ctrl; + } + + ctrl->cmd =3D pmif_arb_cmd; + ctrl->read_cmd =3D pmif_spmi_read_cmd; + ctrl->write_cmd =3D pmif_spmi_write_cmd; + + chan_offset =3D PMIF_CHAN_OFFSET * arb->data->soc_chan; + arb->chan.ch_sta =3D PMIF_SWINF_0_STA + chan_offset; + arb->chan.wdata =3D PMIF_SWINF_0_WDATA_31_0 + chan_offset; + arb->chan.rdata =3D PMIF_SWINF_0_RDATA_31_0 + chan_offset; + arb->chan.ch_send =3D PMIF_SWINF_0_ACC + chan_offset; + arb->chan.ch_rdy =3D PMIF_SWINF_0_VLD_CLR + chan_offset; + + platform_set_drvdata(pdev, ctrl); + + err =3D spmi_controller_add(ctrl); + if (err) + goto err_domain_remove; + + return 0; + +err_domain_remove: + clk_bulk_disable_unprepare(arb->nclks, arb->clks); +err_put_ctrl: + spmi_controller_put(ctrl); + return err; +} + +static int mtk_spmi_remove(struct platform_device *pdev) +{ + struct spmi_controller *ctrl =3D platform_get_drvdata(pdev); + struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + + clk_bulk_disable_unprepare(arb->nclks, arb->clks); + spmi_controller_remove(ctrl); + spmi_controller_put(ctrl); + return 0; +} + +static const struct of_device_id mtk_spmi_match_table[] =3D { + { + .compatible =3D "mediatek,mt6873-spmi", + .data =3D &mt6873_pmif_arb, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, mtk_spmi_match_table); + +static struct platform_driver mtk_spmi_driver =3D { + .driver =3D { + .name =3D "spmi-mtk", + .of_match_table =3D of_match_ptr(mtk_spmi_match_table), + }, + .probe =3D mtk_spmi_probe, + .remove =3D mtk_spmi_remove, +}; +module_platform_driver(mtk_spmi_driver); + +MODULE_AUTHOR("Hsin-Hsiung Wang "); +MODULE_DESCRIPTION("MediaTek SPMI Driver"); +MODULE_LICENSE("GPL"); --=20 2.18.0