From nobody Sun Sep 22 13:23:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62898C433FE for ; Tue, 2 Nov 2021 09:02:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3975E60E05 for ; Tue, 2 Nov 2021 09:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbhKBJFM (ORCPT ); Tue, 2 Nov 2021 05:05:12 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:55682 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229881AbhKBJFK (ORCPT ); Tue, 2 Nov 2021 05:05:10 -0400 X-UUID: ba0947763eba4ab8b4368587899f201f-20211102 X-UUID: ba0947763eba4ab8b4368587899f201f-20211102 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1219803053; Tue, 02 Nov 2021 17:02:33 +0800 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 2 Nov 2021 17:02:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs10n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 2 Nov 2021 17:02:32 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: , , , , , Seiya Wang Subject: [RESEND v2] arm64: dts: mt8183: support coresight-cpu-debug for mt8183 Date: Tue, 2 Nov 2021 17:02:30 +0800 Message-ID: <20211102090230.25013-1-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add coresight-cpu-debug nodes to mt8183 for dumping EDPRSR, EDPCSR, EDCIDSR, EDVIDSR while kernel panic happens Signed-off-by: Seiya Wang --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 64 ++++++++++++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 409cf827970c..2d36575e7dbe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -367,6 +367,70 @@ reg =3D <0 0x0c530a80 0 0x50>; }; =20 + cpu_debug0: cpu-debug@d410000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xd410000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu0>; + }; + + cpu_debug1: cpu-debug@d510000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xd510000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu1>; + }; + + cpu_debug2: cpu-debug@d610000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xd610000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu2>; + }; + + cpu_debug3: cpu-debug@d710000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xd710000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu3>; + }; + + cpu_debug4: cpu-debug@d810000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xd810000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu4>; + }; + + cpu_debug5: cpu-debug@d910000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xd910000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu5>; + }; + + cpu_debug6: cpu-debug@da10000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xda10000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu6>; + }; + + cpu_debug7: cpu-debug@db10000 { + compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; + reg =3D <0x0 0xdb10000 0x0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu7>; + }; + topckgen: syscon@10000000 { compatible =3D "mediatek,mt8183-topckgen", "syscon"; reg =3D <0 0x10000000 0 0x1000>; --=20 2.14.1