From nobody Sun Sep 22 13:35:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E24E4C433F5 for ; Tue, 2 Nov 2021 07:21:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7D4360E08 for ; Tue, 2 Nov 2021 07:21:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231511AbhKBHXz (ORCPT ); Tue, 2 Nov 2021 03:23:55 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33144 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230281AbhKBHXw (ORCPT ); Tue, 2 Nov 2021 03:23:52 -0400 X-UUID: 397eba2c52f54dc6b87da86c99d13c6a-20211102 X-UUID: 397eba2c52f54dc6b87da86c99d13c6a-20211102 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1200185247; Tue, 02 Nov 2021 15:21:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 2 Nov 2021 15:21:14 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Nov 2021 15:21:14 +0800 From: Chunfeng Yun To: Matthias Brugger , Chun-Jie Chen CC: , , , Chunfeng Yun Subject: [RFC PATCH] soc: mediatek: Add support always on flag Date: Tue, 2 Nov 2021 15:20:58 +0800 Message-ID: <20211102072058.4107-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is a t-phy shared by PCIe and USB3 on mt8195, if the t-phy is used by PCIe, when power off its mtcmos, need software reset it (workaround way, usually hardware do it, but has an issue on mt8195), but it has side effect to USB2 phy(works with USB3 phy to support USB3.2 Gen1), so add support GENPD_FLAG_ALWAYS_ON flag, and make its power always on; Another reason is that USB3.2 Gen1/2 need keep power always on when support runtime-pm due to hardware limitation until now; Signed-off-by: Chunfeng Yun --- drivers/soc/mediatek/mt8195-pm-domains.h | 2 +- drivers/soc/mediatek/mtk-pm-domains.c | 2 ++ drivers/soc/mediatek/mtk-pm-domains.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediate= k/mt8195-pm-domains.h index 1379aa39bf16..b6949874c72b 100644 --- a/drivers/soc/mediatek/mt8195-pm-domains.h +++ b/drivers/soc/mediatek/mt8195-pm-domains.h @@ -67,7 +67,7 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8195[] =3D { .ctl_offs =3D 0x334, .pwr_sta_offs =3D 0x174, .pwr_sta2nd_offs =3D 0x178, - .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + .caps =3D MTK_SCPD_ALWAYS_ON, }, [MT8195_POWER_DOMAIN_CSI_RX_TOP] =3D { .name =3D "csi_rx_top", diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 61973a306e97..b89e5e3e3363 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -446,6 +446,8 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys = *scpsys, struct device_no =20 if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP)) pd->genpd.flags |=3D GENPD_FLAG_ACTIVE_WAKEUP; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_ALWAYS_ON)) + pd->genpd.flags |=3D GENPD_FLAG_ALWAYS_ON; =20 if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) pm_genpd_init(&pd->genpd, NULL, true); diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index daa24e890dd4..419d23d5e394 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -8,6 +8,7 @@ #define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) +#define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.25.1