From nobody Sun Sep 22 15:35:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5179C433F5 for ; Sat, 23 Oct 2021 11:15:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF63260FDC for ; Sat, 23 Oct 2021 11:15:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231602AbhJWLRk (ORCPT ); Sat, 23 Oct 2021 07:17:40 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33766 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231133AbhJWLRR (ORCPT ); Sat, 23 Oct 2021 07:17:17 -0400 X-UUID: c7d218ca346b4c98a51ea5139655d1d5-20211023 X-UUID: c7d218ca346b4c98a51ea5139655d1d5-20211023 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 973666721; Sat, 23 Oct 2021 19:14:54 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Sat, 23 Oct 2021 19:14:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 23 Oct 2021 19:14:52 +0800 From: Flora Fu To: Matthias Brugger , Mark Brown , Sumit Semwal CC: , , , , , , Flora Fu , Yong Wu , Pi-Cheng Chen Subject: [RFC 04/13] iommu/mediatek: Add APU iommu support Date: Sat, 23 Oct 2021 19:14:00 +0800 Message-ID: <20211023111409.30463-5-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211023111409.30463-1-flora.fu@mediatek.com> References: <20211023111409.30463-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APU IOMMU is a new iommu HW. it use a new pagetable. Add support for mt8192 apu iommu. Signed-off-by: Yong Wu Signed-off-by: Flora Fu --- drivers/iommu/mtk_iommu.c | 57 +++++++++++++++++++ include/dt-bindings/memory/mt8192-larb-port.h | 4 ++ 2 files changed, 61 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 90be8ebbc98a..a5f8f19e053a 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -133,6 +133,7 @@ /* 2 bits: iommu type */ #define MTK_IOMMU_TYPE_MM (0x0 << 13) #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) +#define MTK_IOMMU_TYPE_APU (0x2 << 13) #define MTK_IOMMU_TYPE_MASK (0x3 << 13) #define IFA_IOMMU_PCIe_SUPPORT BIT(15) =20 @@ -185,6 +186,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_dat= a *data, unsigned int ban #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL =20 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ +static LIST_HEAD(apulist); /* List the apu iommu HWs */ =20 #define for_each_m4u(data, head) list_for_each_entry(data, head, list) =20 @@ -209,6 +211,13 @@ static const struct mtk_iommu_iova_region mt8192_multi= _dom[] =3D { #endif }; =20 +static const struct mtk_iommu_iova_region mt8192_multi_dom_apu[] =3D { + { .iova_base =3D 0x0, .size =3D SZ_4G}, /* APU DATA */ + { .iova_base =3D 0x4000000ULL, .size =3D 0x4000000}, /* APU VLM */ + { .iova_base =3D 0x10000000ULL, .size =3D 0x10000000}, /* APU VPU */ + { .iova_base =3D 0x70000000ULL, .size =3D 0x12600000}, /* APU REG */ +}; + /* If 2 M4U share a domain(use the same hwlist), Put the corresponding inf= o in first data.*/ static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hw= list) { @@ -923,6 +932,37 @@ static int mtk_iommu_mm_dts_parse(struct device *dev, return 0; } =20 +static int mtk_iommu_apu_prepare(struct device *dev) +{ + struct device_node *apupower_node; + struct platform_device *apudev; + struct device_link *link; + + apupower_node =3D of_find_compatible_node(NULL, NULL, "mediatek,apusys-po= wer"); + if (!apupower_node) { + dev_warn(dev, "Can't find apu power node!\n"); + return -EINVAL; + } + + if (!of_device_is_available(apupower_node)) { + of_node_put(apupower_node); + return -EPERM; + } + + apudev =3D of_find_device_by_node(apupower_node); + if (!apudev) { + of_node_put(apupower_node); + return -EPROBE_DEFER; + } + + link =3D device_link_add(&apudev->dev, dev, DL_FLAG_PM_RUNTIME); + if (!link) + dev_err(dev, "Unable link %s.\n", apudev->name); + + of_node_put(apupower_node); + return 0; +} + static int mtk_iommu_probe(struct platform_device *pdev) { struct mtk_iommu_data *data; @@ -1021,6 +1061,10 @@ static int mtk_iommu_probe(struct platform_device *p= dev) } =20 data->pericfg =3D infracfg; + } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_APU)) { + ret =3D mtk_iommu_apu_prepare(dev); + if (ret) + goto out_runtime_disable; } =20 platform_set_drvdata(pdev, data); @@ -1268,6 +1312,18 @@ static const struct mtk_iommu_plat_data mt8192_data = =3D { {0, 14, 16}, {0, 13, 18, 17}}, }; =20 +static const struct mtk_iommu_plat_data mt8192_data_apu =3D { + .m4u_plat =3D M4U_MT8192, + .flags =3D WR_THROT_EN | DCM_DISABLE | MTK_IOMMU_TYPE_APU | + SHARE_PGTABLE, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .hw_list =3D &apulist, + .bank_nr =3D 1, + .bank_enable =3D {true}, + .iova_region =3D mt8192_multi_dom_apu, + .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom_apu), +}; + static const struct mtk_iommu_plat_data mt8195_data_infra =3D { .m4u_plat =3D M4U_MT8195, .flags =3D WR_THROT_EN | DCM_DISABLE | @@ -1323,6 +1379,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = =3D { { .compatible =3D "mediatek,mt8173-m4u", .data =3D &mt8173_data}, { .compatible =3D "mediatek,mt8183-m4u", .data =3D &mt8183_data}, { .compatible =3D "mediatek,mt8192-m4u", .data =3D &mt8192_data}, + { .compatible =3D "mediatek,mt8192-iommu-apu", .data =3D &mt8192_data_a= pu}, { .compatible =3D "mediatek,mt8195-iommu-infra", .data =3D &mt8195_data_i= nfra}, { .compatible =3D "mediatek,mt8195-iommu-vdo", .data =3D &mt8195_data_v= do}, { .compatible =3D "mediatek,mt8195-iommu-vpp", .data =3D &mt8195_data_v= pp}, diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bin= dings/memory/mt8192-larb-port.h index 23035a52c675..908d6831bf99 100644 --- a/include/dt-bindings/memory/mt8192-larb-port.h +++ b/include/dt-bindings/memory/mt8192-larb-port.h @@ -240,4 +240,8 @@ #define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) #define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) =20 +#define IOMMU_PORT_APU_DATA MTK_M4U_ID(0, 0) +#define IOMMU_PORT_APU_VLM MTK_M4U_ID(0, 1) +#define IOMMU_PORT_APU_VPU MTK_M4U_ID(0, 2) + #endif --=20 2.18.0