From nobody Sun Sep 22 15:27:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2F7DC433F5 for ; Sat, 23 Oct 2021 11:15:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B238E60FC3 for ; Sat, 23 Oct 2021 11:15:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231406AbhJWLRU (ORCPT ); Sat, 23 Oct 2021 07:17:20 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:39196 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230496AbhJWLRM (ORCPT ); Sat, 23 Oct 2021 07:17:12 -0400 X-UUID: 3880fae249eb49d98bf7b6952f17da58-20211023 X-UUID: 3880fae249eb49d98bf7b6952f17da58-20211023 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1350239767; Sat, 23 Oct 2021 19:14:51 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Sat, 23 Oct 2021 19:14:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 23 Oct 2021 19:14:50 +0800 From: Flora Fu To: Matthias Brugger , Mark Brown , Sumit Semwal CC: , , , , , , Flora Fu , Yong Wu , Pi-Cheng Chen Subject: [RFC 02/13] dt-bindings: soc: mediatek: apusys: Add new document for APU power Date: Sat, 23 Oct 2021 19:13:58 +0800 Message-ID: <20211023111409.30463-3-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211023111409.30463-1-flora.fu@mediatek.com> References: <20211023111409.30463-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add new document for APU power controller. Signed-off-by: Flora Fu --- .../soc/mediatek/mediatek,apu-pwr.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek= ,apu-pwr.yaml diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pw= r.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.ya= ml new file mode 100644 index 000000000000..0fd5af5138e3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# # Copyright 2021 MediaTek Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pwr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek APU Power + +description: | + Mediatek AI Process Unit (APU) power driver support for subsys clock and + regulator controller. It will has device link to iommu-apu and apusys-rv + tinysys driver to ensure the power state is ready for hardware + in sub modules. + +maintainers: + - Flora Fu + +properties: + compatible: + oneOf: + - const: mediatek,apusys-power + - items: + - const: mediatek,apusys-power + - const: mediatek,mt8192-apu-power + + reg: + minItems: 1 + + reg-names: + minItems: 1 + + power-domains: + maxItems: 1 + + vvpu-supply: + description: apu vpu regulator supply. + + vmdla-supply: + description: apu mdla regulator supply. + + clocks: + description: Contains module clock source and clock names + + clock-names: + description: Names of the clocks list in clocks property + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vvpu-supply + - vmdla-supply + +additionalProperties: false + +examples: + - | + #include + apusys_power: apusys_power@190f1000 { + compatible =3D "mediatek,apusys-power", + "mediatek,mt8192-apu-power"; + reg =3D <0x190f1000 0x1000>; + reg-names =3D "apu_pcu"; + power-domains =3D <&apuspm 0>; + vvpu-supply =3D <&mt6359_vproc1_buck_reg>; + vmdla-supply =3D <&mt6359_vproc2_buck_reg>; + clocks =3D <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP1_SEL>, + <&topckgen CLK_TOP_DSP1_NPUPLL_SEL>, + <&topckgen CLK_TOP_DSP2_SEL>, + <&topckgen CLK_TOP_DSP2_NPUPLL_SEL>, + <&topckgen CLK_TOP_DSP5_SEL>, + <&topckgen CLK_TOP_DSP5_APUPLL_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>, + <&clk26m>; + clock-names =3D "clk_top_dsp_sel", + "clk_top_dsp1_sel", + "clk_top_dsp1_npupll_sel", + "clk_top_dsp2_sel", + "clk_top_dsp2_npupll_sel", + "clk_top_dsp5_sel", + "clk_top_dsp5_apupll_sel", + "clk_top_ipu_if_sel", + "clk_top_clk26m"; + }; --=20 2.18.0