From nobody Sun Sep 22 15:21:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 878D8C433F5 for ; Sat, 23 Oct 2021 11:15:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 703E260E97 for ; Sat, 23 Oct 2021 11:15:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231604AbhJWLSN (ORCPT ); Sat, 23 Oct 2021 07:18:13 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:39320 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231408AbhJWLRW (ORCPT ); Sat, 23 Oct 2021 07:17:22 -0400 X-UUID: 4a3e196170eb448a87f51f8f0e46d445-20211023 X-UUID: 4a3e196170eb448a87f51f8f0e46d445-20211023 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1865629089; Sat, 23 Oct 2021 19:15:01 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 23 Oct 2021 19:15:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 23 Oct 2021 19:15:00 +0800 From: Flora Fu To: Matthias Brugger , Mark Brown , Sumit Semwal CC: , , , , , , Flora Fu , Yong Wu , Pi-Cheng Chen Subject: [RFC 11/13] arm64: dts: mt8192: Add apu power nodes Date: Sat, 23 Oct 2021 19:14:07 +0800 Message-ID: <20211023111409.30463-12-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211023111409.30463-1-flora.fu@mediatek.com> References: <20211023111409.30463-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add apu power node. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index d5e417a512a7..c505c6926839 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -964,6 +964,68 @@ }; }; =20 + apusys_power: apusys_power@190f1000 { + compatible =3D "mediatek,apusys-power", + "mediatek,mt8192-apu-power"; + reg =3D <0 0x190f1000 0 0x1000>, + <0 0x19000600 0 0x100>; + reg-names =3D "apu_pcu", + "apu_spare"; + power-domains =3D <&apuspm 0>; + clocks =3D <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP1_SEL>, + <&topckgen CLK_TOP_DSP1_NPUPLL_SEL>, + <&topckgen CLK_TOP_DSP2_SEL>, + <&topckgen CLK_TOP_DSP2_NPUPLL_SEL>, + <&topckgen CLK_TOP_DSP5_SEL>, + <&topckgen CLK_TOP_DSP5_APUPLL_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_MAINPLL_D4_D2>, + <&topckgen CLK_TOP_UNIVPLL_D4_D2>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_MMPLL_D6>, + <&topckgen CLK_TOP_MMPLL_D5>, + <&topckgen CLK_TOP_MMPLL_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5>, + <&topckgen CLK_TOP_UNIVPLL_D4>, + <&topckgen CLK_TOP_UNIVPLL_D3>, + <&topckgen CLK_TOP_MAINPLL_D6>, + <&topckgen CLK_TOP_MAINPLL_D4>, + <&topckgen CLK_TOP_MAINPLL_D3>, + <&topckgen CLK_TOP_TVDPLL>, + <&topckgen CLK_TOP_APUPLL>, + <&topckgen CLK_TOP_NPUPLL>, + <&apmixedsys CLK_APMIXED_APUPLL>, + <&apmixedsys CLK_APMIXED_NPUPLL>; + clock-names =3D "clk_top_dsp_sel", + "clk_top_dsp1_sel", + "clk_top_dsp1_npupll_sel", + "clk_top_dsp2_sel", + "clk_top_dsp2_npupll_sel", + "clk_top_dsp5_sel", + "clk_top_dsp5_apupll_sel", + "clk_top_ipu_if_sel", + "clk_top_clk26m", + "clk_top_mainpll_d4_d2", + "clk_top_univpll_d4_d2", + "clk_top_univpll_d6_d2", + "clk_top_mmpll_d6", + "clk_top_mmpll_d5", + "clk_top_mmpll_d4", + "clk_top_univpll_d5", + "clk_top_univpll_d4", + "clk_top_univpll_d3", + "clk_top_mainpll_d6", + "clk_top_mainpll_d4", + "clk_top_mainpll_d3", + "clk_top_tvdpll_ck", + "clk_top_apupll_ck", + "clk_top_npupll_ck", + "clk_apmixed_apupll_rate", + "clk_apmixed_npupll_rate"; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8192-camsys"; reg =3D <0 0x1a000000 0 0x1000>; --=20 2.18.0