From nobody Sun Sep 22 15:38:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC55CC433EF for ; Sat, 23 Oct 2021 10:14:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9FE460FD9 for ; Sat, 23 Oct 2021 10:14:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231869AbhJWKQ5 (ORCPT ); Sat, 23 Oct 2021 06:16:57 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:54184 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231481AbhJWKQn (ORCPT ); Sat, 23 Oct 2021 06:16:43 -0400 X-UUID: cca729225b1b40ec8599b7f4ff97d00d-20211023 X-UUID: cca729225b1b40ec8599b7f4ff97d00d-20211023 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1718320597; Sat, 23 Oct 2021 18:14:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 23 Oct 2021 18:14:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 23 Oct 2021 18:14:20 +0800 From: Flora Fu To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd CC: Liam Girdwood , Mark Brown , Flora Fu , Ikjoon Jang , Chun-Jie Chen , , , , , Subject: [PATCH v3 7/7] arm64: dts: mt8192: Add APU power domain node Date: Sat, 23 Oct 2021 18:13:34 +0800 Message-ID: <20211023101334.27686-8-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211023101334.27686-1-flora.fu@mediatek.com> References: <20211023101334.27686-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add APU power domain node to MT8192. Signed-off-by: Flora Fu --- Note: This patch depends on mt8192/mt6359 dts patches which haven't yet been acce= pted. This series is based on MT8192 clock[1][2] and MT8193/PMIC[3][4] patches. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=3D5216= 55 [2] https://patchwork.kernel.org/patch/12134935 [3] https://patchwork.kernel.org/patch/12140237 --- arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 ++++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 27 +++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8192-evb.dts index 808be492e970..5d9e108e41f5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -28,3 +28,10 @@ &uart0 { status =3D "okay"; }; + +&apuspm { + vsram-supply =3D <&mt6359_vsram_md_ldo_reg>; + apu_top: power-domain@0 { + domain-supply =3D <&mt6359_vproc1_buck_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 72bbc3b4abf9..7014082637b0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -928,6 +928,33 @@ #clock-cells =3D <1>; }; =20 + apuspm: power-domain@190f0000 { + compatible =3D "mediatek,mt8192-apu-pm", "syscon"; + reg =3D <0 0x190f0000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + mediatek,scpsys =3D <&scpsys>; + mediatek,apu-conn =3D <&apu_conn>; + mediatek,apu-vcore =3D <&apu_vcore>; + apu_top: power-domain@0 { + reg =3D <0>; + #power-domain-cells =3D <0>; + clocks =3D <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + clock-names =3D "clk_top_conn", + "clk_top_ipu_if", + "clk_off", + "clk_on_default"; + assigned-clocks =3D <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + }; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8192-camsys"; reg =3D <0 0x1a000000 0 0x1000>; --=20 2.18.0