From nobody Tue Dec 16 08:51:45 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33A5E30BB85 for ; Mon, 15 Dec 2025 14:42:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765809725; cv=none; b=JwtTxEzSV4WxfjQ1yOHusGDVkUSigBPp4B3hWx0a52/ExU3ehBSFVqWYDdWhvCgr2ho7sJhmL4YV6T00rtbyHc2PhAm15T1XZ0eyp5Q5Q6L5kvmxvbuvFGF5pYEUn0ca4gyt1QR3eAt5FQm1G5vFELfNnj2Y93wFKw9lM1ovONE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765809725; c=relaxed/simple; bh=cob0Tfyv5UDCeaXp27/pjebA60syehUznwOe1AVD2+8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CSGzX+KsOd+GKYBB6+lCQuTKMrF5tEQvbzptQN1rkT4IgU+lNeqGt2g7ODsSdgFiJY+h7zwKBv+sGAeAVfZ79B+JCh5WEMmXDkzkHNTa7ROYOuCWKCIxi4AfoUK5oYwx8hpSpMIxq0TxgDF59B0hQnsTdgz5bgCzCPvOxXaylBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WqE8Zvk0; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WqE8Zvk0" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4779adb38d3so27246775e9.2 for ; Mon, 15 Dec 2025 06:42:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1765809722; x=1766414522; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=Sjq9hqGMLWVJCvNIjz/5gdBLkm3Fm6/e56WlsVHAzOE=; b=WqE8Zvk0BmQIomj4HKAh9M9kmcmPB7Z7NkxV6M1Iv7Tj4Hnw5HyOMrEgT+S7HJ3Iht 5JqWNhQZZWVFZlwDXSs0xTtG1/6DlBvho1Vo3F0h+GMJbP6ah0tSN9afqa9B/WJCVadk HzmJPDvIZ+GWKunrAEd8k5Ehoetdu1FP2vPylOUB8vjFCIrnF55TM+9Vo0C9JIjNlysX rbo8liVXpn7IYKusvBVIOUelfEi7AL7ActTbW5PUhAHkvjFtx9TEsI9nLXHRaS68Ny9F I0hLnh21FeaBc5FwqWnrGnbfKJsiKrnUp4tl9LapKQXdjKiQFexYhsIToysJDkSIJGrc LruA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765809722; x=1766414522; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sjq9hqGMLWVJCvNIjz/5gdBLkm3Fm6/e56WlsVHAzOE=; b=aISUVXet0Y3zqKpI3+eX433HWqoalw++UxBk3GOLD0XJ65iuVjKB0iH3KB5u7Ui3U0 cJT1wM7ivl5yLSZhnZ5t7LRmDE3Oyq3EZ/tHs8usgKWczM9zW7GQRyUaJhxdm6R/0OJ+ rThZTY2VsktQwBqdpMmGidect+DfuhxoUgOX8+9tMbgx3g5cMQ2QHkt+brSJyjk4TMka nsIgo+G+FtlEOpLGPJs7mpvsHD/aiLWzKRa7eDPajLL+AvAvaZzI1SNe4lXwkDorgal6 0RaOLqOnIKHcNhCo6TKI5pnxofQjvu6wSu2bnW+V5gClaILSbsEDy5GwZRAeeVytflaF q/Bw== X-Forwarded-Encrypted: i=1; AJvYcCVwvVirQJZ6mFnasaxe1TpVifEMbWcusOyIChUerG+byz57GejO9dPnmEFodK1KhLJAVtYUyPaNnjf+WXY=@vger.kernel.org X-Gm-Message-State: AOJu0YxMpStTno9ryOT/uNM4MiqLHIgkP7oiNS127CM73hP3+emC5PgE OHfRgOa5GCM4JILANrxQBloE10dMgSaYcWwRNpvyxSmMupEelXJak4xdI2gu7IA3mTU= X-Gm-Gg: AY/fxX7YhESEHhWo7pfo6dB6Ij5VKhUkDTe8lFe6d2qUhmxgGRCZzAQzJSocgR/6Ehy VFlxW55yPXJ7+tlSqeHh5+46E4BLJi0KT+sRbX0g0/MZ2wviDFciHewm/uVOruoUxtBlgM35wNt gQFU+CKgsjJnnGklFUqQ2StqwhT1Cjly5N8oxBcHm6Y0mO7a1xOUe4qhlQZZBx+G2Hjw7v/p1n1 k2S9QnnMbofYzSg/lvIQeVVKWRP/2WQ48o2EJkWT5Yj4sLGVKuzDAW7dVXqn+Ash14GFnvFooqp X9766TvGfLjeQla19/gzMainEANX/U4mSqPWYoqMCeMAf+hISmVRllT4AhnawgEHc2zO9Bg2C0T 5LkEad47U6JJMIO2kJ4V7kX9VHUFp4KQqrI/fMupyu3IB3gdStICQFcNEl6s8RMZVhhSp1qlYK2 NkP3sUHdtCXauvNwJ6 X-Google-Smtp-Source: AGHT+IEETRagjZzldJ2K5KE+XtO7ZZwocvLnhZyjVLVzDdY/uQUKFKQkatHg2aZmOJSsMWrpNNBzSA== X-Received: by 2002:a05:600c:8286:b0:477:7ab8:aba with SMTP id 5b1f17b1804b1-47a8f8ab861mr112263225e9.1.1765809721474; Mon, 15 Dec 2025 06:42:01 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fb7118267sm22168335f8f.27.2025.12.15.06.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 06:42:00 -0800 (PST) Date: Mon, 15 Dec 2025 17:41:57 +0300 From: Dan Carpenter To: Jan Petrous Cc: s32@nxp.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linaro-s32@linaro.org Subject: [PATCH v2 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Message-ID: <1ecafee4bd7dc3577adfc4ada8bcc50b5eb3e863.1765806521.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The S32 chipsets have a GPR region which has a miscellaneous registers including the GMAC_0_CTRL_STS register. Originally, this code accessed that register in a sort of ad-hoc way, but it's cleaner to use a syscon interface to access these registers. We still need to maintain the old method of accessing the GMAC register but using a syscon will let us access other registers more cleanly. Signed-off-by: Dan Carpenter --- v2: Add the vendor prefix to the phandle Fix the documentation .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..a65036806d60 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -32,6 +32,15 @@ properties: - description: Main GMAC registers - description: GMAC PHY mode control register =20 + nxp,phy-sel: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to the GPR syscon node + - description: offset of PHY selection register + description: + This is a phandle/offset pair. The phandle points to the + GPR region and the offset is the GMAC_0_CTRL_STS register. + interrupts: maxItems: 1 =20 @@ -74,6 +83,7 @@ examples: compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0