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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF000044A3.mail.protection.outlook.com (10.167.243.154) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8722.18 via Frontend Transport; Thu, 15 May 2025 22:56:40 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 15 May 2025 17:56:37 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v13 27/27] x86/resctrl: Configure mbm_cntr_assign mode if supported Date: Thu, 15 May 2025 17:52:12 -0500 Message-ID: <1e9785e00fe55987f8585aef8cbdedbc58e2b1ee.1747349530.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A3:EE_|SA0PR12MB4368:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ccd0999-9095-49d3-9e59-08dd9403c13b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2025 22:56:40.3773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ccd0999-9095-49d3-9e59-08dd9403c13b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4368 Content-Type: text/plain; charset="utf-8" Configure mbm_cntr_assign mode on AMD platforms. On AMD platforms, it is recommended to use the mbm_cntr_assign mode, if supported, to prevent the hardware from resetting counters between reads. This can result in misleading values or display "Unavailable" if no counter is assigned to the event. The mbm_cntr_assign mode, referred to as ABMC (Assignable Bandwidth Monitoring Counters) on AMD, is enabled by default when supported by the system. Update ABMC across all logical processors within the resctrl domain to ensure proper functionality. Signed-off-by: Babu Moger --- v13 : Added the call resctrl_init_evt_configuration() to setup the event configuration during init. Resolved conflicts caused by the recent FS/ARCH code restructure. v12: Moved the resctrl_arch_mbm_cntr_assign_set_one to domain_add_cpu_mon(). Updated the commit log. v11: Commit text in imperative tone. Added few more details. Moved resctrl_arch_mbm_cntr_assign_set_one() to monitor.c. v10: Commit text in imperative tone. v9: Minor code change due to merge. Actual code did not change. v8: Renamed resctrl_arch_mbm_cntr_assign_configure to resctrl_arch_mbm_cntr_assign_set_one. Adde r->mon_capable check. Commit message update. v7: Introduced resctrl_arch_mbm_cntr_assign_configure() to configure. Moved the default settings to rdt_get_mon_l3_config(). It should be done before the hotplug handler is called. It cannot be done at rdtgroup_init(). v6: Keeping the default enablement in arch init code for now. This may need some discussion. Renamed resctrl_arch_configure_abmc to resctrl_arch_mbm_cntr_assign_co= nfigure. v5: New patch to enable ABMC by default. --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/monitor.c | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 6859566398d6..b59f5db96016 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -514,6 +514,9 @@ static void domain_add_cpu_mon(int cpu, struct rdt_reso= urce *r) d =3D container_of(hdr, struct rdt_mon_domain, hdr); =20 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); + /* Update the mbm_cntr_assign state for the CPU if supported */ + if (r->mon.mbm_cntr_assignable) + resctrl_arch_mbm_cntr_assign_set_one(r); return; } =20 @@ -532,6 +535,10 @@ static void domain_add_cpu_mon(int cpu, struct rdt_res= ource *r) } cpumask_set_cpu(cpu, &d->hdr.cpu_mask); =20 + /* Update the mbm_cntr_assign state for the CPU if supported */ + if (r->mon.mbm_cntr_assignable) + resctrl_arch_mbm_cntr_assign_set_one(r); + arch_mon_domain_online(r, d); =20 if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 3b0cdb5520c7..85ebf60a9f1c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -214,5 +214,6 @@ bool rdt_cpu_has(int flag); void __init intel_rdt_mbm_apply_quirk(void); =20 void rdt_domain_reconfigure_cdp(struct rdt_resource *r); +void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r); =20 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index c3e15f4de0b4..51a99b8e69d6 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -436,6 +436,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); r->mon.num_mbm_cntrs =3D (ebx & GENMASK(15, 0)) + 1; r->mon.mbm_assign_on_mkdir =3D true; + hw_res->mbm_cntr_assign_enabled =3D true; } =20 r->mon_capable =3D true; @@ -536,3 +537,10 @@ void resctrl_arch_config_cntr(struct rdt_resource *r, = struct rdt_mon_domain *d, memset(am, 0, sizeof(*am)); } } + +void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + resctrl_abmc_set_one_amd(&hw_res->mbm_cntr_assign_enabled); +} --=20 2.34.1