From nobody Mon Feb 9 13:24:19 2026 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 510B1425CE1 for ; Wed, 4 Feb 2026 19:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770232831; cv=none; b=IjLIiur1opNvESiueigL5aokpiwqZkCMObOvSld8fKCh6EMyDbq+oExlouTDalPdxn7GNV4mhGARHiWlPlCp2/HslnEcGAJF0KIoWR9DV+ZzHlc0naXEok2XwhuKrgonjWU0jbOzETaIP22YK4BfQJ89WvuXrU2eVYREMU/JGx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770232831; c=relaxed/simple; bh=e9TE9ZQy3xE50kGfoLKXb2J0MEw5AJwJ43xpoWbweT0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SCGPSGDoPfw2gEwRrNgdm9lSQu3xyLv6YyVyDW6k7GUQ4xI4D0k4S5AR3330oGOcRmQfSkz/iHRuaUqHP/mslV2krfPYTtnecFzhCXj+Eny7KIZjBJ+uAFyNQZ7Pr7SeYXEkWHBsZKAg8qprVGIJSkLb6+UZwhSIAoGSzXBdLtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=VAo0oAea; arc=none smtp.client-ip=109.224.244.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="VAo0oAea" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1770232829; x=1770492029; bh=/R1s/Veow2jkB86S2q3s5Z9tnoPR8/0Qn8qKyeboaUI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=VAo0oAeaNt5OQmnEI1IMLwDehMy8QAWRF3Ze1P1vHBnGLlUP51EJBAGeqwFggZnhz +GcIWU/ARQIWnQ/zSylKDNoiHHt4SNh5rj/0yDqrSeaoY8GYXQShcvrAjl2mIFNGJo wTpiD/r90YzxsU8+9vUAMRYYLyKr7M9W1mLdF7RC9A3jDMkp9V4b+DE92rwW9i4MfL NkR/lGV/ZZEh/LMq+OAuf5ryVsBlDWMsqjsYP3jJ/dOdcPKBUGyeEbSEZU3QSoTp6w krXWDl+Epv24b6sRgdo/nfhzxVGdEOLQ6q5qmtrXot/8PSqH7sas17a0r0PnxtPyzY S1YxNmhT1z/Ww== Date: Wed, 04 Feb 2026 19:20:23 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , Alexander Potapenko , linux-kernel@vger.kernel.org Subject: [PATCH v10 10/13] x86/mm: Initialize LAM_SUP Message-ID: <1e266ddf1bf0b187028110e871078baa77cd3583.1770232424.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 3fe04149d10c740d0fc4ffac157e781e3612088b Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman To make use of KASAN's tag based mode on x86, Linear Address Masking (LAM) needs to be enabled. To do that the 28th bit in CR4 has to be set. Set the bit in early memory initialization. When launching secondary CPUs the LAM bit gets lost. To avoid this add it in a mask in head_64.S. The bitmask permits some bits of CR4 to pass from the primary CPU to the secondary CPUs without being cleared. Signed-off-by: Maciej Wieczor-Retman Acked-by: Alexander Potapenko --- Changelog v9: - Rename patch title so it fits the tip standards. Changelog v7: - Add Alexander's acked-by tag. Changelog v6: - boot_cpu_has() -> cpu_feature_enabled() arch/x86/kernel/head_64.S | 3 +++ arch/x86/mm/init.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 21816b48537c..c5a0bfbe280d 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -209,6 +209,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) * there will be no global TLB entries after the execution." */ movl $(X86_CR4_PAE | X86_CR4_LA57), %edx +#ifdef CONFIG_ADDRESS_MASKING + orl $X86_CR4_LAM_SUP, %edx +#endif #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 8bf6ad4b9400..a8442b255481 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -764,6 +764,9 @@ void __init init_mem_mapping(void) probe_page_size_mask(); setup_pcid(); =20 + if (cpu_feature_enabled(X86_FEATURE_LAM) && IS_ENABLED(CONFIG_KASAN_SW_TA= GS)) + cr4_set_bits_and_update_boot(X86_CR4_LAM_SUP); + #ifdef CONFIG_X86_64 end =3D max_pfn << PAGE_SHIFT; #else --=20 2.53.0