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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v7 3/8] net: stmmac: Refactor FPE functions to generic version Date: Thu, 31 Oct 2024 20:37:57 +0800 Message-Id: <1c05e448a12057b909cc6c7cc0c9645cf393d181.1730376866.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FPE implementation for DWMAC4 and DWXGMAC differs only for: 1) Offset address of MAC_FPE_CTRL_STS and MTL_FPE_CTRL_STS 2) FPRQ(Frame Preemption Residue Queue) field in MAC_RxQ_Ctrl1 3) Bit offset of Frame Preemption Interrupt Enable Refactor FPE functions to avoid code duplication and to simplify the code flow by avoiding the use of function pointers. Signed-off-by: Furong Xu <0x1207@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 1 - .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 10 -- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 +- .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 2 - drivers/net/ethernet/stmicro/stmmac/hwif.c | 7 + drivers/net/ethernet/stmicro/stmmac/hwif.h | 20 +-- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + .../ethernet/stmicro/stmmac/stmmac_ethtool.c | 4 +- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 155 +++++++++--------- .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 26 +-- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 8 +- 11 files changed, 101 insertions(+), 135 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac4.h index 28fff6cab812..0c050324997a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -69,7 +69,6 @@ #define GMAC_RXQCTRL_TACPQE BIT(21) #define GMAC_RXQCTRL_TACPQE_SHIFT 21 #define GMAC_RXQCTRL_FPRQ GENMASK(26, 24) -#define GMAC_RXQCTRL_FPRQ_SHIFT 24 =20 /* MAC Packet Filtering */ #define GMAC_PACKET_FILTER_PR BIT(0) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac4_core.c index 4d217926820a..c25781874aa7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -1262,11 +1262,6 @@ const struct stmmac_ops dwmac410_ops =3D { .set_arp_offload =3D dwmac4_set_arp_offload, .config_l3_filter =3D dwmac4_config_l3_filter, .config_l4_filter =3D dwmac4_config_l4_filter, - .fpe_configure =3D dwmac5_fpe_configure, - .fpe_send_mpacket =3D dwmac5_fpe_send_mpacket, - .fpe_irq_status =3D dwmac5_fpe_irq_status, - .fpe_get_add_frag_size =3D dwmac5_fpe_get_add_frag_size, - .fpe_set_add_frag_size =3D dwmac5_fpe_set_add_frag_size, .fpe_map_preemption_class =3D dwmac5_fpe_map_preemption_class, .add_hw_vlan_rx_fltr =3D dwmac4_add_hw_vlan_rx_fltr, .del_hw_vlan_rx_fltr =3D dwmac4_del_hw_vlan_rx_fltr, @@ -1317,11 +1312,6 @@ const struct stmmac_ops dwmac510_ops =3D { .set_arp_offload =3D dwmac4_set_arp_offload, .config_l3_filter =3D dwmac4_config_l3_filter, .config_l4_filter =3D dwmac4_config_l4_filter, - .fpe_configure =3D dwmac5_fpe_configure, - .fpe_send_mpacket =3D dwmac5_fpe_send_mpacket, - .fpe_irq_status =3D dwmac5_fpe_irq_status, - .fpe_get_add_frag_size =3D dwmac5_fpe_get_add_frag_size, - .fpe_set_add_frag_size =3D dwmac5_fpe_set_add_frag_size, .fpe_map_preemption_class =3D dwmac5_fpe_map_preemption_class, .add_hw_vlan_rx_fltr =3D dwmac4_add_hw_vlan_rx_fltr, .del_hw_vlan_rx_fltr =3D dwmac4_del_hw_vlan_rx_fltr, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 917796293c26..efd47db05dbc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -85,7 +85,6 @@ #define XGMAC_MCBCQ GENMASK(11, 8) #define XGMAC_MCBCQ_SHIFT 8 #define XGMAC_RQ GENMASK(7, 4) -#define XGMAC_RQ_SHIFT 4 #define XGMAC_UPQ GENMASK(3, 0) #define XGMAC_UPQ_SHIFT 0 #define XGMAC_RXQ_CTRL2 0x000000a8 @@ -96,6 +95,7 @@ #define XGMAC_LPIIS BIT(5) #define XGMAC_PMTIS BIT(4) #define XGMAC_INT_EN 0x000000b4 +#define XGMAC_FPEIE BIT(15) #define XGMAC_TSIE BIT(12) #define XGMAC_LPIIE BIT(5) #define XGMAC_PMTIE BIT(4) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 111ba5a524ed..de6ffda31a80 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1545,7 +1545,6 @@ const struct stmmac_ops dwxgmac210_ops =3D { .config_l3_filter =3D dwxgmac2_config_l3_filter, .config_l4_filter =3D dwxgmac2_config_l4_filter, .set_arp_offload =3D dwxgmac2_set_arp_offload, - .fpe_configure =3D dwxgmac3_fpe_configure, }; =20 static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode, @@ -1602,7 +1601,6 @@ const struct stmmac_ops dwxlgmac2_ops =3D { .config_l3_filter =3D dwxgmac2_config_l3_filter, .config_l4_filter =3D dwxgmac2_config_l4_filter, .set_arp_offload =3D dwxgmac2_set_arp_offload, - .fpe_configure =3D dwxgmac3_fpe_configure, }; =20 int dwxgmac2_setup(struct stmmac_priv *priv) diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ether= net/stmicro/stmmac/hwif.c index 88cce28b2f98..cfc50289aed6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c @@ -6,6 +6,7 @@ =20 #include "common.h" #include "stmmac.h" +#include "stmmac_fpe.h" #include "stmmac_ptp.h" #include "stmmac_est.h" =20 @@ -185,6 +186,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_GMAC4_OFFSET, .mmc_off =3D MMC_GMAC4_OFFSET, .est_off =3D EST_GMAC4_OFFSET, + .fpe_reg =3D &dwmac5_fpe_reg, }, .desc =3D &dwmac4_desc_ops, .dma =3D &dwmac4_dma_ops, @@ -205,6 +207,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_GMAC4_OFFSET, .mmc_off =3D MMC_GMAC4_OFFSET, .est_off =3D EST_GMAC4_OFFSET, + .fpe_reg =3D &dwmac5_fpe_reg, }, .desc =3D &dwmac4_desc_ops, .dma =3D &dwmac410_dma_ops, @@ -225,6 +228,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_GMAC4_OFFSET, .mmc_off =3D MMC_GMAC4_OFFSET, .est_off =3D EST_GMAC4_OFFSET, + .fpe_reg =3D &dwmac5_fpe_reg, }, .desc =3D &dwmac4_desc_ops, .dma =3D &dwmac410_dma_ops, @@ -246,6 +250,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_XGMAC_OFFSET, .mmc_off =3D MMC_XGMAC_OFFSET, .est_off =3D EST_XGMAC_OFFSET, + .fpe_reg =3D &dwxgmac3_fpe_reg, }, .desc =3D &dwxgmac210_desc_ops, .dma =3D &dwxgmac210_dma_ops, @@ -267,6 +272,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_XGMAC_OFFSET, .mmc_off =3D MMC_XGMAC_OFFSET, .est_off =3D EST_XGMAC_OFFSET, + .fpe_reg =3D &dwxgmac3_fpe_reg, }, .desc =3D &dwxgmac210_desc_ops, .dma =3D &dwxgmac210_dma_ops, @@ -353,6 +359,7 @@ int stmmac_hwif_init(struct stmmac_priv *priv) mac->est =3D mac->est ? : entry->est; =20 priv->hw =3D mac; + priv->fpe_cfg.reg =3D entry->regs.fpe_reg; priv->ptpaddr =3D priv->ioaddr + entry->regs.ptp_off; priv->mmcaddr =3D priv->ioaddr + entry->regs.mmc_off; if (entry->est) diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ether= net/stmicro/stmmac/hwif.h index d5a9f01ecac5..64f8ed67dcc4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h @@ -420,15 +420,6 @@ struct stmmac_ops { bool en, bool udp, bool sa, bool inv, u32 match); void (*set_arp_offload)(struct mac_device_info *hw, bool en, u32 addr); - void (*fpe_configure)(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable); - void (*fpe_send_mpacket)(void __iomem *ioaddr, - struct stmmac_fpe_cfg *cfg, - enum stmmac_mpacket_type type); - int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev); - int (*fpe_get_add_frag_size)(const void __iomem *ioaddr); - void (*fpe_set_add_frag_size)(void __iomem *ioaddr, u32 add_frag_size); int (*fpe_map_preemption_class)(struct net_device *ndev, struct netlink_ext_ack *extack, u32 pclass); @@ -530,16 +521,6 @@ struct stmmac_ops { stmmac_do_callback(__priv, mac, config_l4_filter, __args) #define stmmac_set_arp_offload(__priv, __args...) \ stmmac_do_void_callback(__priv, mac, set_arp_offload, __args) -#define stmmac_fpe_configure(__priv, __args...) \ - stmmac_do_void_callback(__priv, mac, fpe_configure, __args) -#define stmmac_fpe_send_mpacket(__priv, __args...) \ - stmmac_do_void_callback(__priv, mac, fpe_send_mpacket, __args) -#define stmmac_fpe_irq_status(__priv, __args...) \ - stmmac_do_callback(__priv, mac, fpe_irq_status, __args) -#define stmmac_fpe_get_add_frag_size(__priv, __args...) \ - stmmac_do_callback(__priv, mac, fpe_get_add_frag_size, __args) -#define stmmac_fpe_set_add_frag_size(__priv, __args...) \ - stmmac_do_void_callback(__priv, mac, fpe_set_add_frag_size, __args) #define stmmac_fpe_map_preemption_class(__priv, __args...) \ stmmac_do_void_callback(__priv, mac, fpe_map_preemption_class, __args) =20 @@ -678,6 +659,7 @@ struct stmmac_est_ops { stmmac_do_void_callback(__priv, est, irq_status, __args) =20 struct stmmac_regs_off { + const struct stmmac_fpe_reg *fpe_reg; u32 ptp_off; u32 mmc_off; u32 est_off; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index 816b979e72cc..1d86439b8a14 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -152,6 +152,7 @@ struct stmmac_fpe_cfg { */ spinlock_t lock; =20 + const struct stmmac_fpe_reg *reg; u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */ =20 enum ethtool_mm_verify_status status; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers= /net/ethernet/stmicro/stmmac/stmmac_ethtool.c index 2792a4c6cbcd..f2783f7c46f3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c @@ -1294,7 +1294,7 @@ static int stmmac_get_mm(struct net_device *ndev, else state->tx_active =3D false; =20 - frag_size =3D stmmac_fpe_get_add_frag_size(priv, priv->ioaddr); + frag_size =3D stmmac_fpe_get_add_frag_size(priv); state->tx_min_frag_size =3D ethtool_mm_frag_size_add_to_min(frag_size); =20 spin_unlock_irqrestore(&priv->fpe_cfg.lock, flags); @@ -1329,7 +1329,7 @@ static int stmmac_set_mm(struct net_device *ndev, str= uct ethtool_mm_cfg *cfg, if (!cfg->verify_enabled) fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_DISABLED; =20 - stmmac_fpe_set_add_frag_size(priv, priv->ioaddr, frag_size); + stmmac_fpe_set_add_frag_size(priv, frag_size); stmmac_fpe_apply(priv); =20 spin_unlock_irqrestore(&fpe_cfg->lock, flags); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index 4d5a1704ed61..818741579904 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -27,6 +27,21 @@ #define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1) #define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0) =20 +/* FPE link-partner hand-shaking mPacket type */ +enum stmmac_mpacket_type { + MPACKET_VERIFY =3D 0, + MPACKET_RESPONSE =3D 1, +}; + +struct stmmac_fpe_reg { + const u32 mac_fpe_reg; /* offset of MAC_FPE_CTRL_STS */ + const u32 mtl_fpe_reg; /* offset of MTL_FPE_CTRL_STS */ + const u32 rxq_ctrl1_reg; /* offset of MAC_RxQ_Ctrl1 */ + const u32 fprq_mask; /* Frame Preemption Residue Queue */ + const u32 int_en_reg; /* offset of MAC_Interrupt_Enable */ + const u32 int_en_bit; /* Frame Preemption Interrupt Enable */ +}; + void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) { struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; @@ -38,38 +53,34 @@ void stmmac_fpe_link_state_handle(struct stmmac_priv *p= riv, bool is_up) =20 if (is_up && fpe_cfg->pmac_enabled) { /* VERIFY process requires pmac enabled when NIC comes up */ - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - false, true); + stmmac_fpe_configure(priv, false, true); =20 /* New link =3D> maybe new partner =3D> new verification process */ stmmac_fpe_apply(priv); } else { /* No link =3D> turn off EFPE */ - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - false, false); + stmmac_fpe_configure(priv, false, false); } =20 spin_unlock_irqrestore(&fpe_cfg->lock, flags); } =20 -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *= cfg, - enum stmmac_mpacket_type type) +static void stmmac_fpe_send_mpacket(struct stmmac_priv *priv, + enum stmmac_mpacket_type type) { - u32 value =3D cfg->fpe_csr; + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; + u32 value =3D priv->fpe_cfg.fpe_csr; =20 if (type =3D=3D MPACKET_VERIFY) value |=3D STMMAC_MAC_FPE_CTRL_STS_SVER; else if (type =3D=3D MPACKET_RESPONSE) value |=3D STMMAC_MAC_FPE_CTRL_STS_SRSP; =20 - writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS); + writel(value, ioaddr + reg->mac_fpe_reg); } =20 -void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) +static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) { struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; =20 @@ -81,8 +92,7 @@ void stmmac_fpe_event_status(struct stmmac_priv *priv, in= t status) =20 /* LP has sent verify mPacket */ if ((status & FPE_EVENT_RVER) =3D=3D FPE_EVENT_RVER) - stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg, - MPACKET_RESPONSE); + stmmac_fpe_send_mpacket(priv, MPACKET_RESPONSE); =20 /* Local has sent verify mPacket */ if ((status & FPE_EVENT_TVER) =3D=3D FPE_EVENT_TVER && @@ -120,8 +130,7 @@ static void stmmac_fpe_verify_timer(struct timer_list *= t) case ETHTOOL_MM_VERIFY_STATUS_INITIAL: case ETHTOOL_MM_VERIFY_STATUS_VERIFYING: if (fpe_cfg->verify_retries !=3D 0) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - fpe_cfg, MPACKET_VERIFY); + stmmac_fpe_send_mpacket(priv, MPACKET_VERIFY); rearm =3D true; } else { fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_FAILED; @@ -131,10 +140,7 @@ static void stmmac_fpe_verify_timer(struct timer_list = *t) break; =20 case ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED: - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - true, true); + stmmac_fpe_configure(priv, true, true); break; =20 default: @@ -177,10 +183,7 @@ void stmmac_fpe_apply(struct stmmac_priv *priv) * Otherwise let the timer code do it. */ if (!fpe_cfg->verify_enabled) { - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - fpe_cfg->tx_enabled, + stmmac_fpe_configure(priv, fpe_cfg->tx_enabled, fpe_cfg->pmac_enabled); } else { fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_INITIAL; @@ -191,50 +194,55 @@ void stmmac_fpe_apply(struct stmmac_priv *priv) } } =20 -void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable) +void stmmac_fpe_configure(struct stmmac_priv *priv, bool tx_enable, + bool pmac_enable) { + struct stmmac_fpe_cfg *cfg =3D &priv->fpe_cfg; + const struct stmmac_fpe_reg *reg =3D cfg->reg; + u32 num_rxq =3D priv->plat->rx_queues_to_use; + void __iomem *ioaddr =3D priv->ioaddr; u32 value; =20 if (tx_enable) { cfg->fpe_csr =3D STMMAC_MAC_FPE_CTRL_STS_EFPE; - value =3D readl(ioaddr + GMAC_RXQ_CTRL1); - value &=3D ~GMAC_RXQCTRL_FPRQ; - value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; - writel(value, ioaddr + GMAC_RXQ_CTRL1); + value =3D readl(ioaddr + reg->rxq_ctrl1_reg); + value &=3D ~reg->fprq_mask; + /* Keep this SHIFT, FIELD_PREP() expects a constant mask :-/ */ + value |=3D (num_rxq - 1) << __ffs(reg->fprq_mask); + writel(value, ioaddr + reg->rxq_ctrl1_reg); } else { cfg->fpe_csr =3D 0; } - writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS); + writel(cfg->fpe_csr, ioaddr + reg->mac_fpe_reg); =20 - value =3D readl(ioaddr + GMAC_INT_EN); + value =3D readl(ioaddr + reg->int_en_reg); =20 if (pmac_enable) { - if (!(value & GMAC_INT_FPE_EN)) { + if (!(value & reg->int_en_bit)) { /* Dummy read to clear any pending masked interrupts */ - readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); + readl(ioaddr + reg->mac_fpe_reg); =20 - value |=3D GMAC_INT_FPE_EN; + value |=3D reg->int_en_bit; } } else { - value &=3D ~GMAC_INT_FPE_EN; + value &=3D ~reg->int_en_bit; } =20 - writel(value, ioaddr + GMAC_INT_EN); + writel(value, ioaddr + reg->int_en_reg); } =20 -int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) +void stmmac_fpe_irq_status(struct stmmac_priv *priv) { + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; + struct net_device *dev =3D priv->dev; + int status =3D FPE_EVENT_UNKNOWN; u32 value; - int status; - - status =3D FPE_EVENT_UNKNOWN; =20 /* Reads from the MAC_FPE_CTRL_STS register should only be performed * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" */ - value =3D readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); + value =3D readl(ioaddr + reg->mac_fpe_reg); =20 if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) { status |=3D FPE_EVENT_TRSP; @@ -256,22 +264,26 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struc= t net_device *dev) netdev_dbg(dev, "FPE: Verify mPacket is received\n"); } =20 - return status; + stmmac_fpe_event_status(priv, status); } =20 -int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) +int stmmac_fpe_get_add_frag_size(struct stmmac_priv *priv) { - return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, - readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS)); + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; + + return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, readl(ioaddr + reg->mtl_fpe_reg)); } =20 -void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size) +void stmmac_fpe_set_add_frag_size(struct stmmac_priv *priv, u32 add_frag_s= ize) { + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; u32 value; =20 - value =3D readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS); + value =3D readl(ioaddr + reg->mtl_fpe_reg); writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ), - ioaddr + GMAC5_MTL_FPE_CTRL_STS); + ioaddr + reg->mtl_fpe_reg); } =20 #define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mappi= ng" @@ -329,27 +341,20 @@ int dwmac5_fpe_map_preemption_class(struct net_device= *ndev, return 0; } =20 -void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable) -{ - u32 value; - - if (!tx_enable) { - value =3D readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); - - value &=3D ~STMMAC_MAC_FPE_CTRL_STS_EFPE; - - writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); - return; - } - - value =3D readl(ioaddr + XGMAC_RXQ_CTRL1); - value &=3D ~XGMAC_RQ; - value |=3D (num_rxq - 1) << XGMAC_RQ_SHIFT; - writel(value, ioaddr + XGMAC_RXQ_CTRL1); - - value =3D readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); - value |=3D STMMAC_MAC_FPE_CTRL_STS_EFPE; - writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); -} +const struct stmmac_fpe_reg dwmac5_fpe_reg =3D { + .mac_fpe_reg =3D GMAC5_MAC_FPE_CTRL_STS, + .mtl_fpe_reg =3D GMAC5_MTL_FPE_CTRL_STS, + .rxq_ctrl1_reg =3D GMAC_RXQ_CTRL1, + .fprq_mask =3D GMAC_RXQCTRL_FPRQ, + .int_en_reg =3D GMAC_INT_EN, + .int_en_bit =3D GMAC_INT_FPE_EN, +}; + +const struct stmmac_fpe_reg dwxgmac3_fpe_reg =3D { + .mac_fpe_reg =3D XGMAC_MAC_FPE_CTRL_STS, + .mtl_fpe_reg =3D XGMAC_MTL_FPE_CTRL_STS, + .rxq_ctrl1_reg =3D XGMAC_RXQ_CTRL1, + .fprq_mask =3D XGMAC_RQ, + .int_en_reg =3D XGMAC_INT_EN, + .int_en_bit =3D XGMAC_FPEIE, +}; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.h index 25725fd5182f..15fcb9ef1a97 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h @@ -12,34 +12,22 @@ #define STMMAC_FPE_MM_MAX_VERIFY_RETRIES 3 #define STMMAC_FPE_MM_MAX_VERIFY_TIME_MS 128 =20 -/* FPE link-partner hand-shaking mPacket type */ -enum stmmac_mpacket_type { - MPACKET_VERIFY =3D 0, - MPACKET_RESPONSE =3D 1, -}; - struct stmmac_priv; struct stmmac_fpe_cfg; =20 void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up); -void stmmac_fpe_event_status(struct stmmac_priv *priv, int status); void stmmac_fpe_init(struct stmmac_priv *priv); void stmmac_fpe_apply(struct stmmac_priv *priv); +void stmmac_fpe_configure(struct stmmac_priv *priv, bool tx_enable, + bool pmac_enable); +void stmmac_fpe_irq_status(struct stmmac_priv *priv); +int stmmac_fpe_get_add_frag_size(struct stmmac_priv *priv); +void stmmac_fpe_set_add_frag_size(struct stmmac_priv *priv, u32 add_frag_s= ize); =20 -void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable); -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, - struct stmmac_fpe_cfg *cfg, - enum stmmac_mpacket_type type); -int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev); -int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr); -void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size); int dwmac5_fpe_map_preemption_class(struct net_device *ndev, struct netlink_ext_ack *extack, u32 pclass); =20 -void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable); +extern const struct stmmac_fpe_reg dwmac5_fpe_reg; +extern const struct stmmac_fpe_reg dwxgmac3_fpe_reg; =20 #endif diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index ab547430a717..9fcf2df099ec 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -5943,12 +5943,8 @@ static void stmmac_common_interrupt(struct stmmac_pr= iv *priv) stmmac_est_irq_status(priv, priv, priv->dev, &priv->xstats, tx_cnt); =20 - if (priv->dma_cap.fpesel) { - int status =3D stmmac_fpe_irq_status(priv, priv->ioaddr, - priv->dev); - - stmmac_fpe_event_status(priv, status); - } + if (priv->dma_cap.fpesel) + stmmac_fpe_irq_status(priv); =20 /* To handle GMAC own interrupts */ if ((priv->plat->has_gmac) || xmac) { --=20 2.34.1