From nobody Wed Dec 17 05:26:52 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0E4EEE4993 for ; Wed, 23 Aug 2023 10:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233666AbjHWKDB (ORCPT ); Wed, 23 Aug 2023 06:03:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233559AbjHWJsH (ORCPT ); Wed, 23 Aug 2023 05:48:07 -0400 Received: from jari.cn (unknown [218.92.28.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 129FD6A6B for ; Wed, 23 Aug 2023 02:20:03 -0700 (PDT) Received: from chenxuebing$jari.cn ( [125.70.163.142] ) by ajax-webmail-localhost.localdomain (Coremail) ; Wed, 23 Aug 2023 17:19:38 +0800 (GMT+08:00) X-Originating-IP: [125.70.163.142] Date: Wed, 23 Aug 2023 17:19:38 +0800 (GMT+08:00) X-CM-HeaderCharset: UTF-8 From: "XueBing Chen" To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amdgpu: Clean up errors in mxgpu_ai.c X-Priority: 3 X-Mailer: Coremail Webmail Server Version 2023.1-cmXT6 build 20230419(ff23bf83) Copyright (c) 2002-2023 www.mailtech.cn mispb-4e503810-ca60-4ec8-a188-7102c18937cf-zhkzyfz.cn Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Message-ID: <1c0204f7.623.18a21b13e92.Coremail.chenxuebing@jari.cn> X-Coremail-Locale: zh_CN X-CM-TRANSID: AQAAfwDXaD4qz+VkOmiQAA--.421W X-CM-SenderInfo: hfkh05pxhex0nj6mt2flof0/1tbiAQAMCmTkgo0AUAAEsc X-Coremail-Antispam: 1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw CS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI daVFxhVjvjDU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: open brace '{' following function definitions go on the next line ERROR: space required before the open parenthesis '(' ERROR: space required before the open brace '{' ERROR: trailing whitespace ERROR: switch and case should be at the same indent Signed-off-by: XueBing Chen --- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/am= dgpu/mxgpu_ai.c index 63725b2ebc03..9941c1f69658 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -75,7 +75,8 @@ static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *= adev, return 0; } =20 -static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) { +static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) +{ return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; } =20 @@ -117,7 +118,8 @@ static int xgpu_ai_poll_msg(struct amdgpu_device *adev,= enum idh_event event) } =20 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev, - enum idh_request req, u32 data1, u32 data2, u32 data3) { + enum idh_request req, u32 data1, u32 data2, u32 data3) +{ u32 reg; int r; uint8_t trn; @@ -135,7 +137,7 @@ static void xgpu_ai_mailbox_trans_msg (struct amdgpu_de= vice *adev, pr_err("trn=3D%x ACK should not assert! wait again !\n", trn); msleep(1); } - } while(trn); + } while (trn); =20 reg =3D RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0)); @@ -182,11 +184,11 @@ static int xgpu_ai_send_access_requests(struct amdgpu= _device *adev, RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2)); } - } else if (req =3D=3D IDH_REQ_GPU_INIT_DATA){ + } else if (req =3D=3D IDH_REQ_GPU_INIT_DATA) { /* Dummy REQ_GPU_INIT_DATA handling */ r =3D xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY); /* version set to 0 since dummy */ - adev->virt.req_init_data_ver =3D 0;=09 + adev->virt.req_init_data_ver =3D 0; } =20 return 0; @@ -316,14 +318,14 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_devi= ce *adev, enum idh_event event =3D xgpu_ai_mailbox_peek_msg(adev); =20 switch (event) { - case IDH_FLR_NOTIFICATION: + case IDH_FLR_NOTIFICATION: if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev)) WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain, &adev->virt.flr_work), "Failed to queue work! at %s", __func__); break; - case IDH_QUERY_ALIVE: + case IDH_QUERY_ALIVE: xgpu_ai_mailbox_send_ack(adev); break; /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore @@ -333,7 +335,7 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device= *adev, case IDH_CLR_MSG_BUF: case IDH_FLR_NOTIFICATION_CMPL: case IDH_READY_TO_ACCESS_GPU: - default: + default: break; } =20 --=20 2.17.1