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Wysocki" To: Linux PM Cc: LKML , Lukasz Luba , Peter Zijlstra , Srinivas Pandruvada , Dietmar Eggemann , Morten Rasmussen , Vincent Guittot , Ricardo Neri , Pierre Gondois , Christian Loehle , Tim Chen Subject: [RFT][PATCH v1 7/8] cpufreq: intel_pstate: Align perf domains with L2 cache Date: Wed, 16 Apr 2025 20:10:50 +0200 Message-ID: <1964444.taCxCBeP46@rjwysocki.net> In-Reply-To: <3344336.aeNJFYEL58@rjwysocki.net> References: <3344336.aeNJFYEL58@rjwysocki.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CLIENT-IP: 195.136.19.94 X-CLIENT-HOSTNAME: 195.136.19.94 X-VADE-SPAMSTATE: clean X-VADE-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgddvvdejtdeiucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecujffqoffgrffnpdggtffipffknecuuegrihhlohhuthemucduhedtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufffkfgjfhgggfgtsehtufertddttdejnecuhfhrohhmpedftfgrfhgrvghlucflrdcuhgihshhotghkihdfuceorhhjfiesrhhjfiihshhotghkihdrnhgvtheqnecuggftrfgrthhtvghrnhepvdffueeitdfgvddtudegueejtdffteetgeefkeffvdeftddttdeuhfegfedvjefhnecukfhppeduleehrddufeeirdduledrleegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepudelhedrudefiedrudelrdelgedphhgvlhhopehkrhgvrggthhgvrhdrlhhotggrlhhnvghtpdhmrghilhhfrhhomheprhhjfiesrhhjfiihshhotghkihdrnhgvthdpnhgspghrtghpthhtohepuddvpdhrtghpthhtoheplhhinhhugidqphhmsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhukhgrshiirdhluhgsrgesrghrmhdrtghomhdprhgtphhtthhopehpvghtvghriiesihhnfhhrrgguvggrugdrohhrghdprhgtphhtthhopehsrhhinhhivhgrshdrphgrnhgurhhuvhgruggrsehlihhnuhigrdh X-DCC--Metrics: v370.home.net.pl 1024; Body=12 Fuz1=12 Fuz2=12 Content-Type: text/plain; charset="utf-8" From: Rafael J. Wysocki On some hybrid platforms a group of cores (referred to as a module) may share an L2 cache in which case they also share a voltage regulator and always run at the same frequency (while not in idle states). For this reason, make hybrid_register_perf_domain() in the intel_pstate driver add all CPUs sharing an L2 cache to the same perf domain for EAS. Signed-off-by: Rafael J. Wysocki --- New in v1. --- drivers/cpufreq/intel_pstate.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -999,8 +999,11 @@ { static const struct em_data_callback cb =3D EM_ADV_DATA_CB(hybrid_active_power, hybrid_get_cost); + struct cpu_cacheinfo *cacheinfo =3D get_cpu_cacheinfo(cpu); + const struct cpumask *cpumask =3D cpumask_of(cpu); struct cpudata *cpudata =3D all_cpu_data[cpu]; struct device *cpu_dev; + int ret; =20 /* * Registering EM perf domains without enabling asymmetric CPU capacity @@ -1014,9 +1017,25 @@ if (!cpu_dev) return false; =20 - if (em_dev_register_perf_domain(cpu_dev, HYBRID_EM_STATE_COUNT, &cb, - cpumask_of(cpu), false)) + if (cacheinfo) { + unsigned int i; + + /* Find the L2 cache and the CPUs sharing it. */ + for (i =3D 0; i < cacheinfo->num_leaves; i++) { + if (cacheinfo->info_list[i].level =3D=3D 2) { + cpumask =3D &cacheinfo->info_list[i].shared_cpu_map; + break; + } + } + } + + ret =3D em_dev_register_perf_domain(cpu_dev, HYBRID_EM_STATE_COUNT, &cb, + cpumask, false); + if (ret) { + cpudata->em_registered =3D ret =3D=3D -EEXIST; + return false; + } =20 cpudata->em_registered =3D true;