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(unknown [121.237.244.238]) by APP-01 (Coremail) with SMTP id qwCowABX7Mtv8yxp69+vAg--.18496S2; Mon, 01 Dec 2025 09:46:24 +0800 (CST) From: zhouquan@iscas.ac.cn To: anup@brainfault.org, ajones@ventanamicro.com, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Quan Zhou Subject: [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features Date: Mon, 1 Dec 2025 09:28:48 +0800 Message-Id: <1793aa636969da0a09d27c9c12f6d5f8f0d1cd21.1764509485.git.zhouquan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowABX7Mtv8yxp69+vAg--.18496S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtw1xGr1UXF47Zr1rWryDJrb_yoW7tw4UpF WxWF9rWayfJr9Y93ZYyrsrWFWYgws7K3ZFyay7G34FvFy2kF45JF1kKr9rAryDA340vFWS kF4qqF1UCrs0v3JanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7Cj xVA2Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVAFwV WkMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_ Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x 0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8 JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIx AIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjiSdPUUUUU= = X-CM-SenderInfo: 52kr31xxdqqxpvfd2hldfou0/1tbiDAgDBmks7K0aZgAAs5 Content-Type: text/plain; charset="utf-8" From: Quan Zhou Add support in KVM SBI FWFT extension to allow VS-mode to request SBI_FWFT_{LANDING_PAD/SHADOW_STACK/PTE_AD_HW_UPDATING}. Signed-off-by: Quan Zhou --- arch/riscv/include/uapi/asm/kvm.h | 3 + arch/riscv/kvm/vcpu_sbi_fwft.c | 129 ++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 7ca087848a43..d93b70d89010 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -232,6 +232,9 @@ struct kvm_riscv_sbi_fwft_feature { struct kvm_riscv_sbi_fwft { struct kvm_riscv_sbi_fwft_feature misaligned_deleg; struct kvm_riscv_sbi_fwft_feature pointer_masking; + struct kvm_riscv_sbi_fwft_feature landing_pad; + struct kvm_riscv_sbi_fwft_feature shadow_stack; + struct kvm_riscv_sbi_fwft_feature pte_ad_hw_updating; }; =20 /* Possible states for kvm_riscv_timer */ diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 62cc9c3d5759..0dc0e70fc83b 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -213,6 +213,108 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu, return SBI_SUCCESS; } =20 +static long kvm_sbi_fwft_set_henvcfg_flag(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value, + unsigned long flag) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + if (value =3D=3D 1) + cfg->henvcfg |=3D flag; + else if (value =3D=3D 0) + cfg->henvcfg &=3D ~flag; + else + return SBI_ERR_INVALID_PARAM; + + if (!one_reg_access) + csr_write(CSR_HENVCFG, cfg->henvcfg); + + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_pointer_landing_pad_supported(struct kvm_vcpu *vc= pu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, ZICFILP); +} + +static void kvm_sbi_fwft_reset_landing_pad(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_LPE; +} + +static long kvm_sbi_fwft_set_landing_pad(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, E= NVCFG_LPE); +} + +static long kvm_sbi_fwft_get_landing_pad(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + *value =3D (cfg->henvcfg & ENVCFG_LPE) =3D=3D ENVCFG_LPE; + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_pointer_shadow_stack_supported(struct kvm_vcpu *v= cpu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, ZICFISS); +} + +static void kvm_sbi_fwft_reset_shadow_stack(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_SSE; +} + +static long kvm_sbi_fwft_set_shadow_stack(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, E= NVCFG_SSE); +} + +static long kvm_sbi_fwft_get_shadow_stack(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + *value =3D (cfg->henvcfg & ENVCFG_SSE) =3D=3D ENVCFG_SSE; + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_pointer_pte_ad_hw_updating_supported(struct kvm_v= cpu *vcpu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, SVADU) && + !riscv_isa_extension_available(vcpu->arch.isa, SVADE); +} + +static void kvm_sbi_fwft_reset_pte_ad_hw_updating(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_ADUE; +} + +static long kvm_sbi_fwft_set_pte_ad_hw_updating(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, E= NVCFG_ADUE); +} + +static long kvm_sbi_fwft_get_pte_ad_hw_updating(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + *value =3D (cfg->henvcfg & ENVCFG_ADUE) =3D=3D ENVCFG_ADUE; + return SBI_SUCCESS; +} + #endif =20 static const struct kvm_sbi_fwft_feature features[] =3D { @@ -236,6 +338,33 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { .get =3D kvm_sbi_fwft_get_pointer_masking_pmlen, }, #endif + { + .id =3D SBI_FWFT_LANDING_PAD, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, landing_pad.enabl= e) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_landing_pad_supported, + .reset =3D kvm_sbi_fwft_reset_landing_pad, + .set =3D kvm_sbi_fwft_set_landing_pad, + .get =3D kvm_sbi_fwft_get_landing_pad, + }, + { + .id =3D SBI_FWFT_SHADOW_STACK, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, shadow_stack.enab= le) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_shadow_stack_supported, + .reset =3D kvm_sbi_fwft_reset_shadow_stack, + .set =3D kvm_sbi_fwft_set_shadow_stack, + .get =3D kvm_sbi_fwft_get_shadow_stack, + }, + { + .id =3D SBI_FWFT_PTE_AD_HW_UPDATING, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pte_ad_hw_updatin= g.enable) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_pte_ad_hw_updating_supported, + .reset =3D kvm_sbi_fwft_reset_pte_ad_hw_updating, + .set =3D kvm_sbi_fwft_set_pte_ad_hw_updating, + .get =3D kvm_sbi_fwft_get_pte_ad_hw_updating, + }, }; =20 static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(u= nsigned long reg_num) --=20 2.34.1